JP2002329964A - Method of manufacturing multilayer printed wiring board - Google Patents

Method of manufacturing multilayer printed wiring board

Info

Publication number
JP2002329964A
JP2002329964A JP2001130642A JP2001130642A JP2002329964A JP 2002329964 A JP2002329964 A JP 2002329964A JP 2001130642 A JP2001130642 A JP 2001130642A JP 2001130642 A JP2001130642 A JP 2001130642A JP 2002329964 A JP2002329964 A JP 2002329964A
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
multilayer printed
manufacturing
reference hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001130642A
Other languages
Japanese (ja)
Inventor
Wakana Aizawa
和佳奈 相澤
Kenji Hyodo
建二 兵頭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Paper Mills Ltd
Original Assignee
Mitsubishi Paper Mills Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Paper Mills Ltd filed Critical Mitsubishi Paper Mills Ltd
Priority to JP2001130642A priority Critical patent/JP2002329964A/en
Publication of JP2002329964A publication Critical patent/JP2002329964A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method of getting a highly accurate printed wiring board by suppressing misregistration simply, in a manufacturing method for a multilayer printed wiring board. SOLUTION: A reference hole in a layer lower than wiring formation layers 5 and 6 is filled with magnetic substances 4, and register with a lamination matter is performed by visualizing the reference hole on the wiring formation layers 5 and 6 by magnetic particles.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は多層プリント配線板
の製造方法に関し、配線形成層と露光マスクとの位置合
わせ、内層基板の積層時の位置合わせ、ビアホールやス
ルーホール穿孔作業時の位置合わせ等、各種位置合わせ
を精度良く行う方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed wiring board, and more particularly to a method for aligning a wiring forming layer and an exposure mask, aligning an inner layer substrate when laminating, and aligning a via hole and a through hole. And a method for performing various alignments with high accuracy.

【0002】[0002]

【従来の技術】多層プリント配線板は、配線を形成した
内層基板とプリプレグおよび外層用基板を積層した後
に、スルーホールや外層配線を形成する積層法や、内層
基板の配線形成層上に絶縁層を塗布し、バイアホールを
形成した後、銅めっき等によって銅層を形成し、次いで
この銅層を用いて配線を形成した後、さらに絶縁層を塗
布して上層配線基板を積み重ねていくビルドアップ法等
によって製造される。
2. Description of the Related Art A multilayer printed wiring board is formed by laminating an inner layer substrate on which wiring is formed, a prepreg, and a substrate for an outer layer, and then forming a through hole or an outer layer wiring, or an insulating layer on the wiring forming layer of the inner layer substrate. After forming via holes, forming a copper layer by copper plating etc., then forming wiring using this copper layer, further applying an insulating layer and building up the upper wiring board It is manufactured by a method or the like.

【0003】多層プリント配線板を製造する場合、各層
の配線位置やスルーホールの位置を精確に合わせること
が重要である。位置合わせ方法としては、基準孔を用い
た方法が一般的である。基準孔方式は、内層基板に設け
た内層基準孔を基にして、以降の製造工程全ての位置合
わせを行うことで、配線やスルーホールの位置ずれを抑
制する方法である。
When a multilayer printed wiring board is manufactured, it is important to accurately adjust the wiring position of each layer and the position of a through hole. As a positioning method, a method using a reference hole is generally used. The reference hole method is a method of performing alignment in all of the subsequent manufacturing steps based on the inner layer reference hole provided in the inner layer substrate, thereby suppressing the displacement of the wiring and the through hole.

【0004】例えば、まず、内層基板に基準孔を設け、
該基準孔と内層配線製造用露光マスク上の位置合わせマ
ークとを合わせて、第一の内層基板に配線を形成する。
これに、片面銅張積層板を重ねて、内層基板の基準孔を
X線等で確認しながら、ビアホールやスルーホールの形
成、銅めっき処理、レジストおよび露光マスクを用いた
配線形成処理を行い、多層プリント配線板を製造する。
また、内層基板および外層基板の両方に基準孔を設けて
おき、該基準孔にガイドピンを挿入固定して熱圧着し、
次いでスルーホールや外層配線形成を行う方法もある。
しかしながら、X線による基準孔の確認はX線装置の管
理が難しいといった欠点がある。内層基板および外層基
板の両方に基準孔を設ける方法では、積層して熱圧着し
た際に、内層基板と外層基板の熱収縮率の違いから基準
孔の位置にずれが生じたり、基準孔の形が変わってしま
うという問題があった。また、多層プリント配線板の配
線密度と層数が高くなるにつれて、この基準孔のずれが
大きくなるという問題もあった。
For example, first, a reference hole is provided in an inner layer substrate,
The reference hole is aligned with the alignment mark on the exposure mask for manufacturing an inner layer wiring to form a wiring on the first inner layer substrate.
On this, a single-sided copper-clad laminate is stacked, and while confirming the reference hole of the inner layer substrate by X-rays or the like, formation of via holes and through holes, copper plating processing, wiring formation processing using a resist and an exposure mask are performed, Manufacture multilayer printed wiring boards.
In addition, a reference hole is provided in both the inner layer substrate and the outer layer substrate, and a guide pin is inserted and fixed in the reference hole and thermocompression-bonded,
Next, there is a method of forming a through hole or an outer layer wiring.
However, confirmation of the reference hole by X-ray has a disadvantage that it is difficult to manage the X-ray apparatus. In the method of providing the reference holes in both the inner layer substrate and the outer layer substrate, when laminating and thermocompression bonding, the difference in the heat shrinkage between the inner layer substrate and the outer layer substrate causes a shift in the position of the reference hole or the shape of the reference hole. There was a problem that would change. In addition, there has been a problem that as the wiring density and the number of layers of the multilayer printed wiring board increase, the displacement of the reference holes increases.

【0005】[0005]

【発明が解決しようとする課題】本発明の課題は、多層
プリント配線板の製造方法において、位置合わせのずれ
を抑制し、精度の高いプリント配線板を得る方法を提供
する。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a multilayer printed wiring board, which suppresses misalignment and obtains a printed wiring board with high accuracy.

【0006】[0006]

【課題を解決するための手段】本発明者らは鋭意検討し
た結果、多層プリント配線板の製造方法において、予め
配線形成層よりも下層の基準孔に磁性体を充填し、磁性
体粒子によって配線形成層上に該基準孔を可視化させ
て、積層物との位置合わせを行えば良いことを見出し
た。本発明によれば、内層基板の基準孔の位置を常に配
線形成層である最外層基板上で確認できるので、簡易に
位置確認をすることができる。また、外層基板と内層基
板の位置がずれたり、外層基板の基準孔の形が変わって
しまっても、精確に基準孔の位置を確認することが可能
である。
Means for Solving the Problems As a result of intensive studies, the present inventors have found that in a method for manufacturing a multilayer printed wiring board, a magnetic material is filled in advance in a reference hole below a wiring forming layer, and wiring is performed by magnetic particles. It has been found that the reference holes may be visualized on the formation layer and alignment with the laminate may be performed. According to the present invention, since the position of the reference hole of the inner layer substrate can always be confirmed on the outermost layer substrate which is the wiring forming layer, the position can be easily confirmed. Further, even if the position of the outer layer substrate and the inner layer substrate is shifted or the shape of the reference hole of the outer layer substrate is changed, the position of the reference hole can be accurately confirmed.

【0007】[0007]

【発明の実施の形態】本発明を詳説する。図1、プリン
ト配線板の概略図であり、2が基準孔、3が製品領域で
ある。本発明では、図14に示したように、多層プリン
ト配線板の配線形成層よりも下層の内層基板に設けた基
準孔に、磁性体を充填しておく。その後、積層法やビル
ドアップ法によって、層数を増やしていき、各層上に配
線を形成する際には、該配線形成層上に磁性体粒子11
によって基準孔を可視化させて、例えば露光マスクの位
置合わせを行ったり、バイアホールやスルーホールをレ
ーザーで開けるときの位置照合基準として使用する。最
終的に、図1のプリント配線板1において、製品領域3
以外は廃棄されるので、磁性体を充填した基準孔4や、
基準孔の位置を可視化するために用いた磁性体粒子11
が製品に悪影響を及ぼすことはない。
DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in detail. FIG. 1 is a schematic view of a printed wiring board, where 2 is a reference hole and 3 is a product area. In the present invention, as shown in FIG. 14, a magnetic material is filled in a reference hole provided in an inner layer substrate below a wiring forming layer of a multilayer printed wiring board. Thereafter, the number of layers is increased by a lamination method or a build-up method. When wiring is formed on each layer, the magnetic particles 11 are formed on the wiring forming layer.
Thus, the reference holes are visualized, and are used, for example, as a position reference for aligning an exposure mask or opening a via hole or a through hole with a laser. Finally, in the printed wiring board 1 of FIG.
Are discarded, so that the reference hole 4 filled with the magnetic material,
Magnetic particles 11 used to visualize the position of the reference hole
Does not adversely affect the product.

【0008】[0008]

【実施例】以下、本発明を実施例によって詳説するが、
本発明はその主旨を超えない限り下記実施例に限定され
るものではない。
Hereinafter, the present invention will be described in detail with reference to Examples.
The present invention is not limited to the following examples as long as the gist is not exceeded.

【0009】図2〜図13は、本発明の実施例の一形態
を工程順に示した断面図である。まず、図2に示したよ
うに、第1の内層基板用両面銅張積層板に基準孔2aを
開ける。次いで、図3に示したように、公知の方法で、
レジスト材料を用いて、第1の内層基板8に配線を形成
する。このレジスト材料を用いて配線を形成する場合、
基準孔2aと内層配線形成用露光マスクの位置合わせマ
ークとで位置合わせを行う。
2 to 13 are sectional views showing one embodiment of the present invention in the order of steps. First, as shown in FIG. 2, a reference hole 2a is formed in the first double-sided copper-clad laminate for an inner substrate. Then, as shown in FIG. 3, by a known method,
Wiring is formed on the first inner substrate 8 using a resist material. When wiring is formed using this resist material,
Positioning is performed using the reference holes 2a and the positioning marks of the exposure mask for forming the inner layer wiring.

【0010】同様にして、配線パターンの異なる第2の
内層基板9を製造したあと、第2の内層基板の基準孔に
磁性体を充填する(4b)。図4に示したように、第2
の内層基板上に絶縁層(プリプレグ)10を重ね、該プ
リプレグ上に磁性体粒子11で基準孔の位置を可視化さ
せたものと、第1の内層基板の基準孔2aを合わせて、
積層する。図5に示したように、該積層体を真空加圧接
着した後、第1の内層基板8の基準孔に磁性体を充填す
る(4a)。
Similarly, after manufacturing the second inner substrate 9 having a different wiring pattern, a magnetic material is filled into the reference holes of the second inner substrate (4b). As shown in FIG.
The insulating layer (prepreg) 10 is superimposed on the inner substrate, and the positions of the reference holes visualized by the magnetic particles 11 on the prepreg are aligned with the reference holes 2a of the first inner substrate.
Laminate. As shown in FIG. 5, after the laminate is bonded by vacuum pressure, a magnetic material is filled into the reference hole of the first inner layer substrate 8 (4a).

【0011】次に、図6に示したように、バイアホール
12を穿孔する。このとき、基準孔4aおよび4bを位
置合わせに使用する。続いて、図7および図8に示した
ように、全面にパネルめっきを施し、レジスト材料を用
いて、積層体13表面に配線を形成する。このレジスト
材料を用いて配線を形成する場合、図7のように、基準
孔4aおよび基準孔4bの位置を銅層上に磁性体粒子1
1で可視化させて、露光マスクの位置合わせマークとの
位置合わせに使用する。
Next, as shown in FIG. 6, a via hole 12 is formed. At this time, the reference holes 4a and 4b are used for positioning. Subsequently, as shown in FIGS. 7 and 8, the entire surface is subjected to panel plating, and a wiring is formed on the surface of the stacked body 13 using a resist material. When wiring is formed using this resist material, as shown in FIG. 7, the positions of the reference holes 4a and 4b are aligned with the magnetic particles 1 on the copper layer.
It is visualized by 1 and used for alignment with the alignment mark of the exposure mask.

【0012】さらに、図9のように、積層体13と片面
銅張積層板14aおよび14bを真空加圧積層した後、
磁性体粒子11で銅層上に基準孔4aの位置を可視化さ
せ、図10に示したように、これを基準にスルーホール
16を穿孔する。次いで、図11に示したように、全面
にパネルめっきをした後、磁性体粒子11で銅層上に基
準孔4aおよび4bの位置を可視化させる。この磁性体
粒子11と露光マスクとの位置合わせを行いながらレジ
スト材料を用いて、図12のように、最外層の配線パタ
ーンを形成する。最終的に図13に示したように、基準
孔4aおよび4bが存在する領域を廃棄して、最終製品
とする。
Further, as shown in FIG. 9, after the laminate 13 and the single-sided copper-clad laminates 14a and 14b are laminated under vacuum and pressure,
The position of the reference hole 4a is visualized on the copper layer with the magnetic particles 11, and as shown in FIG. 10, a through hole 16 is formed based on the reference hole 4a. Next, as shown in FIG. 11, after the entire surface is plated, the positions of the reference holes 4a and 4b are visualized on the copper layer with the magnetic particles 11. As shown in FIG. 12, a wiring pattern of the outermost layer is formed using the resist material while aligning the magnetic particles 11 with the exposure mask. Finally, as shown in FIG. 13, the area where the reference holes 4a and 4b exist is discarded to obtain a final product.

【0013】この実施例の多層プリント配線板の製造方
法では、X線装置等を使用することなく、位置合わせを
行うことができた。また、内層基板8と最外層基板との
ずれが、ガイドピンを用いた方法では、平均10μmで
あったが、本発明の方法では、平均3μmであり、より
精確なプリント配線板が得られることを確認した。
In the method of manufacturing a multilayer printed wiring board according to this embodiment, the positioning can be performed without using an X-ray apparatus or the like. In addition, the deviation between the inner layer substrate 8 and the outermost layer substrate was 10 μm on average in the method using the guide pins, but was 3 μm on average in the method of the present invention, so that a more accurate printed wiring board could be obtained. It was confirmed.

【0014】[0014]

【発明の効果】以上説明したごとく、本発明のプリント
配線板の製造方法では、全ての工程で内層基板の基準孔
の位置を容易かつ精確に把握することができるので、高
精度のプリント配線板を得ることができるという秀逸な
効果をもたらす。
As described above, in the method for manufacturing a printed wiring board of the present invention, the position of the reference hole of the inner layer substrate can be easily and accurately grasped in all the steps, so that a high-precision printed wiring board can be obtained. Has an excellent effect that can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の多層プリント配線板の製造方法におい
て、基準孔設定位置の一例を表す概略図。
FIG. 1 is a schematic diagram illustrating an example of a reference hole setting position in a method for manufacturing a multilayer printed wiring board according to the present invention.

【図2】本発明の一実施例において、多層プリント配線
板の製造方法における一工程を示す断面図。
FIG. 2 is a cross-sectional view showing one step in a method for manufacturing a multilayer printed wiring board in one embodiment of the present invention.

【図3】本発明の一実施例において、多層プリント配線
板の製造方法における図2に続く工程を示す断面図。
FIG. 3 is a sectional view showing a step following the step shown in FIG. 2 in the method for manufacturing a multilayer printed wiring board in one embodiment of the present invention.

【図4】本発明の一実施例において、多層プリント配線
板の製造方法における図3に続く工程を示す断面図。
FIG. 4 is a sectional view showing a step following the step shown in FIG. 3 in the method for manufacturing a multilayer printed wiring board in one embodiment of the present invention.

【図5】本発明の一実施例において、多層プリント配線
板の製造方法における図4に続く工程を示す断面図。
FIG. 5 is a sectional view showing a step following the step shown in FIG. 4 in the method for manufacturing a multilayer printed wiring board in one embodiment of the present invention.

【図6】本発明の一実施例において、多層プリント配線
板の製造方法における図5に続く工程を示す断面図。
FIG. 6 is a sectional view showing a step following the step shown in FIG. 5 in the method of manufacturing the multilayer printed wiring board in one embodiment of the present invention.

【図7】本発明の一実施例において、多層プリント配線
板の製造方法における図6に続く工程を示す断面図。
FIG. 7 is a sectional view showing a step following FIG. 6 in the method of manufacturing the multilayer printed wiring board in one embodiment of the present invention.

【図8】本発明の一実施例において、多層プリント配線
板の製造方法における図7に続く工程を示す断面図。
FIG. 8 is a sectional view showing a step following the step shown in FIG. 7 in the method of manufacturing the multilayer printed wiring board in one embodiment of the present invention.

【図9】本発明の一実施例において、多層プリント配線
板の製造方法における図8に続く工程を示す断面図。
FIG. 9 is a sectional view showing a step following the step shown in FIG. 8 in the method of manufacturing the multilayer printed wiring board in one embodiment of the present invention.

【図10】本発明の一実施例において、多層プリント配
線板の製造方法における図9に続く工程を示す断面図。
FIG. 10 is a sectional view showing a step following the step shown in FIG. 9 in the method of manufacturing the multilayer printed wiring board in one embodiment of the present invention.

【図11】本発明の一実施例において、多層プリント配
線板の製造方法における図10に続く工程を示す断面
図。
FIG. 11 is a sectional view showing a step following the step in FIG. 10 in the method of manufacturing the multilayer printed wiring board in one embodiment of the present invention.

【図12】本発明の一実施例において、多層プリント配
線板の製造方法における図11に続く工程を示す断面
図。
FIG. 12 is a cross-sectional view showing a step following the step shown in FIG. 11 in the method of manufacturing the multilayer printed wiring board in one embodiment of the present invention.

【図13】本発明の一実施例において、多層プリント配
線板の製造方法における図12に続く工程を示す断面
図。
FIG. 13 is a sectional view showing a step following the step shown in FIG. 12 in the method of manufacturing the multilayer printed wiring board in one embodiment of the present invention.

【図14】本発明の多層プリント配線板の製造方法にお
いて、配線形成層に内層基板の基準孔位置を可視化させ
る方法を示した概略断面図。
FIG. 14 is a schematic cross-sectional view showing a method of visualizing a reference hole position of an inner layer substrate in a wiring forming layer in a method of manufacturing a multilayer printed wiring board of the present invention.

【符号の説明】[Explanation of symbols]

1 プリント基板 2、2a、2b 基準孔 3 製品領域 4、4a、4b 磁性体を充填した基準孔 5 銅層 6 絶縁層 7 内層基板スルーホール 8 第1の内層基板 9 第2の内層基板 10 絶縁層(プリプレグ) 11 磁性体粒子 12 バイアホール 13 積層体 14a、14b 片面銅張積層板 15 積層体 16 スルーホール DESCRIPTION OF SYMBOLS 1 Printed circuit board 2, 2a, 2b Reference hole 3 Product area 4, 4a, 4b Reference hole filled with magnetic material 5 Copper layer 6 Insulating layer 7 Inner substrate through hole 8 First inner substrate 9 Second inner substrate 10 Insulation Layer (prepreg) 11 Magnetic particles 12 Via hole 13 Laminated body 14a, 14b Single-sided copper-clad laminate 15 Laminated body 16 Through hole

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 多層プリント配線板の製造方法におい
て、予め配線形成層よりも下層の基準孔に磁性体を充填
し、磁性体粒子によって配線形成層上に該基準孔を可視
化させて、積層物との位置合わせを行うことを特徴とす
る多層プリント配線板の製造方法。
In a method for manufacturing a multilayer printed wiring board, a reference material below a wiring formation layer is filled with a magnetic substance in advance, and the reference holes are visualized on the wiring formation layer by magnetic particles to form a laminate. A method for manufacturing a multilayer printed wiring board, comprising:
JP2001130642A 2001-04-27 2001-04-27 Method of manufacturing multilayer printed wiring board Pending JP2002329964A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001130642A JP2002329964A (en) 2001-04-27 2001-04-27 Method of manufacturing multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001130642A JP2002329964A (en) 2001-04-27 2001-04-27 Method of manufacturing multilayer printed wiring board

Publications (1)

Publication Number Publication Date
JP2002329964A true JP2002329964A (en) 2002-11-15

Family

ID=18978974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001130642A Pending JP2002329964A (en) 2001-04-27 2001-04-27 Method of manufacturing multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JP2002329964A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005029933A1 (en) * 2003-09-18 2005-03-31 Mitsubishi Denki Kabushiki Kaisha Multilayer printed wiring board and method for manufacturing same
WO2005086553A1 (en) * 2004-03-03 2005-09-15 Sanyo Electric Co., Ltd. Multilayer board manufacturing method
JP2015056445A (en) * 2013-09-10 2015-03-23 コーア株式会社 Method for manufacturing part built-in type substrate
JP2015056547A (en) * 2013-09-12 2015-03-23 コーア株式会社 Method for manufacturing part built-in type substrate

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005029933A1 (en) * 2003-09-18 2005-03-31 Mitsubishi Denki Kabushiki Kaisha Multilayer printed wiring board and method for manufacturing same
WO2005086553A1 (en) * 2004-03-03 2005-09-15 Sanyo Electric Co., Ltd. Multilayer board manufacturing method
JPWO2005086553A1 (en) * 2004-03-03 2008-01-24 三洋電機株式会社 Multilayer substrate manufacturing method
KR100861137B1 (en) * 2004-03-03 2008-09-30 산요덴키가부시키가이샤 Multilayer board manufacturing method
US7661191B2 (en) 2004-03-03 2010-02-16 Sanyo Electric Co., Ltd. Multilayer substrate manufacturing method
JP4767163B2 (en) * 2004-03-03 2011-09-07 三洋電機株式会社 Multilayer substrate manufacturing method
JP2015056445A (en) * 2013-09-10 2015-03-23 コーア株式会社 Method for manufacturing part built-in type substrate
JP2015056547A (en) * 2013-09-12 2015-03-23 コーア株式会社 Method for manufacturing part built-in type substrate

Similar Documents

Publication Publication Date Title
FI121774B (en) Multilayer board and method of making it
JP2010087168A (en) Method for manufacturing multilayer printed circuit board
JP2000101248A (en) Multiple multilayer printed wiring board
WO2011129127A1 (en) Multi-layer flexible printed circuit board and method of manufacturing thereof
TWI763895B (en) Manufacturing method of multilayer printed wiring board and multilayer printed wiring board
JP5407470B2 (en) Multilayer circuit board manufacturing method
US9521754B1 (en) Embedded components in a substrate
JP2002329964A (en) Method of manufacturing multilayer printed wiring board
JP2002335062A (en) Method for manufacturing printed circuit board
JP4206545B2 (en) Manufacturing method of multilayer printed wiring board
JP2009239105A (en) Method of manufacturing multilayer circuit board
JP3904401B2 (en) Multilayer printed wiring board and manufacturing method thereof
JP2002329963A (en) Method of manufacturing multilayer printed wiring board
KR101395904B1 (en) Manufacturing multilayer flexible printed circuit board
JP2000183492A (en) Manufacture of multilayer printed circuit board
JP2004079703A (en) Multilayer substrate and manufacturing method of same
JP2809526B2 (en) Method of manufacturing multilayer blind through-hole wiring board
JP2010263035A (en) Method of manufacturing printed wiring board
JP2002016358A (en) Method of manufacturing multilayer printed wiring board and double side exposing tool
JP2004146427A (en) Method for manufacturing multilayer printed circuit board
JPH01140698A (en) Manufacture of multi-layered printed circuit board
JP2006196567A (en) Method for manufacturing circuit formation substrate
JPH06224553A (en) Manufacture of multilayer printed board
JPH0545079B2 (en)
JP5857632B2 (en) Circuit board, circuit board manufacturing method, and electronic apparatus