JPH06224188A - 集積回路製造方法 - Google Patents

集積回路製造方法

Info

Publication number
JPH06224188A
JPH06224188A JP5282863A JP28286393A JPH06224188A JP H06224188 A JPH06224188 A JP H06224188A JP 5282863 A JP5282863 A JP 5282863A JP 28286393 A JP28286393 A JP 28286393A JP H06224188 A JPH06224188 A JP H06224188A
Authority
JP
Japan
Prior art keywords
layer
integrated circuit
dielectric
opening
teos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5282863A
Other languages
English (en)
Japanese (ja)
Inventor
Dayo Alugbin
アラグビン ダヨー
Franklin D Nkansah
ダニエル カンサ フランクリン
Kolawole R Olasupo
ラーマン オラスポ コラウォール
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of JPH06224188A publication Critical patent/JPH06224188A/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/092—Manufacture or treatment of dielectric parts thereof by smoothing the dielectric parts

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Physical Vapour Deposition (AREA)
  • ing And Chemical Polishing (AREA)
  • Electrodes Of Semiconductors (AREA)
JP5282863A 1992-11-12 1993-11-12 集積回路製造方法 Withdrawn JPH06224188A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/975,235 US5268332A (en) 1992-11-12 1992-11-12 Method of integrated circuit fabrication having planarized dielectrics
US975235 1992-11-12

Publications (1)

Publication Number Publication Date
JPH06224188A true JPH06224188A (ja) 1994-08-12

Family

ID=25522812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5282863A Withdrawn JPH06224188A (ja) 1992-11-12 1993-11-12 集積回路製造方法

Country Status (5)

Country Link
US (1) US5268332A (enExample)
EP (1) EP0597634A3 (enExample)
JP (1) JPH06224188A (enExample)
KR (1) KR100276146B1 (enExample)
TW (1) TW247370B (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2926864B2 (ja) * 1990-04-12 1999-07-28 ソニー株式会社 銅系金属膜のエッチング方法
US6297110B1 (en) 1994-07-29 2001-10-02 Stmicroelectronics, Inc. Method of forming a contact in an integrated circuit
JPH11506744A (ja) 1995-06-07 1999-06-15 ノウブン ファーマシューティカルズ インク． 室温で液体である低分子量薬を含む経皮組成物
CN102157437B (zh) * 2010-02-11 2013-12-25 中国科学院微电子研究所 半导体结构的形成方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4708770A (en) * 1986-06-19 1987-11-24 Lsi Logic Corporation Planarized process for forming vias in silicon wafers
EP0263220B1 (en) * 1986-10-08 1992-09-09 International Business Machines Corporation Method of forming a via-having a desired slope in a photoresist masked composite insulating layer
US5022958A (en) * 1990-06-27 1991-06-11 At&T Bell Laboratories Method of etching for integrated circuits with planarized dielectric

Also Published As

Publication number Publication date
US5268332A (en) 1993-12-07
KR100276146B1 (ko) 2001-01-15
TW247370B (enExample) 1995-05-11
EP0597634A3 (en) 1994-08-24
EP0597634A2 (en) 1994-05-18
KR940012505A (ko) 1994-06-23

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Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20010130