TW247370B - - Google Patents
Info
- Publication number
- TW247370B TW247370B TW082109364A TW82109364A TW247370B TW 247370 B TW247370 B TW 247370B TW 082109364 A TW082109364 A TW 082109364A TW 82109364 A TW82109364 A TW 82109364A TW 247370 B TW247370 B TW 247370B
- Authority
- TW
- Taiwan
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/975,235 US5268332A (en) | 1992-11-12 | 1992-11-12 | Method of integrated circuit fabrication having planarized dielectrics |
Publications (1)
Publication Number | Publication Date |
---|---|
TW247370B true TW247370B (zh) | 1995-05-11 |
Family
ID=25522812
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW082109364A TW247370B (zh) | 1992-11-12 | 1993-11-06 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5268332A (zh) |
EP (1) | EP0597634A3 (zh) |
JP (1) | JPH06224188A (zh) |
KR (1) | KR100276146B1 (zh) |
TW (1) | TW247370B (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2926864B2 (ja) * | 1990-04-12 | 1999-07-28 | ソニー株式会社 | 銅系金属膜のエッチング方法 |
US6297110B1 (en) * | 1994-07-29 | 2001-10-02 | Stmicroelectronics, Inc. | Method of forming a contact in an integrated circuit |
NZ309980A (en) | 1995-06-07 | 2001-06-29 | Noven Pharma | Transdermal composition containing a blend of one or more polymers, one or more drugs that has a low molecular weight and is liquid at room temperature |
CN102157437B (zh) * | 2010-02-11 | 2013-12-25 | 中国科学院微电子研究所 | 半导体结构的形成方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4708770A (en) * | 1986-06-19 | 1987-11-24 | Lsi Logic Corporation | Planarized process for forming vias in silicon wafers |
EP0263220B1 (en) * | 1986-10-08 | 1992-09-09 | International Business Machines Corporation | Method of forming a via-having a desired slope in a photoresist masked composite insulating layer |
US5022958A (en) * | 1990-06-27 | 1991-06-11 | At&T Bell Laboratories | Method of etching for integrated circuits with planarized dielectric |
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1992
- 1992-11-12 US US07/975,235 patent/US5268332A/en not_active Expired - Lifetime
-
1993
- 1993-11-04 EP EP9393308839A patent/EP0597634A3/en not_active Withdrawn
- 1993-11-06 TW TW082109364A patent/TW247370B/zh not_active IP Right Cessation
- 1993-11-11 KR KR1019930023860A patent/KR100276146B1/ko not_active IP Right Cessation
- 1993-11-12 JP JP5282863A patent/JPH06224188A/ja not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
KR940012505A (ko) | 1994-06-23 |
KR100276146B1 (ko) | 2001-01-15 |
EP0597634A3 (en) | 1994-08-24 |
US5268332A (en) | 1993-12-07 |
EP0597634A2 (en) | 1994-05-18 |
JPH06224188A (ja) | 1994-08-12 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK4A | Expiration of patent term of an invention patent |