JPH06209110A - Mnos type semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the increase in the trap level density of a gate nitride film due to the sputter damage thereby easily shifting the threshold value voltage in the minus direction in order to form a gate electrode on a gate insulating film (two layers of an oxide film and a nitride film). CONSTITUTION:In order to form a gate part of an MNOS semiconductor device, a conductive thin film (phosphorus doped polysilicon film in this embodiment) 8 is provided between a gate insulating film (oxide film 4a, nitride film 5a) and a gate electrode 6a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to MNOS (Metal Ni
The present invention relates to a structure of a semiconductor device having a tride oxide transistor structure.

[0002]

2. Description of the Related Art Regarding the MNOS type semiconductor device, for example, the Baba Genshiki "Electronic Device Encyclopedia" reprint (Sho 53-1-2)
5) Radio Technology Company p. Although disclosed in many documents such as 61, FIG. 4 shows an example of a sectional structure of a transistor portion of the conventional semiconductor device having the MNOS structure. The figure shows N-ch
This is an example of Tr (N-channel type transistor), and its configuration will be described below.

A low concentration P type diffusion layer 2 is formed on an N type Si substrate 1.
(Generally referred to as a P well layer) is formed,
Further, in the P-well layer 2, a high-concentration N-type diffusion layer (generally N ⁺
Layer 3 is formed.

Further, a gate oxide film (SiO ₂ ) 4a is formed on the channel portion (between the source and the drain), and a gate nitride (Si ₃ N ₄ ) film 5a is formed thereon.

A gate electrode 6a made of Al is formed on the gate film (a two-layer film including an oxide film 4a and a nitride film 5a).

On the other hand, an Al wiring 6 is formed on the N ⁺ layer 3 serving as the source / drain. In addition, the element is a protective film 7
(Generally CVD (Chemical Vapor Deposition) SiN film or CV
DPSG film). The operation as an N-ch Tr is the same as that of a normal N-ch MOSTr (N Channel Meta
(Oxide Transistor), a potential difference is applied between the drain and the source, and a bias of V _T (threshold voltage) or more is applied to the gate electrode.
An electric field is applied to the channel surface via a, an inversion layer is generated in the channel, and a current flows from the drain to the source.

In such a Tr structure, the Si ₃ N ₄ films 5a and 5 are provided on the gate oxide film 4a and the field oxide film 4, which are formed in the semiconductor manufacturing process, for example, Al electrodes. The purpose is to prevent an alkali metal such as Na ⁺ ions from entering 6a and 6 as impurity contamination into the device and causing quality deterioration such as V _T fluctuation. That is, by providing the Si ₃ N ₄ film 5a on the gate SiO ₂ film 4a, it is possible to manufacture a highly reliable metal gate MOSTr that is resistant to contamination of mobile ions such as Na ⁺ .

[0008]

However, the conventional MNOS structure has the following problems.

That is, Si used as a gate insulating film
_Since the metal film (Al or Al-Si film in the above example) of the gate electrode is directly formed on the ₃ N ₄ (silicon nitride) film by the magnetron sputtering method, the trap of the surface layer of the Si ₃ N ₄ film is caused by the sputter damage. The level density becomes large.

As a result, when a voltage is applied to the gate of the Tr having such an MNOS structure, for example, in N-chTr, holes are easily injected and trapped from the gate electrode into the gate insulating film, and the V _T (threshold of Tr is increased. There is a problem that the value voltage) tends to be shifted in the negative direction.

The object of the present invention is to prevent the increase of the trap level density of the gate Si ₃ N ₄ film due to the above-mentioned sputter damage, thereby preventing the fluctuation of V _{T of} Tr and providing a highly reliable MNOS. It is to provide a structural element.

[0012]

In order to achieve the above object, the present invention provides a MNOS type semiconductor device, at least on a gate insulating film, a conductive film using a CVD method (for example, phosphorus-doped Poly-Si (polysilicon)). And then Al-S to be a gate electrode by a magnetron sputtering method.
It has a structure for forming an i film.

[0013]

As described above, according to the present invention, for example, phosphorus-doped Pol is formed on the gate Si ₃ N ₄ film of the MNOS structure element.
After forming a conductive film such as a y-Si film by a CVD method, Al
(Or Al-Si) electrodes are formed.
The element can be formed without damaging the gate Si ₃ N ₄ film during sputtering.

As a result, it is possible to prevent an increase in the trap density of the surface layer of the gate Si ₃ N ₄ film due to sputter damage, and it is highly reliable that fluctuations in V _T of Tr due to holes and electron traps do not occur. MN
A semiconductor device having an OS structure can be provided.

[0015]

FIG. 1 shows the first embodiment of the present invention. Further, FIG. 2 shows a cross-sectional view of the manufacturing process thereof, and the description will be given below mainly with reference to FIG. Note that, similarly to the example of the conventional MNOS semiconductor device of FIG. 4, an example of N-chTr is shown here. The same parts as those in the conventional example are indicated by the same reference numerals.

First, as shown in FIG. 2A, as in the prior art, after forming a P well layer 2 on an N type Si substrate 1, a high concentration N type diffusion layer (referred to as an N ⁺ layer) 3 is formed of Tr. Formed for source and drain. A field oxide film 4 formed by thermal oxidation is formed as a protective and insulating film above the surface layer of the Si substrate 1, and 500 to 1000 Å is applied only to a portion which becomes a channel of Tr
The gate oxide film 4a is formed to a certain extent.

Further, the Si ₃ N ₄ films 5 and 5a peculiar to the MNOS structure are replaced with the gate oxide film 4a and the field oxide film 4.
The upper layer is formed by LP-CVD (Low Pressure Chemical Vapor Deposition) method.

Up to this point, the manufacturing method of the conventional MNOS structure is the same.

Next, as shown in FIG. 2B, a poly-Si is formed on the entire surface of the device by using a low pressure CVD method with SiH ₄ gas.
A thin film 8 of (polysilicon) is produced. This thin film 8 is
A thickness of at least 50 Å or more is sufficient to prevent damage to the nitride film 5a due to sputtering in a later process.

Next, in order to improve the conductivity of the Poly-Si film 8, an N-type dopant is diffused at a high concentration. In general, phosphorus ion implantation using a phosphorus diffusion method using PoCl ₃ as a source or high current type implantation (implantation) device and annealing in a diffusion furnace (or lamp annealing is also possible) are performed to obtain the Poly-Si film 8
Control the resistance of 15Ω / □ to 30Ω □. Next, in order to form a contact hole for drawing out the electrode from the source / drain layer 3, a technique of photolithography is used to form the Poly-Si / Si on the source / drain 3.
_{The 3} N ₄ / SiO ₂ film (8/5/4) is selectively etched using the resist 9 as a mask.

The Poly-Si film 8 and the Si ₃ N ₄ film 5 can be dry-etched by using an etching gas of CF ₄ + 5% O ₂ , and the SiO ₂ film 4 is HF-NH ₃ F.
Can be etched with a system etchant. After that, the resist 9 is removed.

Next, as shown in FIG. 2 (c), Al- is formed on the entire surface.
A Si film (containing 1 to 1.5% Si) 6 having a thickness of about 1.0 μ is formed by a magnetron sputtering method, and is selectively etched by using the resist 10 as a mask using a photolithography technique to form a gate electrode 6a and a source.・ A of drain wiring
The l wiring 6 is formed. Incidentally etching of Al-Si wires 6,6a are phosphoric acid as a main component, nitric acid, by mixed acid of acetic acid, carried out by dry etching using wet etching or BCl ₃ + Cl ₂ and the like gases. After that, the resist 10 is removed.

Next, as shown in FIG. 2D, the Si in the Al-Si films 6 and 6a and the phosphorus-doped Poly-Si film 8 are formed into A.
Using the l wiring pattern 6 as a mask, etching is selectively performed with an etchant such as HF-HNO ₃ .

Finally, the protective film 7 is formed as in the conventional case.
As the protective film 7, a SiO ₂ film or PSG formed by the CVD method is used.
A film or a SiN film formed by a plasma CVD method is generally used.

The structure completed in this way is shown in FIG. 1, which is a structure in which the polysilicon film 8 is provided at least between the gate nitride film 5a and the gate electrode 6a.

In this embodiment, the conductive thin film 8 is LP-C.
Although the Poly-Si film by the VD method was used, as another material, phosphorus-doped Poly-Si is directly LP-CV.
A method of forming a film by D, a CVD film of Ti, and the like can be considered.

In the case of Ti, it is possible to form a film at 400 to 500 ° C. under a reduced pressure of several torr using TiCl ₄ as a raw material gas. Further, when Ti is used, phosphorus doping unlike Poly-Si is not required. Further, the etching of Ti can be performed with an HF-based etchant.

FIG. 3 shows the structure of the second embodiment of the present invention.

In the second embodiment, after the Si ₃ N ₄ film 5 is formed by the LP-CVD method (FIG. 2A), the contact hole is first opened and then the conductive film 8 is formed. It is an example. The difference from the first embodiment is only that the conductive film 8 remains in the contact hole, and the structure under the gate electrode 6a is the same as that of the first embodiment.

Although the above description is based on the N-chTr as an example, the same effect can be obtained even if the P-chTr is replaced by the N-type part and the P-type part. Needless to say.

[0031]

As described above in detail, according to the present invention, a conductive film such as a phosphorus-doped Poly-Si film is formed on the gate Si ₃ N ₄ film of the MNOS structure element by CV.
Since the Al (or Al-Si) electrode is formed after the film is formed by the D method, the element can be formed without damaging the gate Si ₃ N ₄ film during Al sputtering.

As a result, it is possible to prevent an increase in the trap density of the surface layer of the gate Si ₃ N ₄ film due to sputter damage, and it is highly reliable that fluctuations in V _T of Tr due to holes and electron traps do not occur. MN
A semiconductor device having an OS structure can be provided.

[Brief description of drawings]

FIG. 1 is a first embodiment of the present invention.

FIG. 2 is a manufacturing process of the first embodiment.

FIG. 3 is a second embodiment of the present invention.

FIG. 4 Conventional example

[Explanation of symbols]

1 N-type Si substrate 2 P well layer 3 N ⁺ layer (source / drain) 4 Field oxide film 4a Gate oxide film 5,5a Si ₃ N ₄ film 6,6a Al wiring 7 Protective film 8 Polysilicon film

Claims (2)

[Claims] 1. An M having a two-layer film including an oxide film and a nitride film as a gate insulating film, and having a gate electrode on the two-layer film.
A NOS type semiconductor device, comprising a conductive film between the two-layer film and the gate electrode. 2. The conductive film is a film having a thickness of at least 50 Å or more formed by a low pressure chemical vapor deposition method,
2. The MNO according to claim 1, which is a film obtained by injecting impurities into a polysilicon film using SiH ₄ as a raw material gas or a Ti film using TiCl ₄ as a raw material gas.
S-type semiconductor device.