JPH06195303A - Data transfer storage device - Google Patents

Abstract

PURPOSE:To provide the data transfer storage device which simplifies the constitution of the device by control of a software, and executes a high speed processing being equal to a DMA operation. CONSTITUTION:The device is constituted by providing a host device processing part 3 for receiving an instruction from a host device 1 and executing transmission and reception of data, a first storage means 6 for accumulating temporarily the data, a second storage means 7 for storing the data, a transfer processing means 5 for executing a DMA transfer of the data by a prescribed transfer instruction between these first and second storage means, and a control means 2 for decoding the instruction received by the host device processing part, and giving a transfer instruction to the transfer processing means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer storage device for storing data transferred from a host device in accordance with a command from the host device or reading the stored data and transferring the data to the host device.

[0002]

2. Description of the Related Art A conventional data transfer storage device performs data transfer by DMA transfer between a host device and a buffer memory and between a buffer memory and an I / O device.

[0003]

However, since the conventional data transfer storage device has a circuit for performing the DMA transfer on both the upper side and the lower side via the buffer memory, the circuit of the hardware is Since the scale is large, the device is expensive, and it is difficult to reduce the size of the device.

The present invention solves such a conventional problem, and an object of the present invention is to provide a data transfer storage device that simplifies the device configuration by controlling software and performs high-speed processing equivalent to a DMA operation. .

[0005]

In order to achieve the above object, the present invention provides a host device processing unit for receiving a command from a host device and transmitting / receiving data, and a first device for temporarily storing data. The storage means, at least one second storage means for storing data, a transfer processing means for performing DMA transfer of data between the first and second storage means according to a predetermined transfer instruction, and a host device processing section Decode the received instruction,
And a control means for giving a transfer instruction to the transfer processing means.

[0006]

According to the present invention, by the instruction from the host device,
The operation of writing data from the host device to the first storage device at the time of writing and the operation of reading data from the first storage device to the host device at the time of reading are performed by DM
It can be processed at high speed without A transfer.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, the data transfer storage device 8 is connected to the host device 1 by a signal line 9. The data transfer storage device 8 is internally connected to the CPU 2 serving as a control unit via the CPU 2 and the CPU bus 10, receives commands from the host device, and transmits / receives data to / from the host device. It has a higher-level device processing unit 3 for performing the operation. Also,
A buffer memory 6 that is a first storage unit that temporarily stores data and a buffer memory processing unit 4 that controls the buffer memory 6.
have. In addition, SCSI (Small Com
a plurality of I / O devices 7 (7a, 7) that are second storage means conforming to the computer system interface.
b, 7c), the buffer memory processing unit 4 and the I / O device 7 are provided with a SCSI processing unit 5 as a transfer processing unit that performs DMA transfer of data according to a transfer instruction of the CPU 2.

The SCSI processing unit 5 and the buffer memory processing unit 4 are connected via a signal line 11a, and the SCSI processing unit 5 and the I / O device 7 are connected via a SCSI bus 12. Up to seven I / O devices 7 can be connected.

Next, the operation of the data transfer storage device 8 will be described.

The interface of the signal line 9 connecting the higher-level device 1 and the higher-level device processing section 3 has an 8-bit data line and a control line of up and down, operates in a handshake procedure, and activates and transfers commands. , Transitions in three stages of reporting. The maximum transfer rate of the signal line 9 is 500 KByte / sec due to the restriction of the host device 1.

First, the operation (write operation) of writing data from the host device 1 to the I / O device 7a will be described.
In the command activation sequence from the host device 1, a command, that is, an instruction, is sent via the signal line 9 to the host device processing unit 3
To receive. The reception completion is notified to the CPU 2 by an interrupt signal, and the CPU 2 reads the command from the higher-level device processing section 3. In response to the command, the CPU 2 issues a data transfer request to the host device processing unit 3. The host device processing unit 3 requests the transfer sequence from the host device 1.

When in the transfer sequence state, the host device 1
8 bits of data from the
When the data for bytes is accumulated, the CPU 2 reads it as 32-bit data from the higher-level device processing unit 3 and writes it in the buffer memory 6 via the buffer memory processing unit 4. The process of writing data from the host device 1 to the buffer memory 6 is repeated until the transfer amount requested by the host device 1.

When the transfer to the buffer memory 6 is completed,
The CPU 2 instructs the buffer memory processing unit 4 and the SCSI processing unit 5 to perform a DMA (direct memory access) operation, converts the 32-bit data in the buffer memory 6 into 8 bits in the buffer memory processing unit 4, and causes the SCSI processing unit 5 to operate. Then, DMA transfer is performed to the I / O device 7a. When this transfer sequence ends, the CPU 2 sends a report request to the higher-level device processing unit 3, and the higher-level device processing unit 3 requests the higher-level device 1 for the report sequence. In the report sequence state, the CPU 2 writes the status information indicating the normal writing operation end to the higher-level device processing unit 3, and this status information is transferred from the higher-level device processing unit 3 to the higher-level device 1.
The write operation ends.

Next, the operation (read operation) of reading data from the I / O device 7a to the host device 1 will be described.
Similar to the write operation, in the command activation sequence, the command is received by the host device processing unit 3 from the host device 1 via the signal line 9. When the reception is completed, the CPU sends an interrupt signal
2 is notified, and the CPU 2 reads the command from the higher-level device processing unit 3. In response to the command, the CPU 2 instructs the buffer memory processing unit 5 and the SCSI processing unit 5 to perform a DMA operation, and the 8-bit data read from the I / O device 7a is processed by the buffer memory processing unit 4 via the SCSI processing unit 5. Three
It is converted into 2 bits and DMA-transferred to the buffer memory 6. When the DMA transfer is completed, the CPU 2 issues a data transfer request to the host device processing unit 3. The host device processing unit 3 requests the transfer sequence from the host device 1. In the transfer sequence, the CPU 2 reads the 32-bit data from the buffer memory 6 via the buffer memory processing unit 4 and writes the 32-bit data to the higher-level device processing unit 3. The written data is transmitted to the higher-level device 1 as 8-bit data and 4
When the transmission of the data of bytes is completed, the CPU 2 repeats the process of transferring from the buffer memory 6 to the higher-level device 1 up to the transfer amount requested by the higher-level device 1. When the transfer sequence ends, the CPU 2 issues a report request to the higher-level device processing unit 3.

The host device processing unit 3 requests the report sequence from the host device 1.

In the report sequence state, the CPU 2
Writes status information indicating the end of the normal reading operation in the higher-level device processing unit 3. This status information is transferred from the host device processing unit 3 to the host device 1, and the read operation is completed.

Next, the high speed processing in this embodiment will be described with reference to FIGS. 2, 3 and 4. FIG. 2 is a block diagram showing the operation of the higher-level device processing section 3. FIG. 3 is a flowchart of the read transfer process. FIG. 4 is a flowchart of the write transfer process.

In FIG. 2, the host device processing section 3 is the same as that of FIG.
As shown in FIG. 3, the CPU 2 and the host device 1 are connected, and the internal configuration is as follows. That is, the control register 13 that is a register for controlling the higher-level device processing unit 3 from the CPU 2, the status register 14 that is a register for reading the status information of the higher-level device processing unit 3 from the CPU 2, and the read / write data are held. A data register A15 and a data register B16, a register selector 17 for selecting a register to be specified from these registers by the CPU 2, and an I / O sequence controller 18 for controlling a transfer sequence with the higher-level device 1. , A data transfer control unit 19 for controlling data transfer in a transfer sequence with the host device 1, an output signal buffer 20 for sending to the host device 1, and an input signal buffer 21 for receiving from the host device 1. To be done.

First, the read operation will be described based on FIG. 3 with reference to the block diagram showing the operation of the host device processing section 3 in FIG.

In the transfer sequence, the CPU 2 of FIG. 2 sets the settings required for the read operation in the control register 1
Write to 3. Next, 32-bit data is written to the data register A15 (step S1), and then 32-bit data is written to the data register B16 (step S2). As a result, the data register A
The 32-bit data written in 15 is divided into 8-bit data by the data transfer control unit 19, and 4 bytes are transferred to the higher-level device 1 by 1 byte via the I / O sequence control unit 18 and the output signal buffer 20. Then, the 32-bit data written in the data register B16 is also transferred to the higher-level device 1 by 4 bytes, one byte at a time, similarly to the data register A15.

Data register A15 and data register B
After writing to 16, the CPU 2 sets the status register 14
Is read and it is checked whether or not the data register A15 is empty, that is, whether or not the transfer of 32-bit data is completed (step S3). If it is empty, the data register A15 is transferred to the next new 32 bits. Data is written (step S4). After that, the status register 14 is read and it is checked whether or not the data register B16 is empty (step S5). If it is empty, the next 32-bit data is written to the data register B16 (step S6). Then, it is checked whether or not the transfer is completed (step S
7) If the transfer is not completed, the process returns to step S3. If the transfer is completed, the process ends.

As described above, during the read operation, while the data in the B-side register is being transferred to the host device 1, the data is written in the A-side register, and the data in the A-side register is transferred to the host device. High-speed processing can be performed by writing data to the B-side register while transferring to 1.

Next, the write operation will be described based on FIG. 4 with reference to the block diagram showing the operation of the host device processing section 3 in FIG.

In the transfer sequence, the CPU 2 of FIG. 2 sets the settings necessary for the write operation in the control register 1
Write to 3. Then, the status register 14 is read to determine whether the data register A15 is full,
That is, it is checked whether or not all the 32-bit data is stored in the data register A15 (step S8), and if it is full, the 32-bit data is read from the data register A15 (step S9). Then, the status register 14 is read to check whether the data register B16 is full (step S10). If the data register B16 is full, 32-bit data is read from the data register B16 (step S11). Then, it is checked whether or not the transfer is completed (step S12). If the transfer is not completed, the process returns to step S8, and if the transfer is completed, the process is completed.

In the above-described write operation processing, the data of 1 byte transferred from the host device 1 is transferred to the data transfer control unit 19 via the input signal buffer 21 and the I / O sequence control unit 18 of FIG. The data is combined into byte data and written as 32-bit data in the data register A15 or the data register B16.

As described above, during the write operation, while the data is being transferred from the higher-level device 1 to the register on the B side, A
Data is read from the register on the screen, and the host device 1
High-speed processing can be performed by reading the data from the B-side register while transferring the data from the A-side to the A-side register.

In this case, since the transfer rate between the host device 1 and the data transfer storage device 8 is 500 KByte / sec, the transfer time of 32-bit data, that is, 4 bytes is 8 microseconds. Further, since the time for which the CPU 2 sets the 32-bit data in the data register A or B is 1 microsecond or less, one of the data registers is vacant until the transfer of the 32-bit data is completed. The time to set 32-bit data in the data register can be almost ignored.

Although the I / O device is a device conforming to SCSI in the above embodiment, the present invention can be applied to other data transmission interfaces.

[0030]

As described above, according to the present invention, in accordance with an instruction from the host device, the data from the host device is written to the I / O device at the time of writing, and the data from the I / O device is sent to the host device at the time of reading. Can speed up the process of reading
Furthermore, since the hardware configuration for the DMA transfer process can be simplified, the cost of the device can be reduced and the device can be downsized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data transfer storage device of the present invention.

FIG. 2 is a block diagram of a host device processing unit shown in FIG.

FIG. 3 is a flowchart showing a read transfer process of FIG.

FIG. 4 is a flowchart showing a write transfer process of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Upper device 2 CPU (control means) 3 Upper device processing unit 4 Buffer memory processing unit 5 SCSI processing unit (transfer processing unit) 6 Buffer memory (first storage unit) 7a to 7c I / O device (second storage) Means) 8 data transfer storage device 9, 11, 11a signal line 10 CPU bus 12 SCSI bus 13 control register 14 status register 15 data register A 16 data register B 17 register selector 18 I / O sequence control unit 19 data transfer control unit 20 Output signal buffer 21 Input signal buffer

Claims (1)

[Claims] 1. A data transfer storage device for storing data transferred from this host device based on an instruction from the host device, and reading the stored data and transferring it to this host device. A host device processing unit that receives the command from the device and transmits and receives the data, a first storage unit that temporarily stores the data, and at least one second storage unit that stores the data. A transfer processing means for performing a DMA transfer of data between the first and second storage means according to a predetermined transfer instruction, and decoding the instruction received by the host device processing section, and instructing the transfer processing means to perform the transfer instruction. A data transfer storage device, comprising: