JPH01128151A - Interface device - Google Patents

Abstract

PURPOSE:To perform the transfer of data at a high speed to its own data processor and also between processors by using the buffer memories, the input/output programs and the control circuits for both transmission and reception separately from each other and carrying out the parallel transfer of data. CONSTITUTION:An interface device transfers data to a transmission buffer memory 9A from a main memory and then the data stored in the memory 9A to another data processor under the control of a transmission control program 70A of its own data processor and a transmission control circuit 10A which works on the program 70A in case the processor sends data to another one. At the same time, the data are sent to the main memory from a reception buffer memory 9B under the control of a reception control program 70B and a reception control circuit 10B which works on the program 70B in case the data received from another data processor are stored in the memory 9B. Thus it is possible to perform simultaneously the transfer of data for both transmission and reception and to transfer data between data processors at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interface device provided in each data processing device to connect a plurality of data processing devices.

[Conventional technology]

The slow processing speed of input/output devices is compensated for by providing a high-speed buffer memory such as an IC memory between an arithmetic unit capable of high-speed processing and the input/output device.

However, such a conventional interface device has a configuration in which a transmitting operation and a receiving operation cannot be performed simultaneously by simply providing a buffer register or a buffer memory for both transmitting and receiving purposes.

FIG. 5 shows a conventional device including a data processing device (DPI) 1 and an interface device (IFE) 3. The data processing device 1 includes a central processing unit (CPU) 5, a main memory (MM) 6, and a direct memory access control circuit (DMAC). ) 7 and a processor bus 4;
9. Data processing device interface circuit (DINF) 1
0 and an interface control circuit (CTL) 11, and there is an interrupt line 12 between the central processing unit (CPU) 5 and the data processing device interface circuit 10. When the central processing unit 5 sends data to another data processing unit, the central processing unit 5 sets the data storage start address of the main memory 6, the number of transfer words, etc. in the direct memory access control circuit 7, and then transmits the data to the direct memory access control circuit 7. issuing instructions to the processing device interface circuit 10;
Data is sent from the main memory 6 to the back 1 memory 9 by the DMA operation of the direct memory access control circuit 7. When the central processing unit 5 recognizes the end of this data transfer via the interrupt control line 12 from the data processing device interface circuit 10, the central processing unit 5 instructs the interface control circuit 11 to send other data via the interface bus 2. Instructs data transfer to the data processing device. The interface control circuit 11 sends the data in the buffer memory 9 to the interface bus 2 via the interface bus circuit 8 according to instructions from the central processing unit 5 .

The interface bus circuit 8 sends data to the interface bus 2, and under the control of the interface control circuit 11, it also performs operations such as start-up connection processing with other data devices and status reporting processing after data transfer is completed. . If the interface bus 2 is a general-purpose input/output interface bus and transfers data between a data channel device and an input/output device, please refer to 3. of the book ``Electronic Computer System Design'' ■Sanpo Published July 1, 1972). The transfer control operation is explained in detail in the section on three-person output control, so it will be omitted.

When data is sent from another data processing device via the interface bus 2, the interface bus circuit 8 writes the data into the buffer memory 9 under the control of the interface control circuit 11. After the data transfer is completed, the buffer memories 9, 6.

When data storage is completed, the interface control circuit 11 controls the data processing device ink 7 ace circuit 10 and instructs the central processing unit 5 to perform a reception operation via the interrupt control line 12. The central processing unit 5 controls the direct memory access control circuit 7 and the data processing device interface circuit 10 in the same manner as in the transmission operation, and transfers data from the password 1 memory 9 to the main memory 6 by DMA operation.

As explained above, in the conventional device, the data transfer between the buffer memory 9 and the main memory 6 is performed in the same way as the transmission and reception.
8 to 30) describe the buffer memory method.

[Problem that the invention seeks to solve]

In the above conventional technology, since there is only one buffer memory,
4. Data transfer between the interface device and its own data processing device had to be carried out serially in transmission and reception operations, resulting in high speed data transfer.

There were limits to this.

An object of the present invention is to speed up the data transfer between the data processing devices by speeding up the data transfer between the interface device and the own data processing device.

[Means for solving problems]

In order to achieve the above object, the interface device of the present invention provides separate buffer memories for sending and receiving, and also separates buffer memories for sending and receiving input/output control programs to the interface device of the data processing device. a transmission control circuit that controls between the transmission control program and the transmission buffer memory and includes a transmission command register, a transmission transfer counter, a transmission status register, etc.; a reception command register that controls between the reception control program and the reception buffer memory; This is achieved by providing a reception control circuit including a reception transfer counter and reception status register.

[Effect]

In the interface device of the present invention, when a data processing device sends data to another data processing device, the main memory is controlled by a transmission control program of the own data processing device and a transmission control circuit operated by the transmission control program. The data is transferred from the transmitting buffer 7 memory to the transmitting buffer 7 memory, and after the transfer is completed, the data in the transmitting buffer memory is transferred to another data processing device. Additionally, if data sent from another data processing device is stored in the reception buffer 1 memory at the same time, the reception buffer is Transfer data from memory to main memory. In this way, by being able to transfer transmission and reception data simultaneously, data transfer between data processing devices can be realized at high speed.

〔Example〕

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 2 is a connection diagram between data processing devices, and in the case of FIG. DPI
, IB to IN are in the relationship of slave data processing devices, or
Regarding the relationship between the host computer and input/output devices, multiple DPEs and IA-INs are interface devices (IFE).
It is connected to the interface bus 2 via 3A to 3N. During the second visit, the names of each part will be abbreviated.

The present invention will be explained in detail with reference to FIGS. 1, 6, and 4. FIG. 3 is a diagram showing the relationship between the software of the data processing device 1 and the hardware of the interface device B, and FIG. 4 is a detailed circuit configuration diagram of the interface device 3. As shown in Figure 1, from Figure 5 mentioned above, IFE3 is a sending buffer memo') (SBM).
9A is separated into a reception buffer memory (RBM), and DINFlo is separated into a transmission interface circuit (SI).
NF) 10A and reception interface circuit (RINF)
It is separated into 10B. DPEl's software is
As shown in Figure 3, the operating system (OS)
)s.

, an application program (AP) 60, and an input/output control program 70.

The input/output control program 70 further includes a transmission control program (S-IOCP) 7DA and a reception control program 7DA.
- Composed of 70B (R-IOCP). The description of each of the 0850° AP 60 and the input/output control program 7o and their control operations will be omitted since they are well-known techniques in the software of ordinary data processing devices. AP60. S-400P7GA and R-10CP7
0B operates simultaneously under 0850 in a so-called multiple programming mode. When a request occurs to AP60 to send data to another DPE, AP6
0 passes control to 5-IOCP70A. 5-IOCP7
0A controls 5INF10A and writes data to 88M9A. When data writing to 88M9A is completed, S-I OCP controls 5INF10A and CTL
ll to transfer data from 88M9A to interface bus 2. The CTLl 1 controls the INF3 to transfer data within the SBM 9A to and from other DPEls via the interface bus 2. When the data transfer is completed, the CTI 11 controls the 5INF 10A and notifies the 9S-IOCP 70A of the completion of the data transfer via the interrupt control line 12A.

・8・−4, When data is sent from another DPE via the interface bus 2, CTLll controls llNF3 and stores the data in RBM9B. When the data transfer from another DPE is completed, CTLll controls RINFloB and requests data reception from the interrupt control line 12BIC to the R-IOCP 70B. R-IOCP70B is RI
Controls NFIDB and reads data in RBM9B.

Interface bus 2 and INF3 cannot transmit and receive data at the same time, but S-I OCP70A-9
INF10A-8BM9A and RBM9B-RINFIC
Data transfer is possible simultaneously and independently of IB-R-IOCP70B. MM6 and SB'M9A and RBM9
Data transfer between B and MM6 can also be executed by a memory-to-memory data transfer instruction from the CPU 5, but normally the data transfer is performed by the DMAC 7 in DMA mode. A detailed example of IFE3 is shown in FIG. CTLll is a microprogram type control circuit that includes a control memory CM that stores a microprogram, a microinstruction register CMIR, a sequencer SEQ, a microinstruction decoder DEC, a test circuit TS'I', arithmetic circuits AI and U, and a register circuit REG. It is configured. Its operation is explained in the section 2.2.3 Microprogram control of Electronic Computer System Design J and is a well-known technique, so the explanation will be omitted. Similarly, RBM9B is composed of a step circuit +1, and RBM9B is a memory module R.
BMM.

RBM address register RAR and RAR step circuit +1
It is made up of. 5INF10A is composed of a transmit command register SCMR, a transmit byte counter 5B (J) and a transmit status register 5STR, and similarly, RINFloB is composed of a receive command register RCMR, a receive byte counter RBCR, and a receive status register R8'l'R.SCMR Data is written to 5BCR and RCMR from the CPU 5, that is, 5-IOCP70A or R-IOCP70B via the processor bus 4, SCMR is a data transmission instruction from MM6 to SBM9A, 5BCR is an instruction for the number of bytes to transfer transmission data, and RCMR is written from RBM9B. Instructs MM6 to receive data.RBCR, 5STR, R8T
R is read by R-IOCP70B or 5-IOCP70A via processor bus 4), RBC
R indicates the number of transferred bytes of received data, 5STR and R8T
R is IFE3 after transmission or reception data transfer is completed, respectively.
The status is displayed. These 6 circuits are CT
It is connected to Ll1, and its contents can be set and read from CTLll. CTLll is SC
When it detects that there is a data transmission instruction from MRIc S-I 0CP70A, the data in SBMM written in advance by DMAC7 is transferred to 5BCR, which is also written in advance by 5-IOCP70A.
It reads only the amount of data transferred within, controls llNF3, and sends the data to the interface bus 2. When the data transfer is completed, an end indication is set to 5STR, and the interrupt control line 12A is notified of the end of the transfer. On the other hand, when data is stored in the RBMM from the interface bus 2 via llNF3, CTLll sets a data reception request to R8TR, and also sends fiR-I via the interrupt control line 12B.
OC: Requests reception operation to P70A.

・　11　.

The R-IOCP70B then instructs the RCMH to receive data, reads the received data transfer amount in the RBCR written in advance by CTLll, and uses this value to perform the DMAC
7, the contents of the RBMM are read into the MM5. S
AR and RAR are CTLl 1 to SBMM and R
This is used to set the access address to BMM, usually 0.
The address is set and the address is automatically incremented by a +1 circuit for each write and read. Naori MA
Although C7 is not shown, it has a configuration capable of parallel transmission and reception operations.

〔Effect of the invention〕

According to the present invention, since data transfer between a data processing device and an interface device can be performed in parallel in transmission and reception, it is effective in high-speed processing of data transfer.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a data processing device and an interface device according to an embodiment of the present invention, FIG. 2 is a connection diagram between data processing devices, and FIG. 3 is a software and hardware configuration explaining the present invention in detail. 4 is a detailed 12° circuit configuration diagram of an interface device according to the present invention, and FIG. 5 is a circuit diagram of a conventional device. 9A...Transmission buffer memory 9B...Reception buffer memory 1, OA...Transmission control circuit 10B...Reception control circuit SCMR...Transmission command register RCMR...Reception command register 5BCR... Transmission byte counter RBCR...Reception byte counter 5STR...Transmission status register R8TR...
Receive status register.

Claims (1)

[Claims] 1. In an interface device that is provided in a data processing device and includes a buffer memory and a control unit that controls writing and reading from the buffer memory, the buffer memory is separated into a transmitting buffer memory and a receiving buffer memory. An input/output control program for the interface device of the data processing device is provided separately into a transmission control program and a reception control program, and a transmission command register, a transmission transfer ( A transmission control circuit including a byte (byte) counter and a transmission status register, and a reception control circuit that controls between the reception control program and reception buffer memory and includes a reception command register, reception transfer (byte) counter, and reception status register. An interface device characterized by: