JPH06120072A - Capacitive element - Google Patents
Capacitive elementInfo
- Publication number
- JPH06120072A JPH06120072A JP26454792A JP26454792A JPH06120072A JP H06120072 A JPH06120072 A JP H06120072A JP 26454792 A JP26454792 A JP 26454792A JP 26454792 A JP26454792 A JP 26454792A JP H06120072 A JPH06120072 A JP H06120072A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- noble metal
- metal electrode
- capacitive element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路等のチ
ップに内蔵される高誘電率を有する誘電体薄膜等を容量
絶縁膜として用いた容量素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitive element using a dielectric thin film or the like having a high dielectric constant, which is built in a chip such as a semiconductor integrated circuit, as a capacitive insulating film.
【０００２】[0002]
【従来の技術】近年、高誘電率を有する誘電体薄膜（以
下高誘電体薄膜という）は自発分極や高誘電率といった
特徴を持つために不揮発性ＲＡＭ(Random Access Memor
y)や高集積ＤＲＡＭ(Dynamic Random Access Memory)上
での容量絶縁膜としての応用を目指して活発な研究が行
われている。一般に使用される高誘電体薄膜は金属酸化
物の焼結体からなり、反応性に富む酸素を多く含有して
いる。このような高誘電体薄膜を用いて容量素子を構成
する場合、上電極および下電極として酸化反応に対して
安定な貴金属電極が不可欠である。2. Description of the Related Art Recently, a dielectric thin film having a high dielectric constant (hereinafter referred to as a high dielectric thin film) has characteristics such as spontaneous polarization and a high dielectric constant, and therefore, a nonvolatile RAM (Random Access Memor).
y) Active research is being conducted with the aim of application as a capacitive insulating film on high-integrated DRAM (Dynamic Random Access Memory). The commonly used high dielectric thin film is made of a metal oxide sintered body and contains a large amount of highly reactive oxygen. When a capacitive element is formed using such a high dielectric thin film, a noble metal electrode that is stable against an oxidation reaction is indispensable as the upper electrode and the lower electrode.
【０００３】以下従来の容量素子について説明する。図
３は従来の容量素子の要部断面図である。図３に示すよ
うに、例えば集積回路が作り込まれた支持基板３１の上
に膜厚１０〜１００ｎｍのチタン（以下Ｔｉと略す）膜
３２が形成されている。Ｔｉ膜３２の上に膜厚１００〜
３００ｎｍの第１の白金（以下Ｐｔと略す）電極３３が
形成され、第１のＰｔ電極３３の上に容量絶縁膜として
膜厚２０〜３００ｎｍの（ＢａxＳｒ1-x）ＴｉＯ3 膜３
４が選択的に形成されている。さらに、（ＢａxＳ
ｒ1-x）ＴｉＯ3 膜３４の上には膜厚１００から３００
ｎｍの第２のＰｔ電極３５が形成されており、コンタク
ト孔３７を有するシリコン酸化膜からなる絶縁保護膜３
６によって表面が被覆されている。第１のＰｔ電極３３
および第２のＰｔ電極３５は絶縁保護膜３６に設けられ
たコンタクト孔を介して表面に形成されたＡｌ（１％Ｓ
ｉ−０．５％Ｃｕ）合金からなる金属配線膜（以下金属
配線膜という）３８にそれぞれ接続されている。A conventional capacitive element will be described below. FIG. 3 is a sectional view of a main part of a conventional capacitive element. As shown in FIG. 3, for example, a titanium (hereinafter abbreviated as Ti) film 32 having a film thickness of 10 to 100 nm is formed on a support substrate 31 in which an integrated circuit is formed. A film thickness of 100 to 100 is formed on the Ti film 32.
A first platinum (hereinafter abbreviated as Pt) electrode 33 having a thickness of 300 nm is formed, and a (Ba x Sr 1-x ) TiO 3 film 3 having a thickness of 20 to 300 nm is formed as a capacitive insulating film on the first Pt electrode 33.
4 are selectively formed. Furthermore, (Ba x S
The film thickness of 100 to 300 is formed on the (r 1 -x ) TiO 3 film 34.
second Pt electrode 35 having a thickness of 3 nm and an insulating protective film 3 made of a silicon oxide film having a contact hole 37.
The surface is covered with 6. First Pt electrode 33
And the second Pt electrode 35 is formed of Al (1% S) formed on the surface through the contact hole provided in the insulating protection film 36.
i-0.5% Cu) metal wiring film (hereinafter referred to as metal wiring film) 38 made of an alloy.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら上記の従
来の構成では、容量素子の配線工程での熱処理において
第１のＰｔ電極および第２のＰｔ電極と金属配線膜との
間に化合物が生成され、コンタクト部に鬆や欠陥が生
じ、コンタクト部における電気的接続の信頼性を著しく
損なうという課題を有していた。However, in the above conventional structure, a compound is generated between the metal wiring film and the first Pt electrode and the second Pt electrode during the heat treatment in the wiring process of the capacitive element, There is a problem that voids or defects are generated in the contact portion, and the reliability of electrical connection in the contact portion is significantly impaired.
【０００５】本発明は上記従来の課題を解決するもの
で、高誘電体薄膜を容量絶縁膜として用いた信頼性の高
い容量素子を提供することを目的とする。The present invention solves the above-mentioned conventional problems, and an object thereof is to provide a highly reliable capacitive element using a high dielectric thin film as a capacitive insulating film.
【０００６】[0006]
【課題を解決するための手段】この目的を達成するため
に本発明の容量素子は、容量素子の上電極および下電極
である貴金属電極とアルミニウムを主成分とする金属配
線膜とをチタンまたはチタンを主成分とする１層または
２層以上の金属膜を介して電気的に接続した構成を有し
ている。In order to achieve this object, a capacitive element of the present invention comprises a noble metal electrode which is an upper electrode and a lower electrode of the capacitive element and a metal wiring film containing aluminum as a main component of titanium or titanium. It has the structure electrically connected via the metal film of 1 layer or 2 layers or more which has as a main component.
【０００７】[0007]
【作用】この構成によって、配線工程での熱処理におい
て貴金属電極とアルミニウムを主成分とする金属配線膜
との間の反応を抑制できるので、鬆や欠陥のないコンタ
クト部を有する信頼性の高い容量素子を提供できる。With this structure, the reaction between the noble metal electrode and the metal wiring film containing aluminum as the main component can be suppressed during the heat treatment in the wiring process, so that a highly reliable capacitive element having a contact portion free from voids or defects. Can be provided.
【０００８】[0008]
【実施例】以下本発明の一実施例について、図面を参照
しながら説明する。図１は本発明の第１の実施例におけ
る容量素子の要部断面図である。図１において、１は集
積回路が作り込まれた支持基板、２は支持基板１の上に
形成された膜厚１０から１００ｎｍのＴｉ膜、３はＴｉ
膜２の上に形成された膜厚１００〜３００ｎｍの第１の
Ｐｔ電極、４は第１のＰｔ電極３上に形成された膜厚２
０〜３００ｎｍの（ＢａxＳｒ1-x）ＴｉＯ3 膜、５は膜
厚１００〜３００ｎｍの第２のＰｔ電極、６は絶縁保護
膜、７は絶縁保護膜６に設けられたコンタクト孔、８は
Ａｌ（１％Ｓｉ−０．５％Ｃｕ）合金からなる金属配線
膜、９はコンタクト孔７を含む部分に設けられた厚さ５
〜１５０ｎｍのチタン・タングステン（以下ＴｉＷと略
す）膜である。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of an essential part of a capacitor according to the first embodiment of the present invention. In FIG. 1, reference numeral 1 is a support substrate in which an integrated circuit is formed, 2 is a Ti film having a film thickness of 10 to 100 nm formed on the support substrate 1, and 3 is Ti.
The first Pt electrode 4 having a film thickness of 100 to 300 nm formed on the film 2 is the film thickness 2 formed on the first Pt electrode 3
0-300 nm (Ba x Sr 1-x ) TiO 3 film, 5 is a second Pt electrode with a film thickness of 100-300 nm, 6 is an insulating protective film, 7 is a contact hole provided in the insulating protective film 6, 8 Is a metal wiring film made of an Al (1% Si-0.5% Cu) alloy, and 9 is a thickness 5 provided in a portion including the contact hole 7.
It is a titanium-tungsten (hereinafter abbreviated as TiW) film of 150 nm.
【０００９】以上のように本実施例の容量素子では、第
１のＰｔ電極３、第２のＰｔ電極５とＡｌを主成分とす
る金属配線膜８とがＴｉＷ膜９を介して電気的に接続さ
れているので第１および第２のＰｔ電極３、５と金属配
線膜８とが反応を起こすことがなく、コンタクト部に鬆
や欠陥を生じない。As described above, in the capacitive element of this embodiment, the first Pt electrode 3, the second Pt electrode 5 and the metal wiring film 8 containing Al as a main component are electrically connected via the TiW film 9. Since they are connected, the first and second Pt electrodes 3 and 5 and the metal wiring film 8 do not react with each other, and voids or defects do not occur in the contact portion.
【００１０】次に本発明の第２の実施例における容量素
子について説明する。図２は本発明の第２の実施例にお
ける容量素子の要部断面図である。図２において図１に
示す第１の実施例と同一箇所には同一符号を付して説明
を省略する。なお本実施例が図１に示す第１の実施例と
異なる点は、コンタクト孔７において第１のＰｔ電極
３、第２のＰｔ電極５と金属配線膜８との間にＴｉＷ膜
９と窒化チタン（以下ＴｉＮと略す）膜１０からなる多
重膜を介在させた点である。Next, a capacitance element according to the second embodiment of the present invention will be described. FIG. 2 is a sectional view of an essential part of a capacitive element according to the second embodiment of the present invention. In FIG. 2, the same parts as those of the first embodiment shown in FIG. The present embodiment is different from the first embodiment shown in FIG. 1 in that in the contact hole 7, the TiW film 9 and the nitride film are formed between the first Pt electrode 3, the second Pt electrode 5 and the metal wiring film 8. This is a point in which a multiple film made of a titanium (hereinafter abbreviated as TiN) film 10 is interposed.
【００１１】図１に示す第１の実施例と同様に、集積回
路が作り込まれた支持基板１上に膜厚１０〜１００ｎｍ
のＴｉ膜２、膜厚１００〜３００ｎｍの第１のＰｔ電極
３が形成されており、第１のＰｔ電極３の上には容量絶
縁膜として膜厚２０〜３００ｎｍの（ＢａxＳｒ1-x）Ｔ
ｉＯ3 ４が形成されており、その上に膜厚１００〜３０
０ｎｍの第２のＰｔ電極５が形成され、シリコン酸化膜
からなる絶縁保護膜６には第１のＰｔ電極３、第２のＰ
ｔ電極５にそれぞれ通じるコンタクト孔７が形成されて
いる。コンタクト孔７を含んで厚さ５〜５０ｎｍのＴｉ
Ｗ膜９および厚さ５〜５０ｎｍのＴｉＮ膜１０が形成さ
れており、その上にＡｌ（１％Ｓｉ−０．５％Ｃｕ）合
金からなる金属配線膜８が形成されている。Similar to the first embodiment shown in FIG. 1, a film thickness of 10 to 100 nm is formed on a supporting substrate 1 having an integrated circuit built therein.
Ti film 2 and a first Pt electrode 3 having a film thickness of 100 to 300 nm are formed on the first Pt electrode 3 as a capacitive insulating film (Ba x Sr 1-x ) having a film thickness of 20 to 300 nm. ) T
iO 34 is formed and a film thickness of 100 to 30 is formed thereon.
The second Pt electrode 5 of 0 nm is formed, and the first Pt electrode 3 and the second P electrode are formed on the insulating protection film 6 made of a silicon oxide film.
Contact holes 7 are formed so as to communicate with the t-electrodes 5, respectively. Ti with a thickness of 5 to 50 nm including the contact hole 7
A W film 9 and a TiN film 10 having a thickness of 5 to 50 nm are formed, and a metal wiring film 8 made of an Al (1% Si-0.5% Cu) alloy is formed thereon.
【００１２】以上のように本実施例の容量素子では、第
１のＰｔ電極３、第２のＰｔ電極５とＡｌを主成分とす
る金属配線膜８とがＴｉＷ膜９およびＴｉＮ膜１０を介
して電気的に接続されているので第１および第２のＰｔ
電極３、５と金属配線膜８とが反応を起こすことがな
く、コンタクト部に鬆や欠陥を生じない。As described above, in the capacitive element of the present embodiment, the first Pt electrode 3, the second Pt electrode 5 and the metal wiring film 8 containing Al as a main component are interposed by the TiW film 9 and the TiN film 10. Are electrically connected to each other, so that the first and second Pt
The electrodes 3 and 5 and the metal wiring film 8 do not react with each other, and voids or defects do not occur in the contact portion.
【００１３】なお第１の実施例ではＴｉＷ膜９を第１、
第２のＰｔ電極３、５と金属配線膜８との反応のバリア
層として用いたが、ＴｉＮ膜またはＴｉ膜をバリア層と
して用いても同様の効果がある。さらに、第２の実施例
ではＴｉＷ膜９の上にＴｉＮ膜１０を重ねているが、Ｔ
ｉＷ膜、ＴｉＮ膜およびＴｉ膜の組み合わせにおいてそ
の順序、層数または重ね合わせの組合せが異なっても同
様の効果が得られる。In the first embodiment, the TiW film 9 is formed in the first,
Although it was used as a barrier layer for the reaction between the second Pt electrodes 3 and 5 and the metal wiring film 8, the same effect can be obtained by using a TiN film or a Ti film as a barrier layer. Further, in the second embodiment, the TiN film 10 is superposed on the TiW film 9, but
In the combination of the iW film, the TiN film and the Ti film, the same effect can be obtained even if the order, the number of layers or the combination of the layers are different.
【００１４】また第１および第２の実施例では高誘電体
薄膜４として（ＢａxＳｒ1-x）ＴｉＯ3膜を用いたが、
ＳｒＴｉＯ3膜、ＢａＴｉＯ3 膜、ＰＺＴ膜またはＰＬ
ＺＴ膜など他の高誘電体薄膜を用いても同様の効果が得
られる。In the first and second embodiments, the (Ba x Sr 1-x ) TiO 3 film is used as the high dielectric thin film 4, but
SrTiO 3 film, BaTiO 3 film, PZT film or PL
The same effect can be obtained by using another high dielectric thin film such as a ZT film.
【００１５】[0015]
【発明の効果】以上のように本発明は、容量素子の電極
である貴金属電極とアルミニウムを主成分とする金属配
線膜とをチタンを主成分とする１層または２層以上の金
属膜を介して電気的に接続した構成により、コンタクト
部に反応生成物、鬆または欠陥のない信頼性の高い容量
素子を実現できるものである。As described above, according to the present invention, the noble metal electrode, which is the electrode of the capacitor, and the metal wiring film containing aluminum as a main component are provided through one or more metal films containing titanium as a main component. With such a structure in which the contact portion is electrically connected, a highly reliable capacitor element having no reaction product, void, or defect in the contact portion can be realized.
【図１】本発明の第１の実施例における容量素子の要部
断面図FIG. 1 is a sectional view of an essential part of a capacitive element according to a first embodiment of the present invention.
【図２】本発明の第２の実施例における容量素子の要部
断面図FIG. 2 is a cross-sectional view of an essential part of a capacitor according to a second embodiment of the present invention.
【図３】従来の容量素子の要部断面図FIG. 3 is a cross-sectional view of a main part of a conventional capacitive element
１ 支持基板 ３ 第１のＰｔ電極（第１の貴金属電極） ４ （ＢａxＳｒ1-x）ＴｉＯ3膜（容量絶縁膜） ５ 第２のＰｔ電極（第２の貴金属電極） ６ 絶縁保護膜 ７ コンタクト孔 ８ 金属配線膜 ９ ＴｉＷ膜（チタンを主成分とする金属膜）1 Support Substrate 3 First Pt Electrode (First Noble Metal Electrode) 4 (Ba x Sr 1-x ) TiO 3 Film (Capacitance Insulation Film) 5 Second Pt Electrode (Second Noble Metal Electrode) 6 Insulation Protective Film 7 Contact hole 8 Metal wiring film 9 TiW film (metal film containing titanium as a main component)
───────────────────────────────────────────────────── フロントページの続き (72)発明者 那須 徹 大阪府門真市大字門真1006番地 松下電子 工業株式会社内 (72)発明者 松田 明浩 大阪府門真市大字門真1006番地 松下電子 工業株式会社内 (72)発明者 井上 敦雄 大阪府門真市大字門真1006番地 松下電子 工業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Toru Nasu Toru Nasu 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electronics Co., Ltd. (72) Akihiro Matsuda 1006 Kadoma, Kadoma City, Osaka Matsushita Electronics Co., Ltd. 72) Inventor Atsushi Inoue 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electronics Industrial Co., Ltd.
Claims (2)
形成された第１の貴金属電極と、前記第１の貴金属電極
の表面上に形成された高誘電率を有する誘電体薄膜から
なる容量絶縁膜と、前記容量絶縁膜の表面上に前記第１
の貴金属電極と接触することなく形成された第２の貴金
属電極と、前記第１の貴金属電極、容量絶縁膜および第
２の貴金属電極を覆いかつ前記第１の貴金属電極および
第２の貴金属電極をそれぞれ独立に配線するためのコン
タクト孔を備えた絶縁保護膜と、前記絶縁保護膜の表面
上に選択的に形成されたアルミニウムを主成分とする金
属配線膜とからなり、前記第１の貴金属電極または第２
の貴金属電極と前記金属配線膜とがチタンまたはチタン
を主成分とする１層または２層以上の金属膜を介して電
気的に接続されている容量素子。1. A support substrate, a first noble metal electrode formed on one surface of the support substrate, and a dielectric thin film having a high dielectric constant formed on the surface of the first noble metal electrode. A capacitive insulating film, and the first insulating film on the surface of the capacitive insulating film.
A second noble metal electrode formed without contact with the other noble metal electrode, and covering the first noble metal electrode, the capacitive insulating film and the second noble metal electrode and the first noble metal electrode and the second noble metal electrode. The first noble metal electrode is composed of an insulating protective film having a contact hole for independent wiring, and a metal wiring film containing aluminum as a main component selectively formed on the surface of the insulating protective film. Or second
The capacitive element in which the noble metal electrode and the metal wiring film are electrically connected via titanium or one or more metal films containing titanium as a main component.
タングステンまたは窒化チタンである請求項１記載の容
量素子。2. The metal film containing titanium as a main component is titanium.
The capacitive element according to claim 1, which is tungsten or titanium nitride.
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26454792A JPH06120072A (en) | 1992-10-02 | 1992-10-02 | Capacitive element |
| EP93304609A EP0574275B1 (en) | 1992-06-12 | 1993-06-14 | Semiconductor device having capacitor |
| EP97106056A EP0789395B1 (en) | 1992-06-12 | 1993-06-14 | Manufacturing method for semiconductor device having capacitor |
| DE69317940T DE69317940T2 (en) | 1992-06-12 | 1993-06-14 | Semiconductor device with capacitor |
| DE69333864T DE69333864T2 (en) | 1992-06-12 | 1993-06-14 | Manufacturing method for semiconductor device with capacitor |
| US08/778,953 US5717233A (en) | 1992-06-12 | 1997-01-06 | Semiconductor device having capacitior and manufacturing method thereof |
| US08/947,712 US6126752A (en) | 1992-06-12 | 1997-10-09 | Semiconductor device having capacitor and manufacturing apparatus thereof |
| US08/950,920 US6080617A (en) | 1992-06-12 | 1997-10-15 | Semiconductor device having capacitor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26454792A JPH06120072A (en) | 1992-10-02 | 1992-10-02 | Capacitive element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06120072A true JPH06120072A (en) | 1994-04-28 |
Family
ID=17404791
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26454792A Pending JPH06120072A (en) | 1992-06-12 | 1992-10-02 | Capacitive element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06120072A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239462B1 (en) | 1997-07-24 | 2001-05-29 | Matsushita Electronics Corporation | Semiconductor capacitive device having improved anti-diffusion properties and a method of making the same |
| US6281536B1 (en) | 1998-04-08 | 2001-08-28 | Nec Corporation | Ferroelectric memory device with improved ferroelectric capacity characteristic |
| US6384440B1 (en) | 1999-11-10 | 2002-05-07 | Nec Corporation | Ferroelectric memory including ferroelectric capacitor, one of whose electrodes is connected to metal silicide film |
| KR100393197B1 (en) * | 1996-10-31 | 2003-11-01 | 삼성전자주식회사 | Ferroelectric capacitor and manufacturing method thereof |
-
1992
- 1992-10-02 JP JP26454792A patent/JPH06120072A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100393197B1 (en) * | 1996-10-31 | 2003-11-01 | 삼성전자주식회사 | Ferroelectric capacitor and manufacturing method thereof |
| US6239462B1 (en) | 1997-07-24 | 2001-05-29 | Matsushita Electronics Corporation | Semiconductor capacitive device having improved anti-diffusion properties and a method of making the same |
| US6809000B2 (en) | 1997-07-24 | 2004-10-26 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| US6281536B1 (en) | 1998-04-08 | 2001-08-28 | Nec Corporation | Ferroelectric memory device with improved ferroelectric capacity characteristic |
| US6384440B1 (en) | 1999-11-10 | 2002-05-07 | Nec Corporation | Ferroelectric memory including ferroelectric capacitor, one of whose electrodes is connected to metal silicide film |
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