JP2001210641A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reliable semiconductor device, having wiring whose main component is copper. SOLUTION: In the semiconductor device with wiring whose main component is copper, the wiring is made to contain copper dioxide.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a wiring having copper as a main conductive film.

[0002]

2. Description of the Related Art In recent years, with the development of information communication equipment, DRAM
The processing capacity required for semiconductor devices (hereinafter simply referred to as “devices”) including dynamic random access memories (DRAMs) has become increasingly severe year by year, and wiring using aluminum (Al) as a main conductive film (hereinafter referred to as “Al wiring”) In the device using ()), signal delay is a problem. For this reason, a wiring using copper (Cu) having a lower electric resistance than Al as a main conductive film (hereinafter referred to as a Cu wiring) has been studied as a wiring material replacing the Al wiring.

In general, in the manufacture of a semiconductor device, the coefficient of linear expansion of a material is an important parameter related to mechanical reliability. During the heat treatment of a structure made of different materials, thermal stress is generated, and peeling or cracking occurs.

The coefficient of linear expansion of Cu expected as a wiring material is 16.5 × 10 ⁶ / K. On the other hand, the interlayer insulating film on which the Cu wiring is formed is silicon oxide having a linear expansion coefficient of 0.6 × 10 ⁶ / K, which is extremely lower than the linear expansion coefficient of Cu. Therefore, during the formation of the Cu wiring or during the subsequent heat treatment, thermal stress occurs due to the difference in the linear expansion coefficient between Cu and the surrounding material, causing cracks in the interlayer insulating film and peeling of the interface between the wiring and the interlayer insulating film. And other mechanical failures.

Therefore, in a conventional semiconductor device having a Cu wiring, development has been made with an emphasis on improving the mechanical strength of the interlayer insulating film in order to prevent cracks and cracks in the interlayer insulating film.

[0006]

As described above, in recent semiconductor devices, speeding up has been promoted, and Cu is being studied as a wiring material. On the other hand, the interlayer insulating film on which the Cu wiring is formed has been developed in the direction of lowering the dielectric constant, and the mechanical strength has been significantly reduced.

The coefficient of linear expansion of Cu is 16.5 × 10 ⁶ / K.
On the other hand, the interlayer insulating film on which the Cu wiring is formed is silicon oxide having a linear expansion coefficient of 0.6 × 10 ⁶ / K, which is extremely lower than the linear expansion coefficient of Cu. Therefore, when forming the Cu wiring,
In the subsequent heat treatment, thermal stress is generated due to a difference in linear expansion coefficient between Cu and the surrounding material, and mechanical defects such as peeling, cracking, and cracking are generated.

A first object of the present invention is to provide a highly reliable semiconductor device. A second object of the present invention is to provide a semiconductor device having excellent manufacturing cost. A third object of the present invention is to provide a semiconductor device having a wiring containing Cu as a main constituent element, which is less likely to peel, break, or break due to thermal stress.

[0009]

As described above, in recent semiconductor devices, Cu wiring and low dielectric constant interlayer insulating films have been studied with the increase in signal speed. As a result, problems related to mechanical reliability such as cracks, cracks, and peeling have become apparent.

The inventors of the present invention have proposed that copper dioxide (Cu ₂ O)
It has been clarified that the inclusion of the compound enables the linear expansion coefficient to be lower than that of pure Cu. FIG. 2 shows the dependency of the linear expansion coefficient of the Cu / Cu ₂ O composite alloy on the Cu ₂ O content. Cu
With linear expansion coefficient increased ₂ O content ratio is reduced, Cu ₂ O content ratio is 70 vol.% And sometimes, pure ^{Cu (16.5 × 10 ~ 6 /} K) approximately half of ^{(8.2 × 10 ~ 6 / K} ) by also revealed that it lowered to 20 vol.% even when containing about 80% pure ^{Cu (13 × 10 ~ 6 /} K).

Further, as shown in FIG. 3, it was revealed that the Cu / Cu ₂ O composite alloy can reduce Young's modulus as compared with conventional pure Cu. Pure Cu when the content of Cu ₂ O is 70vol.%
(130 GPa), about 20% (30 GPa), and even when containing 20 vol.%, It drops to about 65% (85 GPa) of pure Cu. Therefore, it was clarified that the Cu / Cu ₂ O composite alloy has a stress relaxation effect of peripheral materials.

The object of the present invention is solved, for example, by using a Cu / Cu ₂ O alloy as a main constituent material of a wiring formed in a semiconductor device (a material most contained among the materials forming the wiring). You.

According to the above configuration, in a semiconductor device having a wiring mainly composed of copper and formed on a semiconductor substrate via an insulating film, Cu ₂ O is contained in Cu to reduce thermal stress. And a highly reliable semiconductor device having excellent resistance to peeling, cracking, disconnection failure, and the like is provided.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. FIG. 1 is a schematic diagram of a cross section of the semiconductor device of the present embodiment, and FIG. 2 shows the linear expansion coefficient of the Cu / Cu ₂ O composite alloy.
Cu ₂ O content rate dependent, Figure 3 is the Young's modulus of Cu / Cu ₂ O alloy composite
Cu ₂ O content rate dependent, FIG. 4 is a Cu ₂ O content rate dependency of resistivity at room temperature of Cu / Cu ₂ O alloy composite.

As shown in FIG. 1, the semiconductor device of this embodiment includes a transistor formed on a main surface of a silicon substrate 1, a storage capacitor 10 electrically connected to the transistor, and an electrically connected memory cell. Wiring 22 connected to and forming a circuit
Is a memory device composed of

The transistor is composed of a gate oxide film 2, a gate electrode 3, and a diffusion layer (source and drain regions: not shown), each of which is electrically insulated by an element isolation film 9. The gate oxide film 2 is made of a dielectric film such as a silicon oxide film or a silicon nitride film, or a laminated structure of these. The gate electrode 3 is made of, for example, a polycrystalline silicon film, a metal film, a metal silicide film, or a laminated structure of these. A silicon oxide film 5 is formed on the gate oxide film 3 and on the side walls. Further, the bit line 7 is connected via the contact plug 6. For example, BPSG
(Boron-doped Phospho Silicate Glass) membrane, SOG (S
pin On Glass) film or TEOS (Tetra-Ethyl-Ortho-S)
ilicate) film or an interlayer insulating film 8 made of a silicon oxide film or a nitride film formed by a chemical vapor deposition method or a sputtering method.

A contact plug made of, for example, polycrystalline silicon is provided on the other side of the diffusion layer (not shown) of the transistor.
The storage capacitor 10 is formed through the connection 4. Storage capacity 10
Has a laminated structure of a lower electrode 13, a dielectric film 12, and an upper electrode 11. In addition to this, for example, titanium nitride (TiN)
It may have a laminated structure in which a conductive film such as a film is adjacent to the lower electrode 13 and added to the side opposite to the dielectric film 12. Here, the upper electrode 11 is formed up to a region having no counter electrode (lower electrode 13). Further, the dielectric film 12 is, for example, (Ba, S
_{r) TiO 3 (BST),} PbTiO 3, PbLaTiO 3, BaTiO 3, SrTiO 3, P
It is made of a high and ferroelectric substance such as b (Zr, Ti) O ₃ (PZT), and these are formed by a sputtering method, a chemical vapor deposition method, a laser ablation method, or the like. Although the storage capacitor structure shown in the figure has a structure in which a storage capacitor is formed inside a cylindrical hole, it does not necessarily have to be as shown in the figure, for example, a parallel plate storage capacitor, or Alternatively, a structure in which the outside of the cylinder has a storage capacity, or a structure in which the inner wall and the outer wall of the cylinder have a storage capacity may be used. Further, portions other than the storage capacitor 10 are covered with the interlayer insulating film 8.

The upper electrode 11 and the lower electrode 13 of the storage capacitor 10 are made of titanium nitride (TiN), tungsten (W), ruthenium (Ru), platinum (Pt), iridium (Ir), or a precious metal element thereof. And alloys to which palladium (Pd), cobalt (Co), nickel (Ni), and titanium (Ti) are added, or ruthenium oxide and iridium oxide. These are formed by a sputtering method, a chemical vapor deposition method, an evaporation method, or the like.

On the upper surface of the storage capacitor 10, the wiring 22 and the wiring 22 and the upper electrode of the storage capacitor 10 formed thereunder are formed.
A plug 21 for electrically connecting 13 is formed in interlayer insulating film 25. Here, it is desirable that the wiring 22 and the plug 21 be covered with barrier metals (23, 24), respectively, as shown in FIG. 1, for example, titanium nitride (TiN), tungsten (W), tantalum (Ta). ), Tantalum nitride (TaN),
More preferably, ruthenium (Ru), platinum (Pt), iridium (Ir), or palladium (Pd), cobalt (Co), nickel (Ni), titanium (Ti)
Alloy, or ruthenium oxide or iridium oxide. These barrier metals are formed by a sputtering method, a chemical vapor deposition method, an evaporation method, or the like.

Wiring 22, plug 21, barrier metal (23, 2
4), a plurality of wiring layers made of the interlayer insulating film 25 are formed so as to be electrically connected to each other, and after forming a portion to be electrically connected to the outside, the wiring layer is covered with the protective film 27. In addition, the interlayer insulating film 25 may use the same material as the interlayer insulating film 8.

The wiring 22 and the plug 21 of the semiconductor device according to the present embodiment are covered with a barrier metal around the periphery thereof, but are not necessarily required to be entirely covered.
For example, the barrier metal 24a may not be formed.

In this embodiment, the plug 21, the wiring 22,
The wirings and plugs of a plurality of wiring layers are formed of an alloy of copper and copper dioxide (Cu ₂ O), and are formed by, for example, a sputtering method or an evaporation method. In addition,
The film formation method is not limited to this. Further, as a sputtering target, one obtained by sintering Cu and Cu ₂ O is used.

Hereinafter, the function and effect of the semiconductor device of this embodiment will be described. In the development of semiconductor devices, cracking, peeling,
Problems such as cracks are important issues related to mechanical reliability. In recent semiconductor devices, the speed of signals has been increased, and Cu is being studied as a wiring material.
On the other hand, an interlayer insulating film on which a Cu wiring is formed has been developed in the direction of lowering the dielectric constant.

The coefficient of linear expansion of Cu is 16.5 × 10 ⁶ / K.
On the other hand, the interlayer insulating film on which the Cu wiring is formed is silicon oxide having a linear expansion coefficient of 0.6 × 10 ⁶ / K, which is extremely lower than the linear expansion coefficient of Cu. Therefore, when forming the Cu wiring,
In the subsequent heat treatment, thermal stress occurs due to the difference in linear expansion coefficient between Cu and the surrounding material, and mechanical defects such as cracks, cracks, and peeling occur in the interlayer insulating film.

Conventionally, attempts have been made to increase the mechanical strength of the interlayer insulating film. However, it is essential to lower the dielectric constant of the interlayer insulating film. It is becoming difficult to improve mechanical strength.

The present inventors have sought a measure for improving the mechanical reliability of the wiring and have found a method of improving the mechanical characteristics of the Cu wiring. That is, the linear expansion coefficient of the wiring material is reduced, that is, the linear expansion coefficient of the wiring material is made smaller than the Cu value (16.5 × 10 to ⁶ / K), and the Young's modulus of the wiring material is reduced, that is, the wiring material is reduced. To make the Young's modulus smaller than the value of Cu (130 GPa). Specifically, a composite alloy of Cu and Cu ₂ O is used.

FIG. 2 shows the linear expansion coefficient of the alloy of Cu and Cu ₂ O, Cu ₂ O.
It shows the dependency on the mixing ratio (vol.%). From the figure,
It was clarified that the one containing Cu ₂ O with respect to pure Cu can lower its linear expansion coefficient. In other words, it is clear that by reducing the difference in the coefficient of linear expansion from the silicon oxide, which is the interlayer insulating film surrounding the periphery, the thermal stress during the heat treatment process can be reduced and defects such as cracks, cracks, and peeling can be prevented. I made it.

Further, it has been clarified that the Young's modulus of the Cu / Cu ₂ O composite alloy is better than that of pure Cu. Figure 3 shows the Young's modulus of Cu / Cu ₂ O composite alloy
_It depends on the 2O content. As shown in the figure, compared to pure Cu, Cu
It was clarified that those containing ₂ O had a lower Young's modulus. In other words, it was clarified that the wiring using the Cu / Cu ₂ O composite alloy has an effect of relaxing the stress of the peripheral members.

As described above, in the present composite alloy, the linear expansion coefficient and the Young's modulus can be reduced stepwise by increasing the mixing ratio of Cu ₂ O. Specifically, Cu ₂ O
Is 10 vol.%, The linear expansion coefficient is about 15 × 10
~ ⁶ / ℃, Young's modulus becomes about 100 GPa. As a value representing the magnitude of the thermal stress, when considering the product of the elastic modulus and the linear expansion coefficient, as compared with Al which is often used in conjunction with Cu as the material of the wiring, but its value is increased by elemental Cu, Cu ₂ O to 10
It can be reduced to almost the same when vol.% is included. Therefore, judging from this viewpoint, it is desirable that Cu ₂ O be contained at 10 vol.% Or more. If the was further increased compounding ratio up to 50 vol.%, The linear expansion coefficient of about 10 * 10 ~ ⁶ / ℃, Young's modulus of about
Can be reduced to 50 GPa. As the compounding ratio is further increased, both values are further decreased.

The evaluation of these characteristics by the inventors of the present application is performed in a range where the content ratio of Cu ₂ O is 80 vol.% Or less. This is because the Cu / Cu ₂ O composite alloy becomes brittle with an increase in Cu ₂ O, making processing difficult. However, if the compounding ratio of Cu ₂ O is 80 vol.% Or less, for example, a sputter target can be produced.
/ Cu ₂ O composite alloy wiring can be formed.

When a Cu / Cu ₂ O composite alloy is used as the wiring material, the wiring resistivity is also an important factor. FIG. 4 shows the dependency of the resistivity of the Cu / Cu ₂ O composite alloy on the mixing ratio of Cu ₂ O. As shown in the figure, the case of using a Cu / Cu ₂ O alloy composite as a wiring material, with an increase in the content ratio of Cu ₂ O to Cu ₂ O is an insulating material, the resistance rate compared to pure Cu Increases. The increase in wiring resistance due to the increase in the resistivity of wiring material
This can be overcome by increasing the cross-sectional area of the wiring.
In semiconductor devices such as AM, it is expected that the degree of integration will be further accelerated in the future, and it is conceivable that the increase in wiring cross-sectional area will become severe.

Cu has been studied because it has a lower resistivity than Al and can prevent signal delay in a semiconductor device. That is, the resistivity of the Cu / Cu ₂ O alloy composite resistivity Al (at 2.7 × 10 RT _- ⁸ _Ω · m) if so smaller than, I small signal delay than the Al wiring of a conventional semiconductor device Wiring can be formed without increasing the wiring cross-sectional area. That is, the Cu ₂ O compounding ratio is preferably in a range where the resistivity of the Cu / Cu ₂ O composite alloy is smaller than that of Al in comparison of the resistivity of the Cu / Cu ₂ O composite alloy and Al. From FIG. 4, the resistivity of the Cu / Cu ₂ O composite alloy Cu ₂ O content ratio is 20 vol.%
At the time of 2.6 × 10 to ⁸ Ω · m, which is lower than the value of Al. That is, the mixing ratio of Cu ₂ O is more preferably 20 vol.% Or less.

As shown in FIG. 1, the semiconductor device of the present embodiment uses a Cu / Cu ₂ O composite alloy for the wiring 22 and the plug 21 so that the linear expansion coefficient is smaller than when pure Cu is used. In other words, by reducing the thermal stress generated in the heat treatment process, the effect of suppressing the occurrence of mechanical defects such as cracks, cracks, and peeling can be obtained.

In the above-mentioned Cu / Cu ₂ O composite alloy, the Young's modulus is lower than that of pure Cu, and the stress of peripheral members can be reduced, so that mechanical defects such as cracks, cracks, peeling, etc., occur. Is obtained.

Furthermore, if the mixing ratio of Cu ₂ O is set to 20 vol.% Or less, the mechanical reliability can be improved without increasing the wiring cross-sectional area, so that miniaturization and high integration of the element are not hindered. Thus, an effect that a semiconductor device can be manufactured can be obtained.

In the semiconductor device of this embodiment,
It is described that the wiring is composed of an alloy containing Cu as a main constituent element and containing Cu ₂ O, and other configurations may be other than the present embodiment. Further, Cu ₂ O contained in Cu does not necessarily need to be contained uniformly.

[0037]

According to the present invention, the mechanical characteristics of the wiring are improved, and defects such as peeling, cracks, and cracks are reduced. As a result, a highly reliable semiconductor device can be obtained at low cost.

[Brief description of the drawings]

FIG. 1 is a schematic view showing a cross section of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is an experimental result of dependency of a linear expansion coefficient of a Cu / Cu ₂ O composite alloy on a Cu ₂ O compounding ratio.

FIG. 3 is an experimental result of the dependency of the Young's modulus of the Cu / Cu ₂ O composite alloy on the Cu ₂ O content.

FIG. 4 is an experimental result of the dependency of the resistivity of the Cu / Cu ₂ O composite alloy on the mixing ratio of Cu ₂ O.

[Explanation of symbols]

1 ... silicon substrate, 2 ... gate oxide film, 3 ... gate electrode, 4, 6 ... contact plug, 5 ... silicon oxide film, 7
... Bit line, 9 ... Element isolation film, 10 ... Storage capacitance, 11 ...
・ Upper electrode, 12 ・ ・ ・ Dielectric film, 13 ・ ・ ・ Lower electrode, 21 ・ ・ ・ Contact plug, 8, 25, 26 ・ ・ ・ Interlayer insulating film, 27 ・ ・ ・ Protective film, 22 ・ ・ ・ Wiring , 23, 24 ... barrier metal.

Continued on the front page F-term (reference)

Claims (7)

[Claims] 1. A semiconductor device comprising: a semiconductor substrate; and a wiring formed on one main surface side of the semiconductor substrate and mainly composed of a Cu / Cu ₂ O alloy. 2. The semiconductor device according to claim 1, wherein the Cu ₂ O content of the wiring is 80 vol.% Or less. 3. The semiconductor device according to claim 1, wherein the Cu ₂ O content of the wiring is not less than 10 vol.% And not more than 80 vol.%. 4. A semiconductor device having a wiring having copper as a main constituent element formed on a semiconductor substrate via an insulating film, wherein at least a part of the wiring contains Cu / Cu ₂ O. A semiconductor device whose content is 80 vol.% Or less. 5. The semiconductor device according to claim 1, wherein a barrier film mainly composed of ruthenium oxide or iridium oxide is adjacent to at least a part of the wiring. 6. The semiconductor device according to claim 1, wherein at least a part of the wiring includes titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum nitride (TaN),
A semiconductor device in which a barrier film mainly composed of a material selected from the group consisting of ruthenium (Ru), platinum (Pt), and iridium (Ir) is adjacent. 7. The method according to claim 6, wherein the barrier film includes palladium (Pd), cobalt (Co), nickel (Ni), titanium (T
A semiconductor device to which an element selected from i) is added.