JPH08236719A - Platinum thin film and semiconductor device, and method of their fabrication - Google Patents

Abstract

PURPOSE: To provide a semiconductor device having a fine memory preferable for high integration using a ferroelectric substance as a capacitor insulating film. CONSTITUTION: A platinum lower electrode 62 is provided on a TiN film 61 being a diffusion preventing conductor layer, on which a ferroelectric thin film 63 is provided. A ferroelectric capacitor is constructed with the platinum lower electrode 62 and the ferroelectric thin film 63, etc. An element forming a conductive nitride is added to the platinum lower electrode and part or the whole of the element is nitrided. For this, the TiN film 61 is prevented from being oxidized upon formation of the ferroelectric thin film 63.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a large scale integrated circuit (LS).
The present invention relates to a semiconductor device having a memory capacitor suitable for I), a manufacturing method thereof, a platinum thin film and a manufacturing method thereof.

[0002]

2. Description of the Related Art A semiconductor device having an LSI such as a dynamic random access memory (DRAM) has problems such as an increase in capacitor area and a complicated structure due to high integration. Therefore, instead of silicon oxide and nitride that have been conventionally used as a capacitor insulating film, it has been considered to use a ferroelectric material having an extremely large relative dielectric constant of several hundreds to several thousands. .
Further, since a ferroelectric substance has a spontaneous polarization and its direction can be reversed by an external electric field, it has been attempted to form a nonvolatile memory by using this characteristic. A conventional memory using a ferroelectric substance is described in, for example, JP-A-63-201998.

As a ferroelectric thin film used in the above memory, an oxide ferroelectric such as lead zirconate titanate or strontium barium titanate is generally used. Since many ferroelectrics have a crystallization temperature of 500 ° C. or higher, a platinum electrode having heat resistance is formed on a single crystal substrate such as magnesium oxide, and a ferroelectric thin film is formed on the platinum electrode for use. . However, in order to apply to a memory, a platinum electrode must be formed on a silicon substrate. Since platinum reacts with silicon to form silicide, it is not possible to adopt a structure in which the platinum electrode is in direct contact with the silicon substrate or polycrystalline silicon. So, for example, 1989 IEE International Solid State Circuit Conference Digest No. 2
42-243 (1989 IEEE Int. Solid-State C
ircuits Conf. Digest pp. 242 to 243), a ferroelectric capacitor is formed on the interlayer insulating film, and the source or drain of the MOS transistor is connected to the wiring conductive layer such as aluminum from outside the capacitor region. I was using it.

However, it is difficult to reduce the memory cell area in the method using the conductive layer for wiring such as aluminum for connecting to the source or drain of the MOS transistor,
The advantage of high integration using ferroelectrics is halved. In order to realize a more highly integrated memory, for example, a semiconductor substrate on which a MOS transistor is formed is covered with an insulating material, and a ferroelectric capacitor is formed thereon, and one electrode of the ferroelectric capacitor and the MOS transistor are formed. It is described in JP-A-3-256358 that the connection to the source or the drain is made by a conductive material embedded inside a contact hole formed in an insulating material.

In order to realize this structure, it is necessary to connect one electrode of the ferroelectric capacitor and the source or drain of the MOS transistor with a conductive material. Polycrystalline silicon is generally used for this conductive material. However, as described above, when platinum and silicon directly contact with each other, they react to form a silicide, or Si diffuses in platinum to form a Si oxide film on the platinum surface, which deteriorates the characteristics of the ferroelectric capacitor. In addition, the element that constitutes the ferroelectric is Si
Problems such as diffusion to the substrate occur.

As a method for solving these problems, as described in JP-A-4-14862 and JP-A-4-181766, Ti and T are deposited between a platinum electrode and Si.
There is a method of providing a diffusion preventing conductive layer of a, TiN or the like.

[0007]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
The conventional techniques described in JP-A No. 62-62 and JP-A-4-181766 have the following problems. That is, in order to form an oxide ferroelectric thin film, it is necessary to form the film in a high temperature oxidizing atmosphere at 500 ° C. or higher, or to heat the film formed at a low temperature in a high temperature oxidizing atmosphere. Then, oxygen diffuses in platinum and oxidizes the diffusion preventing conductive layer to increase contact resistance, or the diffusion preventing conductive material diffuses and oxidizes in platinum to generate series parasitic capacitance. As a method of solving this problem, increasing the thickness of the platinum layer can be considered. However, in a fine capacitor, the aspect ratio becomes large, making it difficult to process platinum. In addition, when the ferroelectric film is formed, the leakage current increases and the dielectric strength voltage decreases at the side wall. Therefore, it is not appropriate to increase the thickness of the platinum layer.

A first object of the present invention is to provide a semiconductor device having a fine memory suitable for high integration by using a ferroelectric material for a capacitor insulating film.

A second object of the present invention is to provide a method of manufacturing such a semiconductor device.

A third object of the present invention is to provide a platinum thin film capable of suppressing the diffusion of oxygen.

A fourth object of the present invention is to provide a method for producing such a platinum thin film.

[0012]

In order to achieve the above first object, a semiconductor device of the present invention has a lower conductive film containing platinum as a main component on a substrate and a ferroelectric film provided thereon. A ferroelectric capacitor including a body thin film and an upper conductive film provided on the body thin film is arranged, an element forming a conductive nitride is added to the lower conductive film, and a part or all of this element is added. Is made to be nitrided.

A diffusion preventing conductive layer made of at least one of Ti, Ta and TiN is preferably disposed between the substrate and the lower conductive film. The lower conductive film is
It is preferable to electrically connect to a desired region of the semiconductor element, for example, a source region or a drain region of a MOS transistor, through the diffusion preventing conductive layer.

As the element forming the conductive nitride, titanium, tantalum, zirconium, niobium, vanadium,
An element such as tungsten can be used. You may use 2 or more types of these elements simultaneously. Further, it is preferable that these elements are added to the conductive film in an amount equal to or more than the solid solution limit of platinum of the elements. Furthermore, the addition amount of these elements is 65 mol% when the element is tantalum.
Hereinafter, when it is another element, it is preferably 50 mol% or less. The nitrided elements are often segregated at the crystal grain boundaries of the conductive film. For the ferroelectric thin film, it is preferable to use an oxide ferroelectric such as lead zirconate titanate, lead barium zirconate titanate, barium strontium titanate, and a bismuth-based layered ferroelectric.

In order to achieve the second object,
The method for manufacturing a semiconductor device according to the present invention comprises sputtering or vapor-depositing an element forming a conductive nitride with platinum in an atmosphere containing nitrogen, and using platinum as a main component, with the above element partially or wholly nitrided. A lower conductive film containing the above is formed on the substrate, a ferroelectric thin film is formed on the lower conductive film, and an upper conductive film is further formed thereon, and the upper and lower conductive films and the ferroelectric thin film are separated from each other. A ferroelectric capacitor is configured.

Before forming the lower conductive film, it is preferable that a diffusion preventing conductive layer is formed on the substrate, and the lower conductive film is formed on the diffusion preventing conductive layer. The lower conductive film, through this diffusion preventing conductive layer,
For example, it may be electrically connected to the source region or the drain region of the MOS transistor.

Further, in order to achieve the third object,
The platinum thin film of the present invention is one in which an element forming a conductive nitride is added and a part or all of the element is nitrided. The elements forming the conductive nitride are the above-mentioned elements, and the preferable addition amount thereof is also as described above.

Further, in order to achieve the fourth object, the method for producing a platinum thin film of the present invention is such that platinum and an element forming a conductive nitride are sputtered or vapor-deposited in an atmosphere containing nitrogen. Then, a platinum thin film containing the above element, which is partially or wholly nitrided, is formed on the substrate.

When a platinum thin film is formed by sputtering, nitrogen is added to an inert gas such as argon in an amount of 10 to 10.
The substrate temperature is 200 to 800 ° C. in an atmosphere containing 90 mol%.
It is preferable to carry out in the range of. When the platinum thin film is formed by vapor deposition, it is preferable that the substrate temperature is in the range of 200 to 800 ° C. in a nitrogen gas atmosphere having a pressure in the range of 0.01 to 100 mTorr.

[0020]

As described above, in order to form the ferroelectric capacitor, the ferroelectric thin film is formed on the lower conductive film containing platinum as a main component. Oxygen diffuses in the conductive film of platinum during the formation of this ferroelectric thin film or during the heat treatment in the oxygen atmosphere required for crystallization, and the diffusion mainly occurs at the crystal grain boundaries. When the above-mentioned additives such as titanium and tantalum are added to platinum, they will be replaced by platinum atoms up to a certain atomic weight ratio to form a solid solution, but if the addition amount is increased, the additive will be precipitated more in the grain boundaries. .

When nitrogen atoms or nitrogen molecules are present when forming a conductive film containing such an additive, elements such as titanium and tantalum are nitrided, and conductive nitrides segregate at grain boundaries. This conductive nitride has an effect as a barrier and suppresses the diffusion of oxygen at the grain boundaries, which is the main diffusion path of oxygen. Therefore, when the above-mentioned additive is added, the diffusion preventing conductive layer is not oxidized because the oxygen permeability of the film is low even if the film thickness of the conductive film is reduced.

[0022]

【Example】

<Example 1> Using TiN as a conductive layer for strengthening adhesion and preventing diffusion, it was examined how much additive was added to a platinum electrode formed thereon to prevent oxidation of a TiN underlayer. . 100n on low resistance silicon substrate
After forming a TiN film of m, a desired amount of titanium or tantalum pellets is placed on a platinum target and sputtered in a nitrogen atmosphere to obtain about 5, 10, 15, respectively.
Film thickness 100 containing 20 mol% titanium or tantalum
A film having platinum as a main component was formed. The sputtering conditions are as shown in Table 1.

Table 1 Sputtering conditions of platinum film Power 400 W Sputtering gas Argon (50%)-Nitrogen (50%) Gas pressure 2 Pa Substrate temperature 500 ° C. This platinum film was observed with a scanning Auger electron microscope to find crystal grains. It was confirmed that the concentration of titanium or tantalum and nitrogen increased along the boundary. Further 100 nm
Thin film of lead zirconate titanate was formed by the sol-gel method.
The sol used was a reaction product of lead acetate, titanium isopropoxide, and zirconium isopropoxide in methoxyethanol. It was crystallized by rapid thermal annealing at 650 ° C. for 2 minutes in an oxygen atmosphere. Further, the lead zirconate titanate thin film was removed, and the resistance between the platinum electrode and the substrate was measured for a sample in which a thin film containing platinum as a main component and a TiN film were sequentially micromachined to 100 μm ² by ion milling using a photomask. Figure 1
It is shown in (a). As can be seen from this figure, as the amount of titanium or tantalum added increases, the degree of oxidation of the underlying TiN layer decreases, so that the resistance value decreases. In particular, when the addition amount of titanium is 5 mol% or more, and when the addition amount of tantalum is 10 mol% or more, the effect is great. It has been known that when the titanium content in platinum exceeds 2%, a compound with platinum precipitates, and the solid solution limit of tantalum is about 19%, so the resistance value decreases at each solid solution limit. Is equivalent to. Similar effects were observed with other additive elements such as zirconium, niobium, vanadium, and tungsten.

Further, a 100 nm platinum layer containing 10% titanium was formed on the 100 nm titanium nitride layer by the above sputtering method.
m and the lead zirconate titanate having a thickness of 100 nm formed by the above-mentioned sol-gel method, a gold upper electrode was formed using a metal mask, and a voltage was applied between the upper electrode and the substrate to obtain dielectric characteristics. I checked. As shown in FIG. 1B, a good hysteresis curve is obtained, and it is understood that oxidation of the diffusion prevention conductive layer is suppressed and power is supplied from the substrate. Further, although the case where the platinum electrode is formed by the sputtering method has been described in the present embodiment, similar results were obtained for the platinum electrode formed by the vacuum evaporation method. Less than,
An example of forming a memory cell using the electrode film containing platinum as a main component will be described.

<Embodiment 2> FIGS. 2 to 6 are manufacturing process diagrams of a semiconductor device according to an embodiment of the present invention. In this example, a semiconductor device having a memory cell having a flat capacitor structure was manufactured. First, as shown in FIG. 2, a switching transistor is formed by a conventional MOSFET forming process. Here, 21 is a p-type semiconductor substrate, 22 is an element isolation insulating film, 23 is a gate oxide film, 24 is a word line to be a gate electrode, 25 and 26 are n-type impurity diffusion layers (phosphorus),
Reference numeral 27 is an interlayer insulating film made of SiO ₂ . Next, C
By VD method (chemical vapor deposition method), the entire surface has a thickness of 50.
nm SiO ₂ 28 and 600 nm thick Si ₃ N ₄ 29
And Si ₃ N ₄ 29 of the film thickness are etched to fill the insulating film between the word lines. Si
O ₂ 28 serves as a base when the bit line is processed in the next step, and has a function of preventing the substrate surface from being exposed and the element isolation insulating film from being scraped.

Next, as shown in FIG. 3, the portion where the bit line contacts the n-type impurity diffusion layer 25 on the substrate surface and the portion where the capacitor electrode contacts the n-type impurity diffusion layer 26 on the substrate surface are photolithographically processed. And a hole is formed by using a dry etching method. Amorphous silicon containing n-type impurities having a thickness of 600 nm is deposited by the CVD method, and is then heat-treated and etched by the film thickness to form polycrystalline silicon inside the hole formed by the above-described etching. 31, 32
Embed

Next, as shown in FIG. 4, CV is applied to the entire surface.
An insulating film 41 made of SiO ₂ is deposited by the D method, and the insulating film 41 above the polycrystalline silicon 31 is formed so that the bit line is electrically connected to the n-type impurity diffusion layer 25 of the substrate.
Open holes by using the photolithography method and the dry etching method. Next, the bit line 42 is formed. A laminated film of metal silicide and polycrystalline silicon was used as the material of the bit line. On this, SiO ₂ 43 having a thickness of 200 nm is deposited. The SiO ₂ 43 and the bit line 42 are processed by the photolithography method and the dry etching method to form the bit line 42 into a desired pattern. Next, film thickness 150 nm
Of Si ₃ N ₄ is deposited by the CVD method and etched by the dry etching method to form Si on the side wall of the bit line 42.
₃ N ₄ sidewall spacers 44 are formed to insulate the bit lines 42. Insulating film 4 on top of polycrystalline silicon 32
1 is opened by using the photolithography method and the dry etching method.

Next, as shown in FIG. 5, a silicon oxide film type insulating film 51 such as BPSG (boron phosphosilicate glass) is deposited and flattened. The insulating film 51 needs to have a film thickness sufficient to flatten the substrate surface.
In this embodiment, the insulating film 51 has a thickness of 500 nm.
A method of depositing SiO ₂ on the surface of the substrate by the CVD method and flattening it by the etch back method may be used. Next,
A photolithography method and a dry etching method are used to open a hole, and a phosphorus-doped amorphous silicon film for filling is formed by CVD.
Method, a heat treatment is performed, and a dry etching method is used to etch back to fill the contact holes to form polycrystalline silicon 52.

Next, as shown in FIG. 6, a 100 nm TiN film 61 is formed as a diffusion preventing conductive layer. Further, a platinum lower electrode 62 is formed. In this example, a target in which a titanium metal plate was placed on platinum was used, and a film containing platinum as the main component containing 5 mol% of titanium was deposited to a thickness of about 100 nm by the DC sputtering method. 50 nm TiN is deposited by the DC sputtering method and TiN is deposited by the dry etching method using SF ₆ with the photoresist as a mask.
Then, the platinum lower electrode 62 is patterned by the sputter etching method using this TiN as a mask. After removing TiN used for the mask by the wet etching method, the ferroelectric thin film 63 is formed. In this embodiment, a thickness of about 100 n is obtained by the sol-gel method described above.
m lead titanate zirconate (Pb (Zr _0.5 Ti _0.5 ) O
₃ ) After forming a thin film, in an oxygen atmosphere at 650 ℃, 12
Crystallization was performed by performing 0 second heat treatment (Rapid Thermal Annealing). A plate electrode is deposited and patterned to complete the memory cell capacitor. However, in FIG. 6, the plate electrode is not shown because the drawing is complicated. The dielectric characteristics of this capacitor were measured by the same method as that shown in FIG. When a sample in which the area of the capacitor was changed to 0.2 to 100 μm ² was examined, it was possible to feed power from the substrate, and a good hysteresis curve was obtained.

Lead zirconate titanate (Pb (Zr _0.5 T
As a method of forming the i _0.5 ) O ₃ ) thin film, a high-frequency magnetron sputtering method was used, and the same characteristics were obtained even when formed under the conditions shown in Table 2. Therefore, there is no fear of oxidizing the diffusion prevention film either by the method of crystallizing the amorphous ferroelectric by post annealing or by the method of directly forming the crystallized film. Therefore, the reactive vapor deposition method or the CVD method may be used.

Table 2 Sputtering conditions High frequency power 200 W Sputtering gas Argon (90%)-Oxygen (10%) Gas pressure 10 Pa Substrate temperature 650 ° C. In the above example, lead zirconate titanate (Pb (Ti _x Zr _1-x ) O ₃ and x = 0.5) are shown as an example, but lead zirconate titanate and barium strontium titanate ((Ba _x Sr _1-x )) having different compositions are shown.
A memory cell could be similarly formed by using TiO ₃ (x = 0 to 1)), lead barium zirconate titanate, and a bismuth-based layered ferroelectric. Also, as a diffusion preventing conductive layer, Ti is used.
Although the N film was used, the same effect was obtained by using a Ti film or a Ta film instead of this.

[0032]

As described above, according to the present invention,
Even if the platinum electrode was thin, the diffusion preventing conductive layer was not oxidized, and the memory cell could be formed. for that reason,
It has been possible to obtain a semiconductor device having a fine memory cell suitable for high integration, which suppresses an increase in contact resistance and a series parasitic capacitance. Moreover, such a semiconductor device could be easily manufactured. Furthermore, a platinum thin film capable of suppressing the diffusion of oxygen could be obtained. Further, such a platinum thin film could be easily manufactured.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the present invention.

FIG. 2 is a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a manufacturing process diagram for a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a manufacturing process diagram for a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

21 ... p-type semiconductor substrate 22 ... element isolation insulating film 23 ... gate oxide film 24 ... word line 25, 26 ... n-type impurity diffusion layer 27 ... interlayer insulating film 28, 43 ... SiO ₂ 29 ... Si ₃ N ₄ 31, 32, 52 ... Polycrystalline silicon 41, 51 ... Insulating film 42 ... Bit line 44 ... Side wall spacer 61 ... TiN film 62 ... Platinum lower electrode 63 ... Ferroelectric thin film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshihisa Fujisaki 1-280, Higashi Koikekubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (22)

[Claims] 1. A substrate, a lower conductive film containing platinum as a main component provided on the substrate, a ferroelectric thin film provided on the lower conductive film, and a ferroelectric thin film provided on the ferroelectric thin film. An upper conductive film, the upper and lower conductive films and the ferroelectric thin film constitute a ferroelectric capacitor, and the lower conductive film,
A semiconductor device, wherein an element forming a conductive nitride is added, and part or all of the element is nitrided. 2. A semiconductor device according to claim 1, wherein a MOS transistor is arranged on the substrate, and the lower conductive film is electrically connected to a source region or a drain region of the MOS transistor. 3. The semiconductor device according to claim 1, wherein a diffusion preventing conductive layer is disposed between the substrate and the lower conductive film. 4. The semiconductor device according to claim 3, wherein the diffusion preventing conductive layer is made of at least one substance selected from the group consisting of Ti, Ta and TiN. 5. The element forming the conductive nitride is at least one element selected from the group consisting of titanium, tantalum, zirconium, niobium, vanadium and tungsten. 4. The semiconductor device according to any one of 4 above. 6. The semiconductor device according to claim 1, wherein the lower conductive film is added with the element in an amount not less than the solid solution limit of platinum of the element. . 7. The semiconductor device according to claim 1, wherein the nitrided element is segregated at a crystal grain boundary of the lower conductive film. 8. The semiconductor device according to claim 1, wherein the ferroelectric thin film is made of an oxide ferroelectric material. 9. The semiconductor device according to claim 8, wherein the oxide ferroelectric substance is lead zirconate titanate. 10. The semiconductor device according to claim 8, wherein the oxide ferroelectric substance is barium lead zirconate titanate. 11. The semiconductor device according to claim 8, wherein the oxide ferroelectric substance is barium strontium titanate. 12. The semiconductor device according to claim 8, wherein the oxide ferroelectric substance is a bismuth-based layered ferroelectric substance. 13. A lower portion containing platinum as a main component and part or all of the above elements nitrided by sputtering or vapor deposition of platinum and an element forming a conductive nitride in an atmosphere containing nitrogen. The method includes the steps of forming a conductive film on a substrate, forming a ferroelectric thin film on the lower conductive film, and forming an upper conductive film on the ferroelectric thin film. And a method of manufacturing a semiconductor device, wherein the lower conductive film and the ferroelectric thin film form a ferroelectric capacitor. 14. Before the step of forming the lower conductive film,
14. The method of manufacturing a semiconductor device according to claim 13, further comprising the step of forming a diffusion preventing conductive layer on the substrate, wherein the lower conductive film is formed on the diffusion preventing conductive layer. Method. 15. At least one of the MOS transistors is formed on the substrate before the step of forming the diffusion preventing conductive layer.
A step of forming a portion, wherein the lower conductive film is
15. The method of manufacturing a semiconductor device according to claim 13, wherein the semiconductor device is electrically connected to a source region or a drain region of the transistor. 16. A substrate and a platinum thin film provided on the substrate, wherein the platinum thin film is doped with an element forming a conductive nitride, and part or all of the element is nitrided. A platinum thin film characterized in that. 17. The element forming the conductive nitride is at least one element selected from the group consisting of titanium, tantalum, zirconium, niobium, vanadium and tungsten. Thin platinum film. 18. The platinum thin film according to claim 16, wherein the platinum thin film is added with the element in an amount not less than the solid solubility limit of the element in platinum. 19. The platinum thin film according to claim 16, wherein the nitrided element is segregated at a crystal grain boundary of the platinum thin film. 20. Sputtering or vapor depositing platinum and an element forming a conductive nitride in an atmosphere containing nitrogen to form a platinum thin film containing the above element, which is partially or wholly nitrided, on a substrate. A method for producing a platinum thin film, comprising: 21. The platinum thin film is formed on the substrate by sputtering, and the atmosphere containing nitrogen is an atmosphere containing 10 to 90 mol% of nitrogen in an inert gas. 21. The method for producing a platinum thin film according to 20. 22. The platinum thin film is formed on the substrate by vapor deposition, and the atmosphere containing nitrogen is 0.01-10.
21. The method for producing a platinum thin film according to claim 20, wherein the nitrogen gas atmosphere has a pressure in the range of 0 mTorr.