JPH05890B2 - - Google Patents

Info

Publication number
JPH05890B2
JPH05890B2 JP57127539A JP12753982A JPH05890B2 JP H05890 B2 JPH05890 B2 JP H05890B2 JP 57127539 A JP57127539 A JP 57127539A JP 12753982 A JP12753982 A JP 12753982A JP H05890 B2 JPH05890 B2 JP H05890B2
Authority
JP
Japan
Prior art keywords
circuit
level
signal bus
logic
cmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57127539A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5919434A (ja
Inventor
Tsuneo Ito
Makio Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57127539A priority Critical patent/JPS5919434A/ja
Publication of JPS5919434A publication Critical patent/JPS5919434A/ja
Publication of JPH05890B2 publication Critical patent/JPH05890B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
JP57127539A 1982-07-23 1982-07-23 レベル保証回路 Granted JPS5919434A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57127539A JPS5919434A (ja) 1982-07-23 1982-07-23 レベル保証回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57127539A JPS5919434A (ja) 1982-07-23 1982-07-23 レベル保証回路

Publications (2)

Publication Number Publication Date
JPS5919434A JPS5919434A (ja) 1984-01-31
JPH05890B2 true JPH05890B2 (enrdf_load_html_response) 1993-01-07

Family

ID=14962511

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57127539A Granted JPS5919434A (ja) 1982-07-23 1982-07-23 レベル保証回路

Country Status (1)

Country Link
JP (1) JPS5919434A (enrdf_load_html_response)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63128813A (ja) * 1986-11-18 1988-06-01 Nec Corp 半導体集積回路装置
JPS63131614A (ja) * 1986-11-20 1988-06-03 Nec Corp 半導体集積回路装置
JP2568698B2 (ja) * 1989-07-13 1997-01-08 富士通株式会社 バス制御方式

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55141826A (en) * 1979-04-24 1980-11-06 Seiko Epson Corp Input circuit for integrated circuit
JPS56172126U (enrdf_load_html_response) * 1980-05-23 1981-12-19
JPS5750032A (en) * 1980-09-09 1982-03-24 Matsushita Electric Ind Co Ltd Integrated circuit

Also Published As

Publication number Publication date
JPS5919434A (ja) 1984-01-31

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