JPH0586657B2 - - Google Patents

Info

Publication number
JPH0586657B2
JPH0586657B2 JP58240206A JP24020683A JPH0586657B2 JP H0586657 B2 JPH0586657 B2 JP H0586657B2 JP 58240206 A JP58240206 A JP 58240206A JP 24020683 A JP24020683 A JP 24020683A JP H0586657 B2 JPH0586657 B2 JP H0586657B2
Authority
JP
Japan
Prior art keywords
insulating film
bumps
film
conductive film
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58240206A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60132346A (ja
Inventor
Yoshifumi Kitayama
Shuichi Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58240206A priority Critical patent/JPS60132346A/ja
Publication of JPS60132346A publication Critical patent/JPS60132346A/ja
Publication of JPH0586657B2 publication Critical patent/JPH0586657B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP58240206A 1983-12-20 1983-12-20 転写用バンプ製造方法 Granted JPS60132346A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58240206A JPS60132346A (ja) 1983-12-20 1983-12-20 転写用バンプ製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58240206A JPS60132346A (ja) 1983-12-20 1983-12-20 転写用バンプ製造方法

Publications (2)

Publication Number Publication Date
JPS60132346A JPS60132346A (ja) 1985-07-15
JPH0586657B2 true JPH0586657B2 (enrdf_load_stackoverflow) 1993-12-13

Family

ID=17056027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58240206A Granted JPS60132346A (ja) 1983-12-20 1983-12-20 転写用バンプ製造方法

Country Status (1)

Country Link
JP (1) JPS60132346A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS60132346A (ja) 1985-07-15

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term