JPH0582978B2 - - Google Patents

Info

Publication number
JPH0582978B2
JPH0582978B2 JP61091000A JP9100086A JPH0582978B2 JP H0582978 B2 JPH0582978 B2 JP H0582978B2 JP 61091000 A JP61091000 A JP 61091000A JP 9100086 A JP9100086 A JP 9100086A JP H0582978 B2 JPH0582978 B2 JP H0582978B2
Authority
JP
Japan
Prior art keywords
conductor
semiconductor element
pin
organic resin
resin substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61091000A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62247555A (ja
Inventor
Koichi Izumi
Hironori Takenaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP9100086A priority Critical patent/JPS62247555A/ja
Publication of JPS62247555A publication Critical patent/JPS62247555A/ja
Publication of JPH0582978B2 publication Critical patent/JPH0582978B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP9100086A 1986-04-18 1986-04-18 半導体素子搭載ピングリットアレイパッケージ基板の製造方法 Granted JPS62247555A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9100086A JPS62247555A (ja) 1986-04-18 1986-04-18 半導体素子搭載ピングリットアレイパッケージ基板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9100086A JPS62247555A (ja) 1986-04-18 1986-04-18 半導体素子搭載ピングリットアレイパッケージ基板の製造方法

Publications (2)

Publication Number Publication Date
JPS62247555A JPS62247555A (ja) 1987-10-28
JPH0582978B2 true JPH0582978B2 (en:Method) 1993-11-24

Family

ID=14014231

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9100086A Granted JPS62247555A (ja) 1986-04-18 1986-04-18 半導体素子搭載ピングリットアレイパッケージ基板の製造方法

Country Status (1)

Country Link
JP (1) JPS62247555A (en:Method)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03123065A (ja) * 1989-10-04 1991-05-24 Nec Kyushu Ltd 半導体装置用パッケージ
JP4646417B2 (ja) * 2001-02-21 2011-03-09 京セラ株式会社 セラミック回路基板
JP5175489B2 (ja) * 2007-04-27 2013-04-03 新光電気工業株式会社 半導体パッケージの製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1045977A (en) * 1973-05-17 1979-01-09 Arthur D. Little Biodegradable, implantable drug delivery device, and process for preparing and using the same
JPS5670650U (en:Method) * 1979-10-31 1981-06-11
JPS5982757A (ja) * 1982-11-04 1984-05-12 Toshiba Corp 半導体用ステムおよびその製造方法
JPS6113938U (ja) * 1984-06-30 1986-01-27 イビデン株式会社 プラグインパツケ−ジ基板

Also Published As

Publication number Publication date
JPS62247555A (ja) 1987-10-28

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