JPH0582673A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPH0582673A
JPH0582673A JP24223791A JP24223791A JPH0582673A JP H0582673 A JPH0582673 A JP H0582673A JP 24223791 A JP24223791 A JP 24223791A JP 24223791 A JP24223791 A JP 24223791A JP H0582673 A JPH0582673 A JP H0582673A
Authority
JP
Japan
Prior art keywords
resin
terminal land
frame
substrate
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24223791A
Other languages
Japanese (ja)
Other versions
JP3013544B2 (en
Inventor
Naoharu Senba
直治 仙波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3242237A priority Critical patent/JP3013544B2/en
Publication of JPH0582673A publication Critical patent/JPH0582673A/en
Application granted granted Critical
Publication of JP3013544B2 publication Critical patent/JP3013544B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To effectively use a space and miniaturize a device by a method wherein a substrate terminal land plane of the substrate is provided higher than a mounting plate of a passive element, an active element, or the like so that sealing resin can be prevented from flowing out. CONSTITUTION:A terminal land 23 is provided on a substrate 22 in which a circuit pattern is formed. The terminal land 23 has a flowing-out prevention structure at resin-sealing resin 24. Also, the terminal land 23 is connected to an external lead 21 by solder, conductive adhesive or the like. Namely, the terminal land 23 plane of the substrate 22 is provided higher than the mounting plate of passive elements, active elements 26 or the like, and a resin frame or a printing frame for preventing the sealing resin from flowing out is not provided and instead of that such a structure as the flowing-out prevention frame of the terminal land 23 is provide. Thus, a space for providing the resin frame or the printing frame within the terminal land 23 can also effectively be used as a space constituting a hybrid integrated circuit device, so that it can be effective in miniaturizing the device or the like.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は混成集積回路装置に関す
るものである。
FIELD OF THE INVENTION The present invention relates to a hybrid integrated circuit device.

【0002】[0002]

【従来の技術】有機基板を用いてなる従来技術の混成集
積回路装置を図5に示す。図5において(A)は上面
図、(B)は(A)のE−E断面図である。図5に示す
ように回路パターン13を有する基板2上に接着剤を使
用し、受動素子あるいは能動素子6が搭載され、金属細
線5等を用いて端子配線3に回路接続を行い、樹脂4に
より樹脂封止している。但し、樹脂4の流出防止のた
め、回路基板上2に流れ止め用の樹脂枠(巾1.0mm
×高さ1.0mm etc.)又は印刷枠(巾0.5m
m×高さ0.2mm etc.)10を設けている構造
となっている。また両面搭載構造の場合は図6に示すよ
うに両面に回路パターン13を有する基板2の両面パタ
ーンに接着剤を使用し、受動素子あるいは能動素子6が
搭載され金属細線5等を用いて回路接続を行い、樹脂4
により樹脂封止している。本構造に於いても樹脂4の流
出防止のため、回路基板2の両面に流れ止め用の樹脂枠
(巾1.0mm×高さ1.0mm etc.)又は印刷
枠(巾0.5mm×高さ0.2mm etc.)10を
設けた構造となっている。尚、図6において上面図
(A)のF−F断面が断面図(B)である。図5及び図
6に示すように樹脂枠10の位置は外部リード1の端子
ランド3のいずれも内側に配置されている。
2. Description of the Related Art A prior art hybrid integrated circuit device using an organic substrate is shown in FIG. In FIG. 5, (A) is a top view and (B) is a sectional view taken along line EE of (A). As shown in FIG. 5, an adhesive is used on a substrate 2 having a circuit pattern 13, a passive element or an active element 6 is mounted, and a circuit connection is made to a terminal wiring 3 using a thin metal wire 5 or the like, and a resin 4 is used. It is resin-sealed. However, in order to prevent the resin 4 from flowing out, a resin frame (width 1.0 mm) for preventing flow is provided on the circuit board 2.
× Height 1.0 mm etc. ) Or printing frame (width 0.5m
m × height 0.2 mm etc. ) 10 is provided. Further, in the case of the double-sided mounting structure, as shown in FIG. 6, an adhesive is used for the double-sided pattern of the substrate 2 having the circuit patterns 13 on both sides, and the passive element or the active element 6 is mounted and the circuit connection is made by using the thin metal wire 5 or the like. And resin 4
Is resin-sealed. Also in this structure, in order to prevent the resin 4 from flowing out, a resin frame (width 1.0 mm x height 1.0 mm etc.) or a printing frame (width 0.5 mm x height) is provided on both sides of the circuit board 2 for preventing flow. 0.2 mm etc.) 10 is provided. In addition, in FIG. 6, the FF cross section of the top view (A) is a sectional view (B). As shown in FIGS. 5 and 6, the resin frame 10 is located inside each of the terminal lands 3 of the external leads 1.

【0003】[0003]

【発明が解決しようとする課題】この従来の混成集積回
路装置は、外部リード取り付け用端子ランドの内側に封
止樹脂流出防止用の樹脂枠あるいは印刷枠を設けている
構造となっているため、樹脂枠あるいは印刷枠のスペー
スが必要である。従って混成集積回路を構成する有効面
積が減少する。その結果、高機能化、高集積化、小型化
等が非常に困難であるという問題点があった。図5及び
図6に於ける有効面積及び非有効面積(樹脂枠又は印刷
枠に要する面積)は次のようになる。図5では有効面積
はa×hであり、非有効面積は(a+2b)×(h+2
d)からa×bを引いた面積となる。又、図6ではこの
非有効面積は両面にあるから図5の2倍となる。
This conventional hybrid integrated circuit device has a structure in which a resin frame or a printing frame for preventing the outflow of the sealing resin is provided inside the external lead mounting terminal land. Space for resin frame or printing frame is required. Therefore, the effective area constituting the hybrid integrated circuit is reduced. As a result, there has been a problem that it is very difficult to achieve high functionality, high integration, and miniaturization. The effective area and the non-effective area (the area required for the resin frame or the printing frame) in FIGS. 5 and 6 are as follows. In FIG. 5, the effective area is a × h, and the ineffective area is (a + 2b) × (h + 2
It is the area obtained by subtracting a × b from d). Further, in FIG. 6, since this non-effective area is on both sides, it is twice as large as that in FIG.

【0004】[0004]

【課題を解決するための手段】本発明の混成集積回路装
置は樹脂流出防止用の樹脂枠あるいは印刷枠のかわりに
外部リード付用の端子ランドを使用する構造となってい
る。従って、外部リード付用端子ランドの内側には樹脂
枠あるいは印刷枠のない構造となっている。
The hybrid integrated circuit device of the present invention has a structure in which a terminal land for attaching an external lead is used in place of a resin frame or a printing frame for preventing resin outflow. Therefore, there is no resin frame or printing frame inside the terminal land for external leads.

【0005】[0005]

【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の第1の実施例を示す、平面図(A)
と断面図(B)である。回路パターン(図示省略)が形
成された基板22上に端子ランド23が設けられてい
る。この端子ランド23は、樹脂24の樹脂封止時の流
れ防止構造となっている。端子ランド23には半田又は
導電接着剤等により外部リード21を接続している。回
路パターン上には受動素子あるいは能動素子26等を接
着剤により固着し、金属細線25等により回路接続を実
施する。その後、樹脂24により樹脂封止する。
The present invention will be described below with reference to the drawings. FIG. 1 is a plan view (A) showing a first embodiment of the present invention.
It is a sectional view (B). Terminal lands 23 are provided on a substrate 22 on which a circuit pattern (not shown) is formed. The terminal land 23 has a flow prevention structure when the resin 24 is sealed with the resin. The external leads 21 are connected to the terminal lands 23 by solder, conductive adhesive, or the like. A passive element or an active element 26 or the like is fixed on the circuit pattern with an adhesive, and the metal thin wire 25 or the like is used for circuit connection. After that, resin sealing is performed with the resin 24.

【0006】図2は本発明の第2の実施例を示す平面図
(A)および断面図(B)である。両面に回路パターン
(図示省略)が形成された基板22の両面に端子ランド
23が設けられている。この端子ランド23は樹脂24
の樹脂封止時の流れ防止構造となっている。端子ランド
23には半田又は導電接着剤等により外部リード21を
接続している。両面の回路パターン上には受動素子ある
いは能動素子26等を接着剤により固着し、金属細線2
5等により回路接続を実施する。その後、樹脂24によ
り樹脂封止する。
FIG. 2 is a plan view (A) and a sectional view (B) showing a second embodiment of the present invention. Terminal lands 23 are provided on both surfaces of a substrate 22 having circuit patterns (not shown) formed on both surfaces. This terminal land 23 is made of resin 24
It has a flow prevention structure when the resin is sealed. The external leads 21 are connected to the terminal lands 23 by solder, conductive adhesive, or the like. A passive element or an active element 26 or the like is fixed on the circuit patterns on both sides with an adhesive, and the metal fine wire 2
5. Connect the circuit by 5 etc. After that, resin sealing is performed with the resin 24.

【0007】図3は本発明の第3の実施例を示す平面図
(A)と断面図(B)である。
FIG. 3 is a plan view (A) and a sectional view (B) showing a third embodiment of the present invention.

【0008】回路パターン(図示省略)が形成された基
板32にスルーホールメッキ法(L/Fスルーホール
8)を用いて外部リード31を接続したものでありスル
ーホール7自体が端子ランド33と兼ねている構造とな
っている。またこのスルーホールランド9が樹脂24の
流出防止の役目をする構造となる。回路パターン上には
受動素子あるいは能動素子26等を接着剤により固着
し、金属細線25等により回路接続を実施する。その
後、樹脂24により樹脂封止する。
An external lead 31 is connected to a substrate 32 having a circuit pattern (not shown) formed by using a through hole plating method (L / F through hole 8). The through hole 7 itself also serves as the terminal land 33. It has a structure. Further, the through hole land 9 serves as a structure for preventing the resin 24 from flowing out. A passive element or active element 26 or the like is fixed on the circuit pattern with an adhesive, and a circuit is connected by a metal thin wire 25 or the like. After that, resin sealing is performed with the resin 24.

【0009】図4は本発明の第4の実施例を示す平面図
(A)と断面図(B)である。
FIG. 4 is a plan view (A) and a sectional view (B) showing a fourth embodiment of the present invention.

【0010】回路パターン(図示省略)が両面に形成さ
れた基板32にスルーホールメッキ法(L/Fスルーホ
ール8)を用いて外部リード31を接続したものであ
り、スルーホール7自体が両面共に端子ランド33を兼
ねている構造となっている。またこのスルーホールラン
ド9が樹脂4の流出防止の役目をする構造となる。両面
の回路パターン上には受動素子あるいは能動素子26を
接着剤により固着し、金属細線25等により回路接続す
る。その後、樹脂24により樹脂封止する。以上説明し
たように第1〜第4の実施例のいずれの構造においても
封止樹脂の流出防止のための樹脂枠又は印刷枠は不要で
あり、替りに端子ランドを流出防止枠としている。
External leads 31 are connected to a substrate 32 having circuit patterns (not shown) formed on both sides by using a through hole plating method (L / F through holes 8), and the through holes 7 themselves are formed on both sides. The structure also serves as the terminal land 33. Further, the through hole land 9 serves as a structure for preventing the resin 4 from flowing out. Passive elements or active elements 26 are fixed on the circuit patterns on both sides with an adhesive, and the circuits are connected by metal thin wires 25 or the like. After that, resin sealing is performed with the resin 24. As described above, in any of the structures of the first to fourth embodiments, the resin frame or the printing frame for preventing the outflow of the sealing resin is unnecessary, and the terminal land is used as the outflow prevention frame instead.

【0011】[0011]

【発明の効果】以上説明したように本発明は封止樹脂流
出防止のための樹脂枠又は印刷枠を設けずに替りに端子
ランドを流出防止枠になるような構造としたことにより
端子ランド内の樹脂枠又は印刷枠を設けるべきスペース
も混成集積回路装置を構成するスペースとして有効活用
できる。従って混成集積回路装置の高集積化、高機能
化、小型化等に有効である。また、構成要素(樹脂、枠
材料、製造工程等)の減少が計れるため、品質の向上が
期待できる。
As described above, according to the present invention, the resin land or the printing frame for preventing the outflow of the sealing resin is not provided, but instead the terminal land is used as the outflow prevention frame. The space where the resin frame or the printing frame is to be provided can also be effectively used as a space for forming the hybrid integrated circuit device. Therefore, it is effective for high integration, high functionality, miniaturization, etc. of the hybrid integrated circuit device. Further, since the number of constituent elements (resin, frame material, manufacturing process, etc.) can be reduced, quality improvement can be expected.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を示す平面図及び断面
図。
FIG. 1 is a plan view and a cross-sectional view showing a first embodiment of the present invention.

【図2】本発明の第2の実施例を示す平面図及び断面
図。
2A and 2B are a plan view and a sectional view showing a second embodiment of the present invention.

【図3】本発明の第3の実施例を示す平面図及び断面
図。
FIG. 3 is a plan view and a sectional view showing a third embodiment of the present invention.

【図4】本発明の第4の実施例を示す平面図及び断面
図。
FIG. 4 is a plan view and a sectional view showing a fourth embodiment of the present invention.

【図5】従来技術を示す平面図及び断面図。FIG. 5 is a plan view and a cross-sectional view showing a conventional technique.

【図6】他の従来技術を示す平面図及び断面図。FIG. 6 is a plan view and a cross-sectional view showing another conventional technique.

【符号の説明】[Explanation of symbols]

1,21,31 外部リード 2,22,32 基板 3,23,33 端子ランド 4,24 樹脂 5,25 金属細線 6,26 受動,能動素子 7 スルーホール 8 L/Fスルーホール 9 スルーホールランド 10 樹脂枠又は印刷枠 a 有効寸法 b 非有効寸法 d 非有効寸法 h 有効寸法 1,2,31 External lead 2,22,32 Substrate 3,23,33 Terminal land 4,24 Resin 5,25 Metal fine wire 6,26 Passive and active element 7 Through hole 8 L / F through hole 9 Through hole land 10 Resin frame or printing frame a Effective dimension b Ineffective dimension d Ineffective dimension h Effective dimension

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 有機基板上に受動素子、能動素子等を搭
載し、封止樹脂にて封止し、外部リードを基板端子ラン
ドに接続してなる混成集積回路装置において、前記基板
の基板端子ランド面を受動素子、能動素子等の搭載面よ
り高くしこれにより封止樹脂の流れ出しを防ぐ構造とし
たことを特徴とする混成集積回路装置。
1. A hybrid integrated circuit device in which a passive element, an active element, etc. are mounted on an organic substrate, sealed with a sealing resin, and external leads are connected to a substrate terminal land. A hybrid integrated circuit device having a structure in which a land surface is made higher than a mounting surface for passive elements, active elements, etc., thereby preventing the sealing resin from flowing out.
JP3242237A 1991-09-24 1991-09-24 Hybrid integrated circuit device Expired - Lifetime JP3013544B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3242237A JP3013544B2 (en) 1991-09-24 1991-09-24 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3242237A JP3013544B2 (en) 1991-09-24 1991-09-24 Hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JPH0582673A true JPH0582673A (en) 1993-04-02
JP3013544B2 JP3013544B2 (en) 2000-02-28

Family

ID=17086280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3242237A Expired - Lifetime JP3013544B2 (en) 1991-09-24 1991-09-24 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JP3013544B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023228A (en) * 2001-07-05 2003-01-24 Sanyo:Kk Component mounting substrate having protrusions and recesses on the surface and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023228A (en) * 2001-07-05 2003-01-24 Sanyo:Kk Component mounting substrate having protrusions and recesses on the surface and its manufacturing method

Also Published As

Publication number Publication date
JP3013544B2 (en) 2000-02-28

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Effective date: 19991116