JPH0575182B2 - - Google Patents

Info

Publication number
JPH0575182B2
JPH0575182B2 JP62192860A JP19286087A JPH0575182B2 JP H0575182 B2 JPH0575182 B2 JP H0575182B2 JP 62192860 A JP62192860 A JP 62192860A JP 19286087 A JP19286087 A JP 19286087A JP H0575182 B2 JPH0575182 B2 JP H0575182B2
Authority
JP
Japan
Prior art keywords
lsi
wiring
wiring board
chip
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62192860A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6437046A (en
Inventor
Tatsuo Inoe
Akihiro Dotani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP62192860A priority Critical patent/JPS6437046A/ja
Publication of JPS6437046A publication Critical patent/JPS6437046A/ja
Publication of JPH0575182B2 publication Critical patent/JPH0575182B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Non-Insulated Conductors (AREA)
  • Multi-Conductor Connections (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
JP62192860A 1987-07-31 1987-07-31 Multi-chip package Granted JPS6437046A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62192860A JPS6437046A (en) 1987-07-31 1987-07-31 Multi-chip package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62192860A JPS6437046A (en) 1987-07-31 1987-07-31 Multi-chip package

Publications (2)

Publication Number Publication Date
JPS6437046A JPS6437046A (en) 1989-02-07
JPH0575182B2 true JPH0575182B2 (enrdf_load_stackoverflow) 1993-10-20

Family

ID=16298175

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62192860A Granted JPS6437046A (en) 1987-07-31 1987-07-31 Multi-chip package

Country Status (1)

Country Link
JP (1) JPS6437046A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105118811A (zh) * 2015-07-27 2015-12-02 电子科技大学 一种采用均热板及微通道对多热源器件散热的均温装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012174856A (ja) * 2011-02-21 2012-09-10 Hitachi Cable Ltd ヒートシンク及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105118811A (zh) * 2015-07-27 2015-12-02 电子科技大学 一种采用均热板及微通道对多热源器件散热的均温装置

Also Published As

Publication number Publication date
JPS6437046A (en) 1989-02-07

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees