JPH0573338B2 - - Google Patents

Info

Publication number
JPH0573338B2
JPH0573338B2 JP63032005A JP3200588A JPH0573338B2 JP H0573338 B2 JPH0573338 B2 JP H0573338B2 JP 63032005 A JP63032005 A JP 63032005A JP 3200588 A JP3200588 A JP 3200588A JP H0573338 B2 JPH0573338 B2 JP H0573338B2
Authority
JP
Japan
Prior art keywords
etching
layer
polyimide
photoresist
metallurgy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63032005A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63304644A (ja
Inventor
Eva Hoerner
Reinhold Muehl
Hans-Joachim Trumpp
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS63304644A publication Critical patent/JPS63304644A/ja
Publication of JPH0573338B2 publication Critical patent/JPH0573338B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10P50/287—
    • H10W20/082—

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP63032005A 1987-04-16 1988-02-16 ヴアイア・ホール形成方法 Granted JPS63304644A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP87105700A EP0286708B1 (de) 1987-04-16 1987-04-16 Verfahren zur Herstellung von Kontaktöffnungen in einer Doppellagenisolation
EP87105700.6 1987-04-16

Publications (2)

Publication Number Publication Date
JPS63304644A JPS63304644A (ja) 1988-12-12
JPH0573338B2 true JPH0573338B2 (enExample) 1993-10-14

Family

ID=8196930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63032005A Granted JPS63304644A (ja) 1987-04-16 1988-02-16 ヴアイア・ホール形成方法

Country Status (4)

Country Link
US (1) US4816115A (enExample)
EP (1) EP0286708B1 (enExample)
JP (1) JPS63304644A (enExample)
DE (1) DE3776325D1 (enExample)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4869777A (en) * 1988-12-16 1989-09-26 Ibm Corporation Method for selectively etching the materials of a composite of two materials
US5010039A (en) * 1989-05-15 1991-04-23 Ku San Mei Method of forming contacts to a semiconductor device
US5258264A (en) * 1989-07-06 1993-11-02 International Business Machines Corporation Process of forming a dual overhang collimated lift-off stencil with subsequent metal deposition
US5153303A (en) * 1990-01-19 1992-10-06 Ciba-Geigy Corporation Polyimides prepared from disubstituted aromatic tetracarboxylic acid dianhydrides
US5034091A (en) * 1990-04-27 1991-07-23 Hughes Aircraft Company Method of forming an electrical via structure
US5022958A (en) * 1990-06-27 1991-06-11 At&T Bell Laboratories Method of etching for integrated circuits with planarized dielectric
US5266446A (en) * 1990-11-15 1993-11-30 International Business Machines Corporation Method of making a multilayer thin film structure
JPH0760821B2 (ja) * 1991-05-17 1995-06-28 インターナショナル・ビジネス・マシーンズ・コーポレイション ポリマー基材の状態調整方法
WO1993007629A1 (en) * 1991-10-04 1993-04-15 Motorola, Inc. Integrated deposited vertical resistor in a sequential multilayer substrate
US5223084A (en) * 1991-11-25 1993-06-29 Hewlett-Packard Company Simultaneous dielectric planarization and contact hole etching
JPH05243388A (ja) * 1991-11-29 1993-09-21 Nec Corp 半導体装置の製造方法
JPH06188229A (ja) * 1992-12-16 1994-07-08 Tokyo Electron Yamanashi Kk エッチングの後処理方法
TW290717B (en) * 1994-10-28 1996-11-11 Advanced Micro Devices Inc Method to prevent formation of defects during multilayer interconnect processing
US5883001A (en) * 1994-11-07 1999-03-16 Macronix International Co., Ltd. Integrated circuit passivation process and structure
JP3360461B2 (ja) * 1995-01-31 2002-12-24 ソニー株式会社 メタル成膜工程の前処理方法
KR0179838B1 (ko) * 1995-09-02 1999-04-15 문정환 반도체 소자의 절연막 구조 및 절연막 평탄화 방법
US5661083A (en) * 1996-01-30 1997-08-26 Integrated Device Technology, Inc. Method for via formation with reduced contact resistance
TW385523B (en) * 1996-12-14 2000-03-21 United Microelectronics Corp Method for making contact via with a formed component on semiconductor substrate
US6074569A (en) * 1997-12-09 2000-06-13 Hughes Electronics Corporation Stripping method for photoresist used as mask in Ch4 /H2 based reactive ion etching (RIE) of compound semiconductors
US6245492B1 (en) 1998-08-13 2001-06-12 International Business Machines Corporation Photoresist system and process for aerial image enhancement
US6175087B1 (en) 1998-12-02 2001-01-16 International Business Machines Corporation Composite laminate circuit structure and method of forming the same
US6461969B1 (en) * 1999-11-22 2002-10-08 Chartered Semiconductor Manufacturing Ltd. Multiple-step plasma etching process for silicon nitride
JP2002353195A (ja) * 2001-05-23 2002-12-06 Sony Corp 半導体装置の製造方法
DE10127580B4 (de) * 2001-05-29 2006-04-27 Infineon Technologies Ag In-situ-Maskentechnik zur Produktion von III-V Halbleiter-Bauelementen
US7344825B2 (en) * 2002-04-04 2008-03-18 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating semiconductor device, and developing apparatus using the method
US7875419B2 (en) * 2002-10-29 2011-01-25 Semiconductor Energy Laboratory Co., Ltd. Method for removing resist pattern and method for manufacturing semiconductor device
US7115488B2 (en) * 2003-08-29 2006-10-03 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
KR100506943B1 (ko) * 2003-09-09 2005-08-05 삼성전자주식회사 식각정지막으로 연결홀의 저측면에 경사를 갖는 반도체소자의 제조 방법들
CN103928396A (zh) * 2014-04-08 2014-07-16 上海华力微电子有限公司 扩大沟槽开口的方法
RU2645920C2 (ru) * 2016-06-24 2018-02-28 федеральное государственное бюджетное образовательное учреждение высшего образования "Воронежский государственный университет" (ФГБОУ ВО "ВГУ") Способ формирования контактных окон в слое защитного основания высоковольтного прибора
TWI862734B (zh) 2019-11-19 2024-11-21 德商馬克專利公司 無光酸產生劑(pag)之正型化學增幅光阻組合物及其使用方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2537779B1 (fr) * 1982-12-10 1986-03-14 Commissariat Energie Atomique Procede de positionnement d'un trou de contact electrique entre deux lignes d'interconnexion d'un circuit integre
US4532002A (en) * 1984-04-10 1985-07-30 Rca Corporation Multilayer planarizing structure for lift-off technique
US4631248A (en) * 1985-06-21 1986-12-23 Lsi Logic Corporation Method for forming an electrical contact in an integrated circuit
WO1987002179A1 (en) * 1985-09-27 1987-04-09 Burroughs Corporation Method of fabricating a tapered via hole in polyimide
DE3581941D1 (de) * 1985-12-21 1991-04-04 Ibm Deutschland Verfahren zum herstellen eines photolackmusters.
US4698128A (en) * 1986-11-17 1987-10-06 Motorola, Inc. Sloped contact etch process

Also Published As

Publication number Publication date
EP0286708B1 (de) 1992-01-22
US4816115A (en) 1989-03-28
EP0286708A1 (de) 1988-10-19
DE3776325D1 (de) 1992-03-05
JPS63304644A (ja) 1988-12-12

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