JPH0567037A - Dma transferring device - Google Patents

Abstract

PURPOSE:To realize a DMA device by which data can be transferred to the arbitrary address of memory by outputting aligned data to the arbitrary address, and writing the data in a memory, when a read signal is inactive, and a write signal is active. CONSTITUTION:At the time of operating a data transfer from an inputting and outputting device 15 to a memory 12 by a fly-by transfer system by using a DMAC 14, the DMAC 14 outputs a memory address to a system bus, transmits a DMAC transfer permitting signal DACK 17 to the inputting and outputting device 15, starts a read bus cycle, makes an inversion signal 18 of a read signal IOR active, and starts a data reading. And also, the DMAC 14 outputs an inversion signal 16 of a write signal MW to the memory 12. The inputting and outputting device 15 outputs read data to one part D15-0 of the data of the system bus, according as the DACK signal 17 and the IOR inversion signal 18 are active. An align mechanism 13 of the DMAC stores the data outputted to the data of the system bus in a register 21, and decides the number of shifts controlling an aligner 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct memory access device (hereinafter referred to as D) of an input / output device in an information processing device.
MAC).

[0002]

2. Description of the Related Art A DMAC is used when an input / output device such as a magnetic disk device, a communication device or a display device is connected to a common data transfer path (hereinafter referred to as a system bus).
This is a device for performing high-speed data transfer between an input / output device and a main storage device (hereinafter referred to as a memory) instead of a central processing unit (hereinafter referred to as a CPU) in order to increase the transfer speed.

In the DMAC, while the CPU transfers data by alternately performing a read cycle and a write cycle, a fly-by transfer method in which a read cycle and a write cycle are carried out at the same time can be used. Can be doubled.

[0004]

However, in the fly-by transfer method described above, the address at which data can be read and written to the memory is determined by the position of the data terminal of the input / output device on the system bus. For example, the width of the data terminal of the input / output device is 8 bits (ID7-0), the data width of the system bus is 16 bits (SD15-0), and ID7-0.
If the data is connected to SD7-0, the data read from the input / output device by fly-by transfer can be written in even addresses of the memory, but cannot be written in odd addresses.

An object of the present invention is to provide a DMA transfer device capable of reading / writing data read / written from an input / output device to an arbitrary address on a memory when the system bus width is 16 bits or more in fly-by transfer. To do.

[0006]

A DMA transfer device according to the present invention comprises an aligner capable of shifting or rotating input data in units of multiples of 8 bits (8, 16, 32 bits ...) According to a bus width and an address signal. A circuit for outputting a read / write signal to the input / output device and the memory; when the DMA transfer is started, the read signal and the write signal are made active, and when these signals are made inactive, the read signal is made inactive first And a control circuit for outputting data aligned to an arbitrary byte position by the aligner and writing the data in the memory or the input / output device while the read signal is inactive and the write signal is active. Characterize.

[0007]

1 is a block diagram for explaining an embodiment of the present invention. In this embodiment, the information processing device is the CPU 1
1, a memory 12, a DMAC 14, an input / output device 15, and an aligning mechanism 13, and these components are mutually connected through a system bus (data bus 19, address bus 20).

Here, a case where data is read from the input / output device 15 and written in the memory 12 will be described as an example. The data width of the input / output device 15 is 16 bits, and the data width of the system bus is 32 bits.

FIG. 2 is a block diagram showing the internal structure of the aligning mechanism 13 shown in FIG. 1. The register 21 and the aligner 2 are shown in FIG.
2, composed of an output buffer 23 and a control circuit 24. Further, FIG. 3 is a timing chart for explaining the present embodiment.

In this embodiment, when data is transferred from the input / output device 15 to the memory 12 using the DMAC 14 by the fly-by transfer method, the DMAC 14 outputs a memory address to the system bus (A31-0) and the input / output device 15 The DMA transfer permission signal DACK17 is sent to start the read bus cycle, and the inverted signal 1 of the read signal IOR
8 is activated and data reading is started. Also,
The inverted signal 16 of the write signal MW is output to the memory. The input / output device 15 outputs the read data to a part D15-0 of the data (D31-0) of the system bus in response to the activation of the DACK signal and the IOR inversion signal 18.

The DMAC alignment mechanism 13 stores the data output as the system bus data (D15-0) in the register 21, and the DMAC 14 sends the address (A1-
0), the number of shifts for controlling the aligner 22 is determined by obtaining the bus width information. The relationship between these addresses (A1-0), bus width and aligner control is shown in Table 1.

[0012]

[Table 1]

Next, the DMAC 14 outputs the IOR inversion signal 18
Is made inactive, the MW inversion signal 16 is kept active, the reading of data from the input / output device 15 is completed, and the aligner mechanism 13 causes the aligner 22 and the control circuit 2 to operate.
4, the data read from the input / output device 15 is aligned with an arbitrary address, the output buffer 23 is activated, and the data (D31-0) of the system bus is output.

As shown in FIG. 3, the DMA transfer permission signal DA
While the inversion signal of CK17 is active, the data 31 is read from the input / output device 15, and while the inversion signal is inactive and the inversion signal 16 of the write signal MW is active, the alignment mechanism 13 outputs the data 32 aligned at an arbitrary address. Output to the terminal.

In this way, it is possible to realize a DMA transfer device which can transfer data at high speed similarly to the fly-by transfer system and can transfer the data to any address of the memory.

[0016]

As described above, the present invention makes the write signal longer than the read signal in the fly-by transfer system, and outputs the data aligned at an arbitrary address when the read signal is inactive and the write signal is active. Writing to the memory has an effect that it can be transferred to an arbitrary address in the memory.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of an aligner mechanism 13 in the embodiment of FIG.

3 is an operation timing chart in the embodiment of FIG.

[Explanation of symbols]

 11 CPU 12 Memory (MEM) 13 Alignment Mechanism 14 DMAC 15 Input / Output Device (I / O) 16 Write Inversion Signal 17 DMA Transfer Permission Signal (DACK) 18 Read Signal (IOR) 19 Data Bus 20 Address Bus 21 Register 22 Aligner 23 Output buffer 24 Control circuit

Claims (1)

[Claims] 1. An aligner capable of shifting or rotating input data in units of multiples of 8 bits (8, 16, 32 bits ...) According to a bus width and an address signal; and outputting read and write signals to an input / output device and a memory. A circuit for making the read signal and the write signal active at the start of the DMA transfer and then making the read signal inactive first when making these signals inactive,
A control circuit for outputting data aligned to an arbitrary byte position by the aligner and writing the data in the memory or the input / output device while the read signal is inactive and the write signal is active. DMA transfer device.