經濟部中央標準扃貝工消费合作社印裂 A7 B7 五、發明説明（1 ) 本發明係有關於一種介面控制電路，特別是有關於一 種適用於DVD播放裝置（DVD player)，½配置於MPEG 解碼裝置和’DVD讀取裝置之間，使DVD讀取裝置之輸 出資料得以透過兩者之ATAPI介面，以DMA模式傳送 至MPEG解碼裝上之資料緩衝記憶裝置。而使用此介面 控制電路之DVD播放裝置也加以揭示。 一般而言DVD player大部份都分為機構i司服控制單 元（以下稱為DVD讀取裝置）和MPEG解碼器兩部份。 第1圖為一般DVD讀取裝置架構之示意圖。DVD光 碟1上之資料，經讀取裝置2讀取後，經一資料放大器 3放大處理後，分別輸入資料解碼器4和伺服控制器5。 祠服控制器5，利用輸入之資料處理後，再輸出回授信 號至驅動馬達6，使其轉速維持定線速度。f料解碼器 將光碟資料解出而成為MPEG模式之信號。由於一 般廠商在DVD讀取裝置中，定會建構有IDE-ATAPI介 面，所以MPEG資料可依照系統設計之需求，直接由資 料解碼器4之output端輸出、或是透過ATAPI介面7而 由ATAPI資料匯流排輸出至MPEG解碼器。上述資料解 碼器4、伺服控制器5以及ATAPI介面之協調動作係由 一中央處理單元CPU所統籌控制》在資料直接由資料解 瑪器4之output端輸出之架構下，DVD讀取裝置與 MPEG解碼器兩者間資料傳輸所使用之介面，必須使用 各家1C製造商提供之方式來處理，但因各家1C製造商 提供之1C規格不一，致使DVD製造商必須針對不同1C 3 (請先閱讀背面之注意事項再填寫本頁) ，訂 本紙張尺度適用中國國家揉準（CNS ) A4規捧（2丨0X297公釐） 經濟部中央標準局工消费合作社印*. A7 五、發明説明（2 ) 製造商所提供之1C來設計不同之介面電路，故缺乏設計 彈性；然而，利用ATAPI介面傳輸之方式，則為工業標 準介面，沒有上述問題。 一般ATAPI之資料傳輸模式可分為程式化輸·出/入棋 式（Programmedlnput/Output ;簡稱為 PIO)，以及直接記 憶想存取(Direct Memory Access ’簡稱為DMA)模式。 ATAPI介面在PIO傳輸模式下時，主要利用一主控 單元（例如CPU等）將一包袠指令（package command，12 byte)經資料匯流排和控制線匯流排傳送至ATAPI介 面，CPU與ATAPI介面兩者間，經過一定程序之交握 (hand-shake)認證，在確認無誤後，資料繼續在CPU之 監控下透過ATAPI介面而傳送至目的地。由上所述可 知，採用PIO模式傳輸資料，相當耗費CPU之時間.，因 而降低CPU之效率，且資料傳輸速度也太慢，因此一般 在下達包裹指令後，資料會改採DMA模式傳輸。 DVD播放裝置在播放影片之過程中，MPEG解碼器 所須解碼之資料流量大小、快慢不一；若此時ATAPI 採用DMA之傳輸模式，則資料緩衝區的大小選擇、及 讀/寫管理均很複雜，容易造成傳輸協定上之錯誤。況、 且，由於資料流量大小之不確定，通常需要耗費龐大之 記憶體。因此，上述ATAPI介面之兩種傳輸方式’應用 在DVD播放裝置上，均無法合乎功能及經濟效益之目 的0 有鑑於此，本發明為解決上述問題而提供一種ATAPI 4 (請先閲讀背面之注意事項再填寫本頁) *訂 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 297公釐） 經濟部中央標隼局貝工消费合作社印製 A7 B7 五、發明説明（3 ) 介面控制電路，可使DVD播放裝置中之MPEG解碼裝 置和DVD讀取裝置兩者在使用其AT API介面作DMA模 式之資料傳輸時，縮短CPU資料傳輸所需時間，增加系 統效率，並可以簡化資料緩衝區之管理，以節省記憶體 之使用。The Central Standard of the Ministry of Economic Affairs, Ai Binggong Consumer Cooperative Co., Ltd. printed A7 B7 V. Description of the invention (1) The present invention relates to an interface control circuit, in particular to a suitable for DVD player, which is configured for MPEG decoding Between the device and the DVD reading device, the output data of the DVD reading device can be transmitted to the data buffer memory device mounted on the MPEG decoder in DMA mode through the ATAPI interface of the two. A DVD player using this interface control circuit is also disclosed. Generally speaking, most of the DVD players are divided into two parts: the control unit of the server (hereinafter referred to as the DVD reading device) and the MPEG decoder. FIG. 1 is a schematic diagram of a general DVD reading device architecture. The data on the DVD disc 1 is read by the reading device 2 and amplified by a data amplifier 3, and then input to the data decoder 4 and the servo controller 5, respectively. The temple clothing controller 5 processes the input data and outputs a feedback signal to the drive motor 6 to maintain a constant line speed. f Decoder Decodes the disc data into a signal in MPEG mode. Since general manufacturers will definitely build IDE-ATAPI interfaces in DVD reading devices, MPEG data can be output directly from the output end of data decoder 4 or ATAPI data through ATAPI interface 7 according to system design requirements. The bus is output to an MPEG decoder. The above-mentioned coordinated actions of the data decoder 4, the servo controller 5, and the ATAPI interface are coordinated and controlled by a central processing unit CPU. "Under the structure that the data is directly output by the output end of the data decoder 4, the DVD reading device and MPEG The interface used for data transmission between the two decoders must be processed using the methods provided by each 1C manufacturer. However, due to the different 1C specifications provided by each 1C manufacturer, DVD manufacturers must target different 1C 3 (please Please read the notes on the back before filling this page). The size of the paper is applicable to China National Standards (CNS) A4 regulations (2 丨 0X297 mm). Printed by the Industrial and Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs *. A7 V. Description of the invention (2) The 1C provided by the manufacturer is used to design different interface circuits, so it lacks design flexibility; however, the transmission method using the ATAPI interface is an industry standard interface without the above problems. The general ATAPI data transmission mode can be divided into Programmable Input / Output / Enter Chess (Programmedlnput / Output; PIO for short), and Direct Memory Access (DMA) for short. When the ATAPI interface is in PIO transmission mode, a main control unit (such as a CPU, etc.) is mainly used to send a package command (12 byte) to the ATAPI interface via the data bus and control line bus. The CPU and ATAPI interface Between the two, after a certain process of hand-shake authentication, after confirming that it is correct, the data continues to be transmitted to the destination through the ATAPI interface under the supervision of the CPU. It can be known from the above that transmitting data in PIO mode takes a lot of CPU time. As a result, the efficiency of the CPU is reduced, and the data transmission speed is too slow. Therefore, after the package command is issued, the data will be transferred in DMA mode. The size and speed of the data flow that the MPEG decoder must decode during the playback of the DVD by the DVD player. If ATAPI uses the DMA transmission mode at this time, the size of the data buffer and the read / write management are very different. Complicated and easy to cause errors in transmission protocols. Moreover, due to the uncertainty of the data flow, large amounts of memory are usually required. Therefore, the two transmission methods of the above ATAPI interface are not suitable for the purpose of function and economic efficiency when applied to DVD playback devices. In view of this, the present invention provides an ATAPI 4 to solve the above problems (please read the note on the back first) Please fill in this page again for the matters) * The size of the paper is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) Printed by A7 B7, Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 5. Description of the invention (3) Interface control The circuit enables both the MPEG decoding device and the DVD reading device in the DVD playback device to use their AT API interface for DMA mode data transmission, shortening the time required for CPU data transmission, increasing system efficiency, and simplifying data buffering Zone management to save memory usage.
為達到上述目為，本發明提出之介面控制裝置，包 括：一控制信號傳輸裝置，用以傳送上述MPEG解碼裝 置對上述DVD讀取裝置之控制信號，及上述DVD讀取 裝置對上述MPEG解碼裝置之回應信號；一 DMA模式 信號產生器，用以當上述MPEG解碼裝置和上述DVD 讀取裝置完成上述DMA模式傳輸之準備動作時，產生 一 DMA致能信號，傳送給上述ATAPI介面，使上述DVDTo achieve the above object, the interface control device provided by the present invention includes: a control signal transmission device for transmitting a control signal of the MPEG decoding device to the DVD reading device, and the DVD reading device to the MPEG decoding device A response signal; a DMA mode signal generator for generating a DMA enabling signal when the MPEG decoding device and the DVD reading device complete the preparation for the DMA mode transmission, and transmitting the DMA enabling signal to the ATAPI interface to enable the DVD
J 讀取裝置得以開始透過上述ATAPI介面以上述DMA模 式傳送MPEG資料至上述MPEG解碼裝置；以及” 一資 料流量控制器，當偵測出上述MPEG解碼器之記憶裝置 所累積之上述MPEG資料已達一預設值時，便請求上述 DMA模式信號產生器將上述DMA致能訊號切斷，使上 述DVD讀取裝置暫時停止將MPEG資料傳送至上述 MPEG解碼器，而當上述MPEG解碼器之記憶裝置所累 積之資料不足時、或當上述DVD讀取裝置停止傳送歷 經一特定時間後，則請求上述DMA模式信號產生器將 上述DMA致能訊號予以恢復，使MPEG資料得以繼續 透過上述ATAPI介面來進行傳輸，並重複上述切斷與恢 復之程序，直到所有MPEG資料傳送完畢為止。 5 本紙張尺度適用中國國家揉準（CNS > A4規格（210X297公釐） ml n HI ^^^1 i m nn n nn I ^ in— n^i ml ml - - (請先閱讀背面之注意事項再填寫本頁) 經濟部中央揉準局貝工消费合作社印氧 A7 B7 五、發明説明（4 ) 圖式之簡單說明： 為讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉較佳之實施例，並配合所附圖式，做詳細 說明如下： - 第1圊係表示一般DVD讀取裝置架構之示意圖； 第2圖係表示應用本發明介面控制器之DVD播放裝 直的示意方塊圖； 第3圖係表示本發明之一實施例電路示意圖；以及 第4圖表示，DMA模式信號產生器相關信號之時序 圖。 符號說明： 1〜光碟片；2〜讀取裝置；3〜放大器；4~資料解碼 器；5〜伺服控制器；6〜驅動馬達；7〜ATAPI介面； 20〜DVD讀取裝置；201~MPEG資料；202~ATAPI介 面；21〜ATAPI介面控制電路；22-MPEG解碼裝置； 211〜控制信號傳輸裝置；212〜DMA模式信號產生器； 213〜資料流量控制器；221〜FIFO緩衝裝置；222~資料 緩衝記憶體；223〜DMA控制器。 實施例： 第2圖中，CPU主要係控制MPEG解碼器之動作， 例如在播放影片時，CPU即發出指令透過控制信號傳 輸裝置211傳送至ATAPI介面，ATAPI介面則依指令由 DVD光碟上讀出MPEG資料，並回應信號給CPU表示 完成準備，並發出DMA請求信號(DMA_req)，準備以 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公嫠〉 (請先閱讀背面之注意事項再填寫本頁)The J reading device was able to start transmitting MPEG data to the MPEG decoding device in the DMA mode through the ATAPI interface; and "a data flow controller, when detecting that the MPEG data accumulated by the memory device of the MPEG decoder has reached At a preset value, the DMA mode signal generator is requested to cut off the DMA enable signal, so that the DVD reading device temporarily stops transmitting MPEG data to the MPEG decoder, and when the memory device of the MPEG decoder When the accumulated data is insufficient, or when the DVD reading device stops transmitting for a certain period of time, the DMA mode signal generator is requested to restore the DMA enable signal, so that MPEG data can continue to be processed through the ATAPI interface. Transmission, and repeat the above-mentioned cut-off and recovery procedures until all MPEG data have been transmitted. 5 This paper size applies to the Chinese national standard (CNS > A4 specification (210X297 mm) ml n HI ^^^ 1 im nn n nn I ^ in— n ^ i ml ml--(Please read the precautions on the back before filling this page) Printed oxygen A7 B7 V. Brief description of the invention (4) Drawings: In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are given below, in conjunction with the accompanying drawings, The detailed description is as follows:-Fig. 1 is a schematic diagram showing the structure of a general DVD reading device; Fig. 2 is a schematic block diagram showing a DVD playback device using the interface controller of the present invention; Fig. 3 is one of the present invention The schematic circuit diagram of the embodiment; and Fig. 4 shows the timing diagram of the signals related to the DMA mode signal generator. Symbol description: 1 ~ disc; 2 ~ reading device; 3 ~ amplifier; 4 ~ data decoder; 5 ~ servo control 6 ~ drive motor; 7 ~ ATAPI interface; 20 ~ DVD reading device; 201 ~ MPEG data; 202 ~ ATAPI interface; 21 ~ ATAPI interface control circuit; 22-MPEG decoding device; 211 ~ control signal transmission device; 212 ~ DMA mode signal generator; 213 ~ data flow controller; 221 ~ FIFO buffer device; 222 ~ data buffer memory; 223 ~ DMA controller. Example: In the second figure, the CPU mainly controls the movement of the MPEG decoder. For example, when playing a movie, the CPU sends a command to the ATAPI interface through the control signal transmission device 211, and the ATAPI interface reads the MPEG data from the DVD disc according to the command, and responds to the CPU to indicate completion of the preparation and sends a DMA request signal. (DMA_req), ready to apply Chinese National Standard (CNS) A4 specification (210X297) at 6 paper sizes (Please read the precautions on the back before filling this page)
、tT 絲 經濟部中央標準扃員工消费合作社印家 A7 B7 五、發明説明（5 ) DMA模式像送MPEG資料。接著，DMA模式信號產生 器212和DMA控制器223 ’藉由DMA_req信號和由DMA 控制器223發出之控制信號，完成DMA資料傳送之交 握確認（hand-shake)控制後，再由DMA控制器223，控 制MPEG資料經FIFO緩衝裝置221而輸入至資料缓衝 記憶體222’以提供MPEG解碼器22工作之所須。其中， 在資料緩衝記憶艘222收到一預定量之資料時，資料流 量控制器213將會自動切斷Dma模式信號產生器212 之信號’以阻止ATAPI上之資料繼續傳輸。 第3圖顯示本發明之一實施例示意圖，其中與第2圖 相同之單元則以相同符號標示。以下將參照第3圖，對 本發明ATAPI介面電路應用於dvd播放裝置中之動作 情形詳細加以描述。 如同第2圓之解說，CPU主要係控制MPEG解碼器 22之動作，例如在播放影片時，CPU即發出指令透過 控制信號傳輸裝置211傳送至ATAPI介面，ATAPI介面 則依指令由DVD光碟上讀出MPEG資料，並回應信號 給CPU表示完成準備’並發出DMA請求信號 (DMA_req)’準備以DMA模式傳送MPEG資料。由於對 ATAPI下達指令，必須使用Pio模式以便將控制指令傳 入AT API之命令暫存器中，故控制信號傳輸裝置211可 能的實施電路如第3圈所示《本實施例中*控制MPEG 解碼器之CPU為8位元，而ATAPI為16位元介面，所 以由第一栓鎖電路211a和選擇電路211b，將由CPU經 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注^項再填寫本頁) 訂 -锊· A7 B7 經濟部中央梂準局Λ工消费合作社印家 五、發明説明（6) data—bus傳送之2個8位元控制資料合成一 16位元資料 後再送往ATAPI介面。同理，ATAPI回應之16位元資 料則先存於第二栓鎖電路211c中，而由多工器21 Id分 成8位元之控制資料而傳回給CPU β - 當MPEG解碼器22藉由其CPU下達讀取資料之指令 後’則MPEG解碼器22和DVD讀取裝置20，將使用 DMA模式來讀取MPEG資料。其詳細動作情形如下文所 述。 ATAPI介面202接到CPU之讀取命令後，由於須進 行DMA模式傳送，所以ATAPI介面202將DMA存取要 求信號(DMA_req)啟動後，傳給CPU，表示其已準備以 DMA模式來傳送資料。而同時，DMA模式信號產生器 212 ’亦將此DMA_req信號傳送給MPEG解碼器22中 之DMA控制器223，請求確認DMA控制器223是否完 成準備’若已完成準備，則DMA模式信號產生器212 將發出一 DMA致能信號（DMA_ack)給ATAPI，用以通 知ATAPI介面202表示MPEG解碼器22已準備以DMA 模式接收資料。經一特定時間之後，DMA控制器223 將DMA讀取信號（DMA_read)啟動後，傳給DMA模式信 號產生器212,以表示資料將由ATAPI介面往MPEG解 碼器22中之資料緩衝記憶體222傳送。接著，ATAPI 介面202將其資料DATA置於資料匯流排DATA_BUS 上’以供讀取。以上動作之時序圖如第4圖所示，當DATA 於資料匯流排可以有效讀取時，MPEG解碼器22藉由 8 (請先閱讀背面之注<1^項再填寫本頁) ，訂. 本紙張尺度ii用㈣g家網^ ( CNS )( 21GX297公爱） A7 B7 經濟部中失橾準局貝工消费合作社印製 五、發明説明（7) DMA控制器輸出MPEG_read之讀取信號，而將 DATA_BUS上之DATA讀取，透過FIFO緩衝裝置，而 寫入資料緩衝記憶體222。一般MPEG均設有並列式或 串列式之FIFO緩衝裝置，如第3圏所示之FIF〇(p)及 FIFO(s)，可任選其一來作資料之I/O處理，但若使用串 列式輸入的話，則需先將data利用並列·串列轉換裝置 PISO轉為串列資料後，而經FIFO(S)寫入資料緩衝記憶 體 222。 緩衝記憶體222寫入資料後，資料流量控制器213， 透過DMA控制器223持續監控緩衝記憶體222寫入之狀 況，例如透過一計數器，來計算寫入之資料量。當寫入 緩衝記憶體222之資料量達到一預設值時，資料流量控 制器213即將DMA模式信號產生器212發出之DMA致 能信號DMA_ack信號切斷，以阻止ATAPI上之資料繼 續傳輸。參照第4圖之時序，唯有當DMA致能信號 DMA_ack觸發後（處於low狀態），以下DMA_read等之 信號才會——起動，故當寫入緩衝記憶體222之資料量 達到一預設值時，資料流量控制器213將會請求DMA 模式信號產生器212把DMA致能信號DMA_ack持續保 持在high之狀態，故而ATAPI未傳送之資料不致流失， 而MPEG解碼器22也暫時不會再讀取MPEG資料。當 緩衝記憶體222之資料處理後，資料不足時，或經一特 定時間後，資料流量控制器213會請求DMA模式信號 產生器212再將DMA致能信號DMA_ack信號恢復正 本紙張尺度逋用中國國家梯準（CNS > A4規格（2丨〇><297公釐） (請先閲讀背面之注意事項再填寫本頁) r -銷·、 TT silk Central Standard of the Ministry of Economic Affairs 扃 Employee Consumer Cooperatives A7 B7 V. Description of the invention (5) DMA mode sends MPEG data. Next, the DMA mode signal generator 212 and the DMA controller 223 ′ use the DMA_req signal and the control signal sent by the DMA controller 223 to complete the hand-shake control of DMA data transmission, and then the DMA controller 223. Control the MPEG data to be input into the data buffer memory 222 'through the FIFO buffer device 221 to provide the MPEG decoder 22 with what it needs to work. Among them, when the data buffer memory 222 receives a predetermined amount of data, the data flow controller 213 will automatically cut off the signal of the Dma mode signal generator 212 to prevent the data on the ATAPI from continuing to be transmitted. FIG. 3 shows a schematic diagram of an embodiment of the present invention, and the same elements as those in FIG. 2 are marked with the same symbols. The operation of the ATAPI interface circuit of the present invention applied to a DVD player will be described in detail below with reference to FIG. 3. As explained in the second circle, the CPU mainly controls the operation of the MPEG decoder 22. For example, when playing a movie, the CPU sends a command to the ATAPI interface through the control signal transmission device 211, and the ATAPI interface is read from the DVD disc according to the instruction. MPEG data, and respond to the signal to the CPU to indicate that it is ready to 'and send a DMA request signal (DMA_req)' ready to transmit MPEG data in DMA mode. Since the instruction is given to ATAPI, the Pio mode must be used in order to transfer the control instruction to the command register of AT API. Therefore, a possible implementation circuit of the control signal transmission device 211 is shown in the third circle. "Control MPEG decoding in this embodiment * The CPU of the device is 8-bit, and the ATAPI is a 16-bit interface, so the first latch circuit 211a and the selection circuit 211b will be adapted by the CPU to the Chinese National Standard (CNS) A4 specification (210X297 mm) via this paper size (please (Please read the note ^ on the back before filling this page) Order- 锊 · A7 B7 Yin Jia, Consumer Product Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5.Invention (6) Synthesis of 2 8-bit control data transmitted by data-bus A 16-bit data is sent to the ATAPI interface. Similarly, the 16-bit data of the ATAPI response is stored in the second latch circuit 211c first, and is divided into 8-bit control data by the multiplexer 21 Id and returned to the CPU β-when the MPEG decoder 22 uses the After the CPU issues an instruction to read the data, the MPEG decoder 22 and the DVD reading device 20 will use the DMA mode to read the MPEG data. The detailed operation situation is as follows. After receiving the read command from the CPU, the ATAPI interface 202 needs to perform DMA mode transmission, so the ATAPI interface 202 transmits the DMA access request signal (DMA_req) to the CPU, indicating that it is ready to transfer data in the DMA mode. At the same time, the DMA mode signal generator 212 'also transmits this DMA_req signal to the DMA controller 223 in the MPEG decoder 22, and requests to confirm whether the DMA controller 223 is ready.' If the preparation is completed, the DMA mode signal generator 212 A DMA enable signal (DMA_ack) will be sent to ATAPI to notify the ATAPI interface 202 that the MPEG decoder 22 is ready to receive data in DMA mode. After a specific time, the DMA controller 223 starts the DMA read signal (DMA_read) and sends it to the DMA mode signal generator 212 to indicate that data will be transmitted from the ATAPI interface to the data buffer memory 222 in the MPEG decoder 22. Next, the ATAPI interface 202 places its data DATA on the data bus DATA_BUS for reading. The timing diagram of the above action is shown in Figure 4. When DATA can be read effectively on the data bus, the MPEG decoder 22 uses 8 (please read the note on the back < 1 ^ before filling this page), and order This paper size ii is printed on the home network ^ (CNS) (21GX297 Public Love) A7 B7 Printed by the Shell Bureau Consumer Cooperative of the Ministry of Economic Affairs of the People's Republic of China V. Description of the invention (7) The DMA controller outputs the read signal of MPEG_read, The DATA on DATA_BUS is read and written into the data buffer memory 222 through the FIFO buffer device. Generally, MPEG is equipped with a parallel or serial FIFO buffer device, such as FIF0 (p) and FIFO (s) shown in Figure 3, which can be selected for I / O processing of data, but if If serial input is used, the data must first be converted into serial data using the parallel-serial conversion device PISO, and then written into the data buffer memory 222 via the FIFO (S). After the buffer memory 222 writes data, the data flow controller 213 continuously monitors the status of the buffer memory 222 writes through the DMA controller 223, for example, a counter to calculate the amount of data written. When the amount of data written into the buffer memory 222 reaches a preset value, the data flow controller 213 cuts off the DMA enable signal DMA_ack signal sent from the DMA mode signal generator 212 to prevent the data on the ATAPI from continuing to be transmitted. Referring to the timing diagram in Figure 4, only when the DMA enable signal DMA_ack is triggered (in the low state), the following signals such as DMA_read will be activated-so when the amount of data written into the buffer memory 222 reaches a preset value At this time, the data flow controller 213 will request the DMA mode signal generator 212 to keep the DMA enable signal DMA_ack continuously in the high state, so the data not transmitted by ATAPI will not be lost, and the MPEG decoder 22 will not be read again temporarily. MPEG information. When the data in the buffer memory 222 is processed, when the data is insufficient, or after a certain period of time, the data flow controller 213 will request the DMA mode signal generator 212 to restore the DMA enable signal DMA_ack signal to the original paper size and use China Ladder standard (CNS > A4 specification (2 丨 〇 > < 297 mm) (Please read the precautions on the back before filling in this page) r -pin ·
I 經濟部中央揉準局貝工消费合作社印製 A7 B7 五、發明説明（8 ) 常，則可依正常情況進行資料接收。 如第2、3圖所示，具有本發明介面電路之DVD播 放裝置，包括一 DVD讀取裝置20,一介面控制裝置21， 以及，一 MPEG解碼裝置22，其中，ATAPI介面控制 電路，配置於MPEG解碼裝置和DVD讀取裝置之間， 其特徵在於：上述DVD讀取裝置輸出之MPEG資料係 透過上述ATAPI介面而以DMA模式傳送至上述MPEG 解碼裝置中。其動作原理如上述，在此不再加以贅述。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟悉本項技藝者，在不脫離本發 明之精神和範圍内，當可做些許之更動和潤飾，因此本 發明之保護範圍當視後附之申請專利範圍所界定者為 準。 (請先閱讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）I Printed by Shellfish Consumer Cooperative of the Central Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (8) If available, data can be received according to normal circumstances. As shown in FIGS. 2 and 3, the DVD playback device having the interface circuit of the present invention includes a DVD reading device 20, an interface control device 21, and an MPEG decoding device 22, wherein the ATAPI interface control circuit is configured in Between the MPEG decoding device and the DVD reading device, the MPEG data output by the DVD reading device is transmitted to the MPEG decoding device in the DMA mode through the ATAPI interface. The operation principle is as described above, and it will not be repeated here. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page.) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm)