JPH11328842A - Atapi interface control circuit and dvd player using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the efficiency of the whole of a system and to save memories to be used at the time an MPEG decoder and a DVD reader in a DVD player perform data transmission of a DMA mode via an ATAPI interface. SOLUTION: A processing of temporarily stopping the transmitting of MPEG data to an MPEG decoder 22 by a DVD reader by requesting the interrupting of a DMA possible signal to a DMA mode signal generating part 212 when the MPEG data stored in the data buffer memory 222 of the MPEG decoder 22 reach a prescribed value and a processing of requesting the revival of the DMA possible signal to the DMA mode signal generating part 212 when the MPEG data stored in the data buffer memory 222 of the MPEG decoder 22 do not reach the prescribed value or when a prescribed time is elapsed after the DVD 20 stopped the transmitting of data are repeated until the transmitting of the MPEG data is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface control circuit, and more particularly to an interface control circuit applicable to a DVD player, that is, a DVD reader and an MPE.
The present invention relates to an interface control circuit arranged between a G decoder and a controller for controlling transmission of MPEG data output from a DVD reader to a buffer memory of the MPEG decoder via an ATAPI interface.
The present invention also discloses a DVD player using the ATAPI interface control circuit.

[0002]

2. Description of the Related Art A DVD player generally includes a servo control unit (hereinafter referred to as a DVD reader) and an MPEG decoder.

FIG. 1 is a circuit block diagram showing a general configuration of a DVD reader. After the data on the DVD optical disk 1 is read by the reading unit 2, the data is amplified by the amplifying unit 3 and input to the data decoder 4 and the servo control unit 5. After performing processing using the input data, the servo control unit 5 outputs a feedback signal and transmits the feedback signal to the drive motor 6 to rotate the motor 6 at a constant linear velocity (con
stant line speed). The data decoder 4
The data from the optical disk 1 is decoded and output as an MPEG data signal. In general, an IDE-ATAPI interface is provided in the DVD reader, so that the MPEG data can be directly output from the output terminal of the data decoder 4 to the MPEG decoder, or the ATAPI interface 7 can be used, depending on the needs of the system design. Under control, the data can be output to the MPEG decoder through the ATAPI data bus. The operations among the data decoder 4, the servo control unit 5, and the ATAPI interface 7 are managed and controlled by a central processing unit (CPU) 8. However, when data is directly output from the output terminal of the data decoder 4 to the MPEG decoder, the DVD maker must use an interface provided by the IC maker for data transmission between the DVD reader and the MPEG decoder. In addition, since the IC standard varies depending on the manufacturer, the DVD maker must design a plurality of types of interface circuits according to the various IC standards, which is extremely disadvantageous in terms of flexibility and economy. On the other hand, the ATAPI interface is an interface of an industrial standard, and if it is used, the above-described problem does not occur.

In general, data transmission through the ATAPI interface is performed by using a programmed I / O (Programmed Input / Output).
/ 0 utput: hereinafter referred to as PIO) mode, and direct memory access (Direct Memory Access: hereinafter D)
MA mode).

When the ATAPI interface is in the PIO transmission mode, the data bus and control line bus under control of, for example, a CPU or the like.
A package command (package command, 12 bytes) is transmitted to the ATAPI interface via the
After confirming the execution of the handshake between the ATA and the ATAPI interface, the ATA
Data is transmitted to the destination via the PI interface. As can be seen from the above, data transmission in the PIO mode requires a considerable amount of CPU time, which causes a reduction in efficiency and also has a disadvantage in that the data transmission rate decreases. For this reason, in the PIO mode, after transmitting a package command, it is general to switch to the DMA mode and then transmit data.

[0006]

For example, during operation of a DVD player for reproducing a moving image or the like, a data stream to be decoded by an MPEG decoder is not constant in size and speed. In this case, if the DMA mode is adopted in the ATAPI interface, the size of the data buffer becomes large, and the management of reading and writing becomes complicated, so that a protocol error easily occurs. Moreover, since the size of the data stream is uncertain, a huge amount of memory is consumed. Therefore, ATAPI
When these two types of data transmission methods in the interface are applied to a DVD player, efficiency and
It cannot meet the purpose of economics.

[0007] In order to solve the above problems, an object of the present invention is to provide a new ATAPI interface control circuit. If this ATAPI interface control circuit is used, the DVD reader in the DVD player and the MP
When the EG decoder and the EG decoder perform data transmission in the DMA mode via the ATAPI interface, the CPU can reduce the time required for data transmission to improve the efficiency of the system, and at the same time, manage the data buffer. The simplification can save the memory used. Another object of the present invention is to provide a DVD player using such an ATAPI interface control circuit.

[0008]

According to a first aspect of the present invention, there is provided an image processing apparatus, comprising: a DVD reader and an MPEG decoder; and MPEG data output from the DVD reader via an ATAPI interface. AT for controlling transmission to the MPEG decoder by means of
In the API interface control circuit, the MPEG
A control signal from the decoder to the DVD reader;
A control signal transmission unit for transmitting a response signal of the control signal from the VD reader to the MPEG decoder, and when the MPEG decoder and the DVD reader complete preparation for MPEG data transmission in the DMA mode,
By transmitting a DMA enable signal to the ATAPI interface, the DMA mode is transmitted to the MPEG decoder via the ATAPI interface in the DMA mode.
A DMA mode signal generator for enabling the DVD reader to transmit EG data; and a DMA mode signal generator when the MPEG data stored in the memory of the MPEG decoder reaches a predetermined value. Said D
The transmission of the MPEG data to the MPEG decoder by the DVD reader is temporarily stopped by requesting the interruption of the MA enable signal, and when the MPEG data stored in the memory of the MPEG decoder is less than a predetermined number, or When a predetermined time has elapsed since the reader stopped data transmission, MPEG data can be continuously transmitted through the ATAPI interface by requesting the DMA mode signal generation unit to restore the DMA enable signal. And a data stream control unit that repeats a process of requesting the interruption / reactivation of the DMA enable signal until the transmission of the MPEG data is completed.

In the second invention, a DVD reader and an MP
An ATAPI interface control circuit disposed between the MPEG decoder and the EG decoder for controlling transmission of MPEG data output from the DVD reader to the MPEG decoder via an ATAPI interface; A control signal transmitting unit for transmitting a control signal for controlling the control signal to the DVD reader, and transmitting a control signal response signal from the DVD reader to the MPEG decoder when a response signal is supplied from the DVD reader. , When the MPEG decoder and the DVD reader are ready for MPEG data transmission in the DMA mode, the MPEG mode is enabled in the DMA mode via the ATAPI interface.
Transmitting MPEG data to a decoder
Generating a DMA enable signal to enable the reader,
A DMA mode signal generator for transmitting to the TAPI interface;
When the PEG data reaches a predetermined value, the DMA mode signal generation unit is requested to shut off the DMA enable signal so as to temporarily stop the transmission of the MPEG data to the MPEG decoder by the DVD reader.
When the number of MPEG data stored in the memory of the G decoder is less than a predetermined number, or when a predetermined time has elapsed since the DVD reader stopped data transmission, the MPEG
The DMA mode signal generation unit is requested to restore the DMA enable signal so that data can be continuously transmitted through the ATAPI interface, and the DMA enable signal is interrupted until the transmission of the MPEG data is completed.
A data stream control unit that repeats a process for requesting a resurrection.

Further, in the third invention, a DVD reader and an M
The MP output from the DVD reader is disposed between the PEG decoder and the DVD reader and the MPEG decoder.
The EG data is transferred to the M via the ATAPI interface.
ATAP for controlling transmission to PEG decoder
An ATAPI interface control circuit for transmitting a control signal from the MPEG decoder to the DVD reader and a response signal of the control signal from the DVD reader to the MPEG decoder. Control signal transmission unit, and the MPEG decoder and the DVD reader
When preparation for MPEG data transmission in the MA mode is completed, transmitting a DMA enable signal to the ATAPI interface to transmit MPEG data to the MPEG decoder in the DMA mode via the ATAPI interface. A DMA mode signal generator for enabling the DVD reader;
When the MPEG data stored in the memory of the G decoder reaches a predetermined value, the DVD mode reader requests the DMA mode signal generation unit to cut off the DMA enable signal, thereby enabling the DVD reader to send the MPEG data to the MPEG decoder.
When the transmission of data is temporarily stopped and the MPEG data stored in the memory of the MPEG decoder is less than a predetermined number, or when a certain time has elapsed since the DVD reader stopped data transmission, the DMA mode is used. By requesting the signal generation unit to restore the DMA enable signal, the MPEG data can be continuously transmitted through the ATAPI interface, and a request to shut off and restore the DMA enable signal until the MPEG data transmission is completed. And a data stream control unit that repeats the processing to be performed.

Still further, in the fourth invention, a DVD reader, an MPEG decoder, and an MPEG data output from the DVD reader are arranged between the DVD reader and the MPEG decoder via an ATAPI interface. A for controlling transmission to the decoder
In a DVD player having a TAPI interface control circuit, the ATAPI interface control circuit, when given a control signal for controlling the DVD reader from the MPEG decoder, outputs the control signal to the DV signal.
A control signal transmitting unit for transmitting a response signal of the control signal from the DVD reader to the MPEG decoder when receiving the response signal from the DVD reader;
When the preparation for G data transmission is completed, the ATAPI
The M mode through the interface via the DMA mode.
A DMA mode signal generating unit for generating a DMA enable signal for enabling the DVD reader to transmit MPEG data to the PEG decoder and transmitting the signal to the ATAPI interface; and an MPEG data stored in a memory of the MPEG decoder. When a predetermined value is reached, the DV
Requesting the DMA mode signal generator to shut off the DMA enable signal in order to temporarily stop the transmission of MPEG data to the MPEG decoder by the D reader, and the predetermined number of MPEG data stored in the memory of the MPEG decoder M, or when a certain time has elapsed since the DVD reader stopped data transmission,
The DMA mode signal generation unit is requested to restore the DMA enable signal so that the PEG data can be continuously transmitted through the ATAPI interface.
And a data stream control unit that repeats a process of requesting to block and restore the DMA enable signal until the transmission of the EG data is completed.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS In order to further clarify the objects, features and advantages of the present invention, preferred embodiments will be described below with reference to the drawings.

FIG. 2 is a circuit block diagram showing a configuration of a DVD player to which the interface control circuit according to the present invention is applied.

In FIG. 2, CPU 220 is mainly composed of an MPE.
The G decoder 22 is controlled. For example, during operation such as playing a moving image, a command issued by the CPU 220 is transmitted to the ATAPI interface 202 through the control signal transmission unit 211, and the ATAPI interface 202 receiving the command transmits the DVD according to the content of the command. The MPEG data stored on the optical disk is accessed. On the other hand, the ATAPI interface 202 sends a response signal indicating that the preparation is completed to the CPU 220 and outputs a DMA request signal (DMA_req) to trigger MPEG data transmission in the DMA mode. Next, D
MA mode signal generation section 212 and DMA control section 223
Are the DMA request signal (DMA_req), and the DMA
The control signal output from the control unit 223 completes the handshake control of the DMA data transmission. Then, under the control of the DMA control unit 223, the FIFO
The MPEG data is input to the data buffer memory 222 via the O-buffer 221 and data necessary for the operation of the MPEG decoder 22 is provided. Here, when the amount of data received by the data buffer memory 222 reaches a predetermined value, the data stream control unit 213 cuts off the signal output from the DMA mode signal generation unit 212, and
The transmission of the MPEG data in the PI interface 202 to the data buffer memory 222 is stopped.

FIG. 3 is a circuit block diagram showing the configuration of one embodiment of the present invention. Here, parts common to FIG. 2 are given the same reference numerals. Hereinafter, with reference to FIG. 3, the operation when the ATAPI interface control circuit according to the present invention is applied to a DVD player will be described in more detail.

As in the description of FIG.
Reference numeral 220 mainly controls the operation of the MPEG decoder 22.
For example, during operation such as playing a video, the CPU
The command issued by 220 is transmitted to the ATAPI interface 202 via the control signal transmission unit 211, and the ATAPI interface 202 receiving the command transmits the command stored in the DVD optical disk according to the content of the command.
Access PEG data. On the other hand, the ATAPI interface 202 sends a response signal notifying that the preparation has been completed to the CPU 220, and also outputs a DMA request signal (DMA_r
eq) to trigger MPEG data transmission in the DMA mode. Since a command is issued to the ATAPI interface 202, the control command is P
ATAPI interface 202 using IO mode
Must be transmitted to the command temporary storage section inside,
Therefore, a practical circuit that can be used as the control signal transmission unit 211 is as shown in FIG. In this embodiment, MP
The CPU 220 that controls the EG decoder 22 is 8-bit, while the ATAPI is a 16-bit interface. Therefore, the two 8-bit commands output from the CPU 220 via the data bus are combined into 16-bit data by the first latch circuit 211a and the selection circuit 211b, and then transmitted to the ATAPI interface. Similarly, the ATAPI interface 202
The 16-bit response signal output from is stored first in the second, divided into two 8-bit signals by and then sent back to the CPU 220. The latch circuits 211a,
211c, selection circuit 211b and multiplexer 211
d operates under the control of the CPU 220 in cooperation with the control logic circuit 211e.

After the MPEG decoder 22 issues a data read command from the CPU 220, the MPEG decoder 22 and the DVD reader 20 read the MPEG data in the DMA mode in cooperation with the ATAPI interface control circuit 21. A detailed series of processes will be described below.

The ATAPI interface 202 is a CPU
After receiving the read command from 220, to trigger the transmission of MPEG data in DMA mode,
Activate DMA request signal (DMA_req)
220 to inform that it is ready for data transmission in DMA mode. At the same time, the DMA mode signal generation unit 212 outputs the DMA request signal (DMA_re
q) is also transmitted to the DMA controller 223 in the MPEG decoder 22, and the DMA controller 223
It is confirmed whether the preparation for the transmission of the EG data is completed.
If the preparation has already been completed, the DMA mode signal generation unit 212 sends the DMA enable signal (DMA_ack) to the AT
It transmits to the API interface 202 and informs the ATAPI interface 202 that the MPEG decoder 22 is ready to receive MPEG data in DMA mode. After a lapse of a predetermined time, the DMA controller 223 activates the DMA read signal (DMA_read) and transmits it to the DMA mode signal generation unit 212, and the data is transmitted from the ATAPI interface 202 to the data buffer memory 222 in the MPEG decoder 22. Notify that.
Then, the ATAPI interface 202 accesses a data bus (DATA_BU) to access the MPEG data.
S). The timing of the above series of operations is shown in FIG. MPEG data is on the data bus,
When the data can be effectively accessed, the MPEG data on DATA_BUS is read by the instruction of the read signal (MPEG_read) from the DMA control unit 223, and the data buffer memory 2 is read via the FIFO buffer.
22 is written. MPEG decoders generally have a parallel buffer FIFO as shown in FIG.
(P) and a serial type buffer FIFO (s), and one of them can be arbitrarily selected to perform data input / output (I / O) processing. However, when the serial type FIFO buffer FIFO (s) is selected, the parallel / serial conversion unit PISO214 for converting parallel data (for example, 16 bits) into serial data is connected to the serial type FIFO buffer FIFO (s). Must be placed in front of. Serial FIFO buffer FIFO
The serial data is transferred to the data buffer memory 222 via (s).
Is written to.

MPEG to data buffer memory 222
When the data writing is started, the data stream control unit 213 monitors the data writing status to the data buffer memory 222 via the DMA control unit 223. In this monitoring method, for example, a counter is provided in the data stream control unit 213, and the data buffer memory 22
For example, there is a method of counting the accumulated amount of MPEG data written in the second. When the amount of MPEG data written to the data buffer memory 222 reaches a predetermined value, the data stream control unit 213 cuts off the DMA enable signal (DMA_ack) output from the DMA mode signal generation unit 212, and the ATAPI interface 202 MPE
Stop transmission of G data. As can be seen from the timing chart of FIG. 4, the DMA enable signal (DMA_ack)
Is activated (low level state), signals thereafter such as a DMA read signal (DMA_read) are also activated one after another. Therefore, when the amount of data written to the data buffer memory 222 reaches a predetermined value,
The data stream control unit 213 sends a DMA enable signal (DMA_ACK) to the DMA mode signal generation unit 212.
To be maintained at a high level. Therefore, the untransmitted data is held in the ATAPI interface 202, and the MPEG decoder 22 also temporarily stops reading the MPEG data. When the MPEG data stored in the data buffer memory 222 is less than a specific number of bytes for processing, or when the MPEG decoder 22 stops receiving the MPEG data for a certain period of time, the data stream control unit 213 generates a DMA mode signal. It instructs the unit 212 to restore the DMA enable signal (DMA_ACK) to a normal state, so that data transmission between the DVD reader 20 and the MPEG decoder 22 can be continued.

As shown in FIGS. 2 and 3, a DVD player having an interface control circuit according to the present invention includes a DVD reader 20, an ATAPI interface control unit 21, and an MPEG decoder 22,
The API interface control circuit 21 is a DVD reader 20
And the MPEG decoder 22, and the DV
MPEG data output from the D reader 20
Through the PI interface 202, the MPE is controlled in the DMA mode under the control of the ATAPI interface control unit 21.
It is characterized by transmission to the G decoder 22. Since the operation principle is as described above, the description is omitted here.

While the preferred embodiments have been disclosed above, they are not intended to limit the scope of the invention in any way, and anyone skilled in the art will be able to provide the same without departing from the spirit and scope of the invention. Various variations and additions should be made, and accordingly, the protection scope of the present invention is based on the contents specified in the claims.

[0022]

As described in detail above, the AT according to the present invention
According to the API interface control circuit and the DVD player using the circuit, the DV
When the D reader and the MPEG decoder perform data transmission in the DMA mode via the ATAPI interface, the CPU shortens the time required for data transmission, thereby improving the system efficiency. Memory can be saved by simplifying the management of.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a general configuration of a DVD reader.

FIG. 2 is a circuit block diagram showing a configuration of a DVD player to which an interface control circuit according to the present invention is applied.

FIG. 3 is a circuit block diagram showing a configuration of one embodiment of the present invention.

FIG. 4 is a timing chart of related signals of a DMA mode signal generation unit.

[Explanation of symbols]

 Reference Signs List 20 DVD reader 21 ATAPI interface control circuit 22 MPEG decoder 201 MPEG data 202 ATAPI interface 211 Control signal transmission unit 212 DMA mode signal generation unit 213 Data stream control unit 222 Data buffer memory 223 DMA control unit

Claims (4)

[Claims] An MPEG output device arranged between a DVD reader and an MPEG decoder and output from the DVD reader.
The data is transferred to the MPE through an ATAPI interface.
An ATAPI interface control circuit for controlling transmission to a G decoder, for transmitting a control signal from the MPEG decoder to the DVD reader and a response signal of the control signal from the DVD reader to the MPEG decoder. The MPEG decoder and the DVD reader are DMA
When the preparation of the MPEG data transmission in the mode is completed, the DMA transmission of the MPEG data to the MPEG decoder in the DMA mode through the ATAPI interface by transmitting the DMA enable signal to the ATAPI interface. A DMA mode signal generation unit for enabling a DVD reader; and a request to shut off the DMA enable signal to the DMA mode signal generation unit when MPEG data stored in a memory of the MPEG decoder reaches a predetermined value. To temporarily stop the transmission of the MPEG data to the MPEG decoder by the DVD reader.
When the MPEG data stored in the memory of the decoder is less than a predetermined number, or when a certain time has elapsed since the DVD reader stopped data transmission, the DMA
By requesting the mode signal generator to restore the DMA enable signal, the MPEG data is
Enables transmission via API interface,
An ATAPI interface control circuit, comprising: a data stream control unit that repeats a process of requesting to block and restore the DMA enable signal until data transmission is completed. 2. An MPEG output device arranged between a DVD reader and an MPEG decoder and output from the DVD reader.
The data is transferred to the MPE through an ATAPI interface.
In an ATAPI interface control circuit for performing control for transmission to a G decoder, when a control signal for controlling the DVD reader is given from the MPEG decoder, the control signal is transmitted to the DVD reader, and the control signal is transmitted from the DVD reader to the DVD reader. A control signal transmitting unit for transmitting a response signal to the MPEG decoder when a response signal of the control signal is provided;
When the preparation for the MPEG data transmission in the mode has been completed, the DMA is transmitted via the ATAPI interface.
DMA that enables the DVD reader to transmit MPEG data to the MPEG decoder depending on the mode
A DMA mode signal generation unit for generating an enable signal and transmitting the signal to the ATAPI interface; and, when the MPEG data stored in the memory of the MPEG decoder reaches a predetermined value, the MPEG to the MPEG decoder by the DVD reader. Requesting the DMA mode signal generation unit to shut off the DMA enable signal to temporarily stop data transmission, and when the MPEG data stored in the memory of the MPEG decoder is less than a predetermined number, or when the DVD reader Requesting the DMA mode signal generation unit to restore the DMA enable signal so that MPEG data can be continuously transmitted via the ATAPI interface when a predetermined time has elapsed after stopping data transmission. And the DMA enable signal until the transmission of the MPEG data is completed. An ATAPI interface control circuit, comprising: a data stream control unit that repeats a process of requesting interruption / restoration of the data. 3. A DVD reader, an MPEG decoder,
The MPEG data output from the DVD reader is arranged between the DVD reader and the MPEG decoder.
An ATAPI interface control circuit for controlling transmission to the MPEG decoder via a PI interface, wherein the ATAPI interface control circuit transmits a control signal from the MPEG decoder to the DVD reader, A control signal transmission unit for transmitting a response signal of the control signal from a DVD reader to the MPEG decoder;
By transmitting a DMA enable signal to the ATAPI interface when the preparation of the MPEG data transmission in the mode is completed, transmitting the MPEG data to the MPEG decoder in the DMA mode via the ATAPI interface is performed. A DMA mode signal generation unit for enabling a DVD reader; and a request to shut off the DMA enable signal to the DMA mode signal generation unit when MPEG data stored in a memory of the MPEG decoder reaches a predetermined value. To temporarily stop the transmission of the MPEG data to the MPEG decoder by the DVD reader.
When the MPEG data stored in the memory of the decoder is less than a predetermined number, or when a certain time has elapsed since the DVD reader stopped data transmission, the DMA
By requesting the mode signal generator to restore the DMA enable signal, the MPEG data is
Enables transmission via API interface,
A DVD player comprising: a data stream control unit that repeats a process of requesting to block and restore the DMA enable signal until data transmission is completed. 4. A DVD reader, an MPEG decoder,
The MPEG data output from the DVD reader is arranged between the DVD reader and the MPEG decoder.
An ATAPI interface control circuit for controlling transmission to the MPEG decoder via a PI interface, wherein the ATAPI interface control circuit controls the DVD reader from the MPEG decoder. A control signal transmitting unit that transmits a control signal to the DVD reader when the control signal is supplied, and transmits a control signal response signal to the MPEG decoder when a response signal of the control signal is supplied from the DVD reader; The DVD reader is a DMA
When the preparation for the MPEG data transmission in the mode has been completed, the DMA is transmitted via the ATAPI interface.
DMA that enables the DVD reader to transmit MPEG data to the MPEG decoder depending on the mode
A DMA mode signal generation unit for generating an enable signal and transmitting the signal to the ATAPI interface; and, when the MPEG data stored in the memory of the MPEG decoder reaches a predetermined value, the MPEG to the MPEG decoder by the DVD reader. Requesting the DMA mode signal generation unit to shut off the DMA enable signal to temporarily stop data transmission, and when the MPEG data stored in the memory of the MPEG decoder is less than a predetermined number, or when the DVD reader Requesting the DMA mode signal generation unit to restore the DMA enable signal so that MPEG data can be continuously transmitted via the ATAPI interface when a predetermined time has elapsed after stopping data transmission. And the DMA enable signal until the transmission of the MPEG data is completed. A data stream control unit that repeats a process of requesting interruption and resumption of the DVD player.