JPH0562311B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a logic circuit testing device, and more particularly to a logic circuit testing device with improved means for supplying pattern data for each function of a logic circuit.

(b) Background of the technology Since the logic circuits in manufactured integrated circuits do not necessarily operate as designed, there is a need to test them. Conventionally, test equipment for this type of test has been developed and put into practical use, but when we examine the techniques, we find that there is still room for improvement in the pattern generation method and means of generation. The reality is that there is a need for the development of technical means that can improve this situation.

(c) Prior art and problems As an example of the conventional test equipment of the above-mentioned type,
There is something like the one shown in Figure 1. In this example, the logic circuit under test a consists of three functional blocks a1, a2, a
In this case, circuit a can be divided into three circuits, and test pattern data is stored in pattern memory b to test circuit a. The test pattern data b1 stored in the pattern memory b is the function block a1.
data b2 is for function block a2, and data b3 is for function block a3. The shaded area c1 is the condition setting area for data b1, the shaded area c2 is the condition setting area for data b2, and the shaded area c3 is the condition setting area for data b
3, the non-hatched area d1 contains the same data as the condition setting part c1, the non-shaded part d2 contains the same data as the condition setting part c2,
Also, the non-hatched area d3 stores the same data as the data in the condition setting area c3.

Since the test pattern data stored in this way is configured to be read out from the pattern memory b and supplied to the logic circuit under test a, even if there is only one pin to be tested, the pattern Data for all pins must be stored in memory b, and data for all pins must be created even if only the condition settings are different. Because of this storage mode, the data must be stored for each test pattern, and the data is fixed. Therefore, test patterns that are suitable for each function of the logic circuit under test are being created in such a way that they are impossible to generate while increasing memory usage efficiency.

(d) Purpose of the Invention The present invention was devised in view of the above-mentioned drawbacks of the conventional device, and its purpose is to generate test pattern data for a logic circuit under test by adapting it to its function. At the same time, it is an object of the present invention to provide a logic circuit testing device that can perform this generation while maintaining a high level of efficiency of the generating means.

(E) Structure of the Invention The object is to provide a plurality of pattern generators that generate test pattern data and enable signals for a logic circuit under test, a pattern generation control circuit that operates each of the pattern generators, a first multiplexer that is connected to the plurality of pattern generators and selects an enable signal corresponding to the test pattern data supply target pin; and a first multiplexer that is connected to the plurality of pattern generators and selects a test pattern corresponding to the test pattern data supply target pin. a second multiplexer for selecting data; and a second multiplexer responsive to an enable signal output from the first multiplexer.
The test pattern data output from the multiplexer is supplied to the test pattern data supply target pin, and the test pattern data is compared with the test result data from the output pin of the logic circuit under test corresponding to the test pattern data supply target pin. This is achieved by providing an input waveform control output comparison circuit.

(f) Embodiments of the invention Examples of the invention will be described below with reference to the accompanying drawings.

FIG. 2 shows an embodiment of the invention. P1, P
2, . . . PN are pattern generators, each of which is composed of, for example, a memory, and each generates test pattern data and an enable signal. The pattern generators P1, P2, . . . PN are controlled by a pattern generation control circuit 1. The pattern generators P1, P2, . Reference numeral 2 denotes a selection circuit, which is provided for each pin of the logic circuit under test.
P2,...Multiplexer that selects one of the pattern data under test from all or part of PN
MPX2, a multiplexer MPX that selects the enable signal from the corresponding pattern generator
1, and an input waveform control output comparison circuit 3 that performs waveform processing etc. as in the conventional case. The output of the circuit 3 is connected to the pin of the logic circuit under test assigned to the circuit.

The device of the present invention configured as described above operates as follows.

The pattern generation control circuit 1 operates the pattern generators P1, P2, . . . PN. An enable signal and test pattern data are generated from the operating pattern generator Pi (i is one of 1, 2, . . . N). The enable signal is selected by the multiplexer MPX1, and the test pattern data is selected by the multiplexer MPX2 and supplied to the comparator circuit 3. Only for the enable signal that is on during test execution, a logic signal is applied to that pin and the output is compared. However, the test is performed with the enable signal in the OFF state maintained at its previous state.

Such an operation is generated for each pin, and for each series of test pattern data, the output signals from all or part of the pattern generators P1, P2,...PN are used as described above to control the logic under test. A series of tests are performed on the circuit.

Therefore, a test pattern suitable for the function of the logic circuit under test can be generated and tested. Furthermore, when the pattern generator is configured with a memory, it is sufficient to store only the data necessary for generation by the pattern generator, thereby increasing the efficiency of its use. Furthermore, the present invention is particularly effective when serial test patterns are required.

Although the pattern generation circuit has been described using a memory as an example, it is clear from the above that the pattern generation circuit is not limited to this.

(G) Effects of the invention As described above, according to the present invention, it is possible to generate a pattern that matches the function of the logic circuit under test, and when the pattern generator is configured with memory, it is possible to enjoy the effects ofゝIt is possible to obtain effects such as being able to improve the memory usage efficiency.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing characteristic parts of a conventional device, and FIG. 2 is a diagram showing an embodiment of the present invention. In the figure, 1 is a pattern generation control circuit, P1, P
2,...PN is a pattern generator, and 2 is a selection circuit.

Claims (1)

[Scope of Claims] 1. A plurality of pattern generators that generate test pattern data and enable signals for the logic circuit under test, a pattern generation control circuit that operates each of the pattern generators, and a plurality of pattern generators that operate the pattern generators. a first multiplexer connected to the plurality of pattern generators to select an enable signal corresponding to the test pattern data supply target pin; and a first multiplexer connected to the plurality of pattern generators to select test pattern data corresponding to the test pattern data supply target pin. supplying test pattern data output from the second multiplexer to the test pattern data supply target pin in response to the enable signal output from the first multiplexer; and supplying the test pattern data supply target pin. A logic circuit testing device comprising: an input waveform control output comparison circuit that compares test result data from an output pin of the logic circuit under test corresponding to a pin.