JPH03215765A - Memory testing device - Google Patents

Abstract

PURPOSE:To control the inverted or uninverted state of the polarity of each bit of each pattern signal by providing selecting circuits which select and supply one of polarity control signals outputted by plural polarity control signal generators to polarity switches. CONSTITUTION:The signal selecting circuits 13A - 13N, and 23A - 23N are provided on the respective polarity control signal input sides of the polarity switches 12 and 22 provided on both the supply path 11 for a test pattern signal Tp and the supply path 21 for an expected value pattern signal Kp, and the circuits 13A - 13N and 23A - 23N select and extract one of the N input signals. Further, respective signal sources 41A - 41N of a polarity control signal generator 40 generate the polarity control signals P1 - PN corresponding to the respective bits of a memory 10 to be tested, and an inversion area and a noninversion area are prescribed by the bits of the memory 10 to be tested. Thus, the signal sources 41A - 41N of the generator 40 have patterns of various signals and the memory having inversion areas in various configurations can be tested.

Description

Detailed Description of the Invention: "Industrial Application Field" This invention relates to a memory testing device for testing memories made of semiconductors, and in particular, a memory with an added function suitable for testing memories equipped with a polarity reversal function. The aim is to provide testing equipment.

``Prior Art'' The storage capacity of memories made of semiconductors continues to increase, and is now on a trend of reaching IM bits, 4M bits, and 16M bits.

Various types of failures occur as storage capacity increases. One example of this is the variation in power usage depending on the format of written and successive data. In other words, if all the write and read data is "1" logic data and "1" logic data is written to all storage areas, the amount of current used will increase,
Maximum value.

Furthermore, if "0" is written to all memory cells, then the amount of power used is the minimum.

It is not desirable for the power supply side that the amount of power used fluctuates depending on the format of the data written in this way. Especially when a large number of memory elements are used, this disadvantage is significant.

For this reason, the inside of memory has traditionally been divided into multiple areas,
The logic to be stored in each area is reversed to the opposite logic from the original logic and stored, and when repeated, the logic is returned to the original logic and output.
Memories have been created that can even out power consumption by preventing data logic from being biased.

Such a function will be referred to herein as a polarity reversal function, and a memory having this polarity reversal function will be referred to as a memory with a polarity reversal function.

When testing a memory with a polarity reversal function, there is no need to simply write a test pattern signal to the memory under test, read it out, and test whether the read pattern matches the expected value as in the past. In addition, the polarity of the test pattern signal is inverted in advance on the test equipment side and applied to the storage area where the polarity is inverted and written inside the memory, and by this polarity inversion, other It is required that the memory under test be operated under severe conditions and tested by writing and writing with the same polarity as the storage area.

Such a test can be carried out by modifying the pattern generation program of the pattern generator that generates the test patterns, but modifying the program is labor intensive and troublesome. Furthermore, since the standards of the memory under test are not uniform and the polarity inversion area and non-inversion area are not constant, it is not a good idea to modify the program to match each standard.

For this reason, conventional tests have been configured to have the test equipment recognize the polarity inversion area of the memory under test, and to freely control whether the polarity of the test pattern signal is "inverted" or "not inverted" when accessing the polarity inversion area. The device is being made.

FIG. 3 shows an example. In the figure, 10 is the memory under test, 2
0 is a logic comparator that determines whether the response output signal read from the memory under test 10 matches an expected value;
Reference numeral 30 denotes a pattern generator that provides a test pattern signal Tp to the memory under test 10 and an expected value pattern signal Kp to the logic comparator 20.

The general configuration of a normal test system is pattern generator 3.
0 and a logic comparator 20, the logic comparator 2
The logic signal output to the output terminal 20A of
A defect is determined, and the memory under test 10 is tested.

In order to test a memory with a polarity reversal function, polarity switchers 12 and 22 and a polarity control signal generator 40 are provided in the test pattern signal supply path 11 and the expected value pattern signal supply path 21. The polarity switchers 12 and 22 are connected to the memory under test 10.
The polarity of the test pattern signal Tp given to the test pattern signal Tp and the expected value pattern signal Kp given to the logic comparator 20 is controlled to be switched between a state in which the polarity is inverted and a state in which the polarity is not inverted by a polarity control signal AIH given from the polarity control signal generator 40. . In other words, in this example, when the polarity control signal AIR is 1 logic, all bit signals of the test pattern signal Tp and the expected value pattern signal are inverted in polarity, and the test pattern signal Tp and the expected value pattern signal Kp with the inverted polarity are inverted. It is input to the test memory 10 and the logic comparator 20, and the logic comparator 2
The determination result is output to the output terminal 2OA of 0.

In FIG. 3, the polarity control signal generator 40 applied to the memory under test 10 controls the polarity switchers 12 and 22 to invert the polarity every time the polarity inversion nod area created in the memory under test 10 is accessed. give a signal. For this purpose, an address signal A is given from the pattern generator 30 to the memory under test 10.
R to the polarity control signal generator 40 and the memory under test 10
A test is performed in which the polarity control signal generator 40 outputs a 1-logic polarity control signal each time the polarity inversion area of 2 is accessed, and the 1-logic polarity control signal is applied to the polarity switchers 12 and 22 to be applied to the memory under test 10. The polarity of the pattern signal Tp is inverted, and the polarity of the expected value pattern signal κp supplied to the logic comparator 20 is also inverted, so that the polarities of the logic comparison in the logic comparator 20 match.

"Problems to be Solved by the Invention" Conventionally, polarity switchers 12 and 22 provided in the path 11 for the test pattern signal Tp and the path 2l for the expected value pattern signal Kp are used to switch between the test pattern signal Tp and the expected value pattern signal. It is inserted into the path of all the focus points of κp and the polarity can be inverted depending on the common polarity control signal AIR.
control is being carried out.

According to this conventional configuration, if the inverted area A and the non-inverted area B created in the memory under test 10 are separated in the address direction as shown in FIG. It can operate according to the area and can test the memory under test 10.

However, as shown in FIGS. 5 and 6, there is a disadvantage that it is not possible to test an element in which the inversion region A and the non-inversion region B are separated in the bit direction (a test in which the inversion region is not operated as an inversion region). be.

An object of the present invention is to provide a memory test device that can perform a test even if the inverted regions created in the memory under test 10 are separated in either the address direction or the bit direction.

"Means for Solving the Problem" In the present invention, a test pattern signal is written in the memory under test, the test pattern signal is read out, and the read pattern signal and the expected value pattern signal are compared in a logic comparator, In a memory test device that determines the quality of a memory under test depending on whether a discrepancy is detected in the comparison results, the memory test device is provided in a supply path of a test pattern signal and an expected value pattern signal to be applied to the memory under test and a logic comparator,
A plurality of polarity switchers that separately invert the polarity of the test pattern signal and the expected value pattern signal for each bit as necessary, and a plurality of polarity switchers that provide a polarity control signal that determines whether or not to invert the polarity of the polarity switcher. A memory test device configured by: a control signal generator; and a plurality of signal selection circuits that select any one of the polarity control signals output from the plurality of polarity control signal generators and apply it to the polarity switcher. It is.

According to the configuration of the present invention, a signal selection circuit is provided on each input side of the polarity switch provided in the supply path for both the test pattern signal and the expected value pattern signal to be applied to the memory under test and the logic comparator, and the signal selection circuit The selection circuit can select any polarity control signal output from the plurality of polarity control signal generators and input it to the polarity switch.

Therefore, according to the present invention, since it is possible to control the state of polarity inversion and non-inversion for each bit of each pattern signal, even in a memory where an inversion area and a non-inversion area exist in the bit direction, there are inversion areas and non-inversion areas. It is possible to write the same logic as in the area and perform a test to see if it operates normally.

"Embodiment" FIG. 1 shows an embodiment of the present invention. In Figure 1,
Portions corresponding to those in FIG. 3 are designated by the same reference numerals.

In this invention, the test pattern signal Tp supply path 11
Signal selection circuits 13A to 13N and 23A to 23N are provided on the input sides of the polarity control signals of the polarity switchers l2 and 22 provided on both the supply path 21 of the expected value pattern signal Kp and the expected value pattern signal Kp. These signal selection circuits 13A to 13N and 23A to
23N can be constituted by a so-called multiplexer that selects and takes out one signal from each of N input signals.

On the other hand, the polarity control signal generator 40 includes N signal sources 41A,
41B...41N are provided. These signal sources 41A to 41
N can be constituted by, for example, a memory, and generates a polarity control signal in synchronization with pattern generation of the test pattern signal Tp and the expected value pattern signal Kp.

In other words, each of the signal sources 41A to 41N generates polarity control signals P1 to P. An inversion area A and a non-inversion area B (see FIGS. 5 and 6) are defined for each bit of the memory under test 10.

This situation will be explained using FIG. 2. FIG. 2 shows an example of a polarity control signal used when testing the memory having the inverted region shown in FIG. By switching the signal selection circuits 13A to 13N and 23A to 23N, the signal selection circuit 1
3A and 23A select the signal source 41A, and thereby the signal source 41A generates the polarity control signal for bit BO of the memory under test IO, then the addresses 0, 1, 2 of the memory that constitute the signal source 41A 0 logic, which defines a non-inverted area, is written to address .3, and I logic, which defines an inverted area, is written to addresses 4, 5, and 6.7.

In this way, each signal #41A to #41N is connected to the memory under test 1.
By writing the data defining the inversion area A of each bit b0 to b of 0 as 1 logic, the memory under test 10
A 1-logic polarity control signal can be given to the polarity switch of the bit corresponding to the inversion region A of , and the polarity of the test pattern signal and the expected value pattern signal can be inverted bit by bit using this 1-logic polarity control signal. .

Signal sources 41A to 41N provided in the polarity control signal generator 40
By preparing signal sources with various signal patterns, it is possible to test memories having various types of inverted regions.

"Effects of the Invention" As explained above, according to the present invention, the signal selection circuit 13
By setting the selection states of A to 13N and 23A to 23N, the polarity control signal to be applied to the polarity switchers 12 and 22 can be freely selected for each bit, as shown in FIG. 5 or 6. Even in a memory having the presence or absence of an inversion area in the bit direction, it is possible to write and read data in the inversion area A with the same logic as that written in the non-inversion area B.

Needless to say, the memory testing device according to the present invention can test a memory having no inversion area A in the address direction as shown in FIG. 4, and its operation can be easily understood from the above explanation. I can understand.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the present invention, FIG. 3 is a block diagram for explaining the conventional technique, and FIGS. 6th
The figures are diagrams for explaining various forms of inverted areas and non-inverted areas in a memory. 10...Memory under test, 1l...Test pattern signal supply path, 12.22...Polarity switch, 1 3A to 13
N, 23A to 23N...Signal selection circuit, 20...Logic comparator, 30...Pattern generator, 40...Polarity control signal generator

Claims (1)

[Claims] (1) A. Write the test pattern signal to the memory under test,
A memory test in which the test pattern signal is read out, the read pattern signal and the expected value pattern signal are compared in a logical comparator, and the quality of the memory under test is determined based on whether or not a mismatch is detected in the comparison results. In the apparatus, B is provided in a supply path for a test pattern signal and an expected value pattern signal to be applied to the memory under test and the logic comparator;
a polarity switch that inverts the polarity of the test pattern signal and the expected value pattern signal as necessary; C. a plurality of polarity control signal generators that provide the polarity switch with polarity control signals that determine whether or not to invert the polarity; D. A selection circuit for selecting any one of the polarity control signals outputted from the plurality of polarity control signal generators and applying it to the polarity switch.