JPH0561640A - Speed converter - Google Patents

Abstract

PURPOSE:To read out correct data without overwriting a data input longer than the memory capacity of a storage cell. CONSTITUTION:This speed converter is provided with the storage cell 11 for writing/reading out input data, a pulse generating circuit 1 for generating an output pulse signal with plural phases satisfying a certain range for the combination of an input data length and the speed ratio of a reading clock signal to a writing clock signal, a phase selecting circuit 2 for selecting an output pulse signal with a certain phase based upon an output from the circuit 1, a write address counter 10 to be reset by a write resetting signal, counted up by a writing clock signal to apply an address to the specified storage cell 11 and recounted at the time of full counting, and an address counter 12 to be reset by a reset signal based upon an output from the circuit 2, counted up by a reading clock signal to apply an address to the specified storage cell 11 and recount addresses at the time of full counting.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speed conversion circuit, and more particularly to a speed conversion circuit using an elastic store memory.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional example. The speed conversion circuit using the elastic store memory shown in FIG. 3 is reset by the write reset signal d, and the write clock signal c is reset.
The write address counter 10 which counts up from the address 0 by giving an address to the specified store cell 11 and recounts from the address 0 when full count is performed, and the read reset signal h resets the address 0 from the address 0. A read address counter 12 that counts up and gives an address to a specified store cell 11 and performs a full count again at address 0, and a read address counter 12 that has a capacity longer than the input data length for writing and reading input data e at a specified address And a store cell 11.

Next, the operation of the above conventional example will be described.

1) A write reset signal d is input to the write address counter 10 to reset the write address counter 10.

2) The write clock signal c is input to the write address counter 10.

3) The write address counter 10 gives the address of address 0 to the store cell 11.

4) The store cell 11 takes in the input data e and writes it at the address 0.

5) Further, when the write clock signal c is input, the write address counter 10 is automatically incremented by +1 to give the +1 address to the store cell 11.

6) The store cell 11 takes in the next input data e and writes it at the address given by the write address counter 10.

After 7), 5) and 6) are repeated until all the input data e are written in the store cell 11.

8) The read reset signal h is input to the read address counter 12 to reset the read address counter 12.

9) A read clock signal f having a speed different from that of the write clock signal c is input to the read address counter 12.

10) The read address counter 12 gives the address of address 0 to the store cell 11.

11) The store cell 11 takes out the data from the address 0 and uses it as the output data g.

12) Further, when the read clock signal f is input, the read address counter 12 is automatically incremented by +1 to give the +1 address to the store cell 11.

13) The store cell 11 takes out the data from the given address and uses it as the output data g.

After 14), (12) and (13) are repeated until all write data is output.

As described above, in the conventional speed conversion circuit, speed conversion is performed by making the speeds of the write clock signal c and the read clock signal f different.

[0019]

However, in the above-mentioned conventional example, since the write address counter recounts from the address 0 after the full count,
When data longer than the memory capacity of the store cell is input, there is a disadvantage that the data is destroyed by overwriting the same address.

[0020]

SUMMARY OF THE INVENTION The object of the present invention is to improve the inconvenience of the conventional example, and in particular, even if data longer than the memory capacity of the store cell is input, correct data can be read out without overwriting the same address. It is to provide a speed conversion circuit.

[0021]

Therefore, in the present invention, a store cell for writing and reading input data at a designated address and a write reset signal sent at the same timing as the input data are used as input triggers. A pulse generation circuit that operates and generates an output pulse signal of a plurality of phases that satisfies a certain range for a combination of the data length of input data and the speed ratio of a read clock signal and a write clock signal, and a pulse generation circuit based on the output of this pulse generation circuit And a phase selection circuit for selecting an output pulse signal of a certain specific phase. Then, it is reset by the write reset signal and the address 0 by the write clock signal.
Equipped with a write address counter that counts up from an address, gives an address to a specified store cell, and recounts from address 0 when full count
It is equipped with a read address counter that is reset by a read reset signal from the phase selection circuit, counts up from address 0 by a read clock signal to give an address to a specified store cell, and recounts from address 0 when full count is performed. The composition is adopted. This aims to achieve the above-mentioned object.

[0022]

When the write reset signal is input, the write address counter is reset and the pulse generation circuit is activated at the same time. When the write clock signal is input to the write address counter, the write address counter gives the address of address 0 to the store cell. Then, the store cell fetches the input data and writes it at the address 0. When the write clock signal is further input, the write address counter will automatically
The address which has been incremented by 1 is given to the store cell by +1. Then, the store cell fetches the next input data and writes it at the address given by the write address counter. In the pulse generation circuit, in parallel with the above-described write processing to the store cell, output pulse signals of a plurality of phases satisfying a specific range are based on the combination of the data length of the input data and the speed ratio of the read clock signal and the write clock signal. Occur.

Then, one of the plurality of pulse signals output from the pulse generation circuit is selected by the phase selection circuit. When the selected pulse signal is input to the reset of the read address counter as the read reset signal from the phase selection circuit, the read address counter is reset. At the same time, the read reset signal is input to the frame aligner as a frame aligner write reset signal and the frame aligner is reset.

When the read clock signal is input to the read address counter, the read address counter gives the address of address 0 to the store cell. The store cell fetches data from the address 0 and outputs it to the frame aligner. Further, when the read clock signal is input, the read address counter is automatically incremented by +1 to give the +1 address to the store cell. Then, the store cell extracts the data from the given address and outputs it to the frame aligner. When the frame aligner read reset signal is sent to the frame aligner, the phase of the data output from the frame aligner is set. When the read clock signal is input to the frame aligner, the speed-changed data is output from the frame aligner as output data. The above operation is continued until there is no input data.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

In the embodiment shown in FIG. 1, a store cell 11 having a capacity of N bits for writing and reading the input data e at a designated address, and a data length M and a read of the input data e by using a write reset signal d as an input trigger. The pulse generation circuit 1 is composed of a mono-multivibrator group that generates output pulse signals of a plurality of phases that satisfy a certain range for a combination of the speed ratio k of the clock signal f and the write clock signal c, and is output from the pulse generation circuit 1. And a phase selection circuit 2 for selecting an output pulse signal of a specific phase from output pulse signals of a plurality of phases. Also, a write address counter 10 which is reset by a write reset signal d, counts up from address 0 by a write clock signal c, gives an address to a designated store cell 11 and, when full count is performed, re-counts from address 0, and a phase selection circuit. A read address counter 12 that is reset by the read reset signal h from 2 and counts up from the address 0 by the read clock signal f, gives an address to the designated store cell 11 and recounts from the address 0 when full count The frame aligner 3 has a write phase set by a reset signal h, an output phase set by a frame aligner read reset signal a, and operates by a read clock signal f.

Next, the operation of this embodiment will be described.

Here, the write speed is W, the read speed is R, the input data length is M bits, the memory capacity is N bits, the speed ratio between the read clock signal and the write clock signal is k (k = R / W), and the input The write time of the data M bits is tw (tw = M / W), the read time of the input data M bits is tr (tr = M / R), and the time difference between the write reset signal and the read reset signal is t0.

1) When the write reset signal d is input, the write address counter 10 is reset and at the same time the pulse generation circuit 1 is activated.

2) The write clock signal c is input to the write address counter 10.

3) The write address counter 10 gives the address of address 0 to the store cell 11.

4) Then, the store cell 11 takes in the input data e and writes it at the address 0.

5) Further, when the write clock signal c is input, the write address counter 10 is automatically incremented by +1 to give the +1 address to the store cell 11.

6) Then, the store cell 11 takes in the next input data e and writes it at the address given from the write address counter 10.

7) The pulse generation circuit 1 performs the following processes in parallel with 2) to 6).

8) For a combination of the data length M (bits) of the input data e and the speed ratio k of the read clock signal f and the write clock signal c, output pulse signals of a plurality of phases satisfying the following ranges are generated. ..

(A) As shown in FIG. 2A, R>
When W, the condition of t0 is N / W>t0> tw-tr (1) That is, N / W>t0> M (1 / W-1 / R) (2)

In equation (2), when t0 is represented by the number of write clocks Wt0, the above equation (2) is: N>Wt0> M (1-W / R) (3) In this equation (3), W / When R is replaced by the clock ratio k, N>Wt0> M (1-k) (4).

(B) As shown in FIG. 2B, W>
When R, the condition of t0 is t0 + (M−N) / R <tw (5) At this time, t0> 0 (6)

From equations (5) and (6), 0 <t0 <M / W- (MN) / R (7) In equation (7), when t0 is represented by the number of write clocks Wt0, 0 <Wt0 <M- (MN) W / R (8) In the equation (8), if W / R is replaced by the clock ratio k, then 0 <Wt0 <M- (MN) / k (9). That is, the phase of the pulse signal output from the pulse generation circuit 1 from the above (A) and (B) is measured by the write clock from the write reset signal d (1-1 /
k) Mth (however, 0th when (1-1 / k) M <0) to {M− (M−N) / k} th (however, M− (M
When -N) / k> N, it is the Nth range.

9) Then, one of the plurality of pulse signals output from the pulse generation circuit 1 is selected by the phase selection circuit 2.

10) When the selected pulse signal is input to the reset of the read address counter 12 as the read reset signal h from the phase selection circuit 2, the read address counter 12 is reset. At the same time, the read reset signal h is input to the frame aligner 3 as the frame aligner write reset signal b, and the frame aligner 3 is reset.

11) When the read clock signal f is input to the read address counter 12, the read address counter 12 gives the address of address 0 to the store cell 11.

12) The store cell 11 takes out data from the address 0 and outputs it to the frame aligner 3.

13) Further, when the read clock signal f is input, the read address counter 12 is automatically incremented by +1 to give the +1 address to the store cell 11.

14) Then, the store cell 11 takes out the data from the given address and outputs it to the frame aligner 3.

15) The phase of the data read from the store cell 11 is determined by the read reset phase,
Since the phase may be different from the originally required phase, the frame aligner read reset signal a
To set the phase of the data output from the frame aligner.

16) When the read clock signal f is input to the frame aligner 3, speed-changed data is output from the frame aligner 3 as output data g.

The above operation is continued until there is no input data.

That is, in the present invention, data is stored in the storage cell 1
While writing to 1, the speed is converted from the store cell 11 and reading is performed.

[0051]

Since the present invention is constructed and functions as described above, according to the present invention, a plurality of read reset signals are generated within a specific phase range, and the phase selection circuit reads and resets the optimum phase for the input data length. By selecting a signal, speed conversion is possible even with a memory capacity that is less than the input data length. Furthermore, when a frame aligner is added, the data read from the store cell can be converted into a required phase. Therefore, the speed conversion can be performed without considering the input data length, the memory can be effectively used, and the degree of freedom of the speed conversion can be widened, thereby providing an unprecedented excellent speed conversion circuit. be able to.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

2 to 3 are timing charts of the pulse generation circuit of FIG.

FIG. 4 is a configuration diagram showing a conventional example.

[Explanation of symbols]

 1 pulse generation circuit 2 phase selection circuit 3 frame aligner 10 write address counter 11 store cell 12 read address counter a frame aligner read reset signal b frame aligner write reset signal c write clock signal d write reset signal e input data f read clock signal g Output data h Read reset signal

Claims (2)

[Claims] 1. A store cell for writing / reading input data at a specified address, and a write reset signal sent at the same timing as the input data to act as an input trigger to set the data length of the input data and A pulse generation circuit that generates an output pulse signal of a plurality of phases that satisfies a certain range for a combination of speed ratios of a read clock signal and a write clock signal, and an output pulse of a certain specific phase based on the output of this pulse generation circuit A phase selection circuit for selecting a signal is provided, which is reset by the write reset signal, counts up from address 0 by a write clock signal to give an address to a specified store cell, and when full count is performed, re-counts from address 0. Equipped with a write address counter to A read address counter is provided, which is reset by a read reset signal from the phase selection circuit, counts up from address 0 by a read clock signal to give an address to a specified store cell, and recounts from address 0 when full count is performed. A speed conversion device characterized by the above. 2. A write phase is set by a read reset signal from the phase selection circuit, an output phase is set by a frame aligner read reset signal from the outside, and an operation is performed by the read clock signal at the output stage of the store cell. The speed conversion device according to claim 1, further comprising a frame aligner for starting phase conversion.