JP2740350B2 - Timer correction circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a correction circuit, and more particularly, to a timer correction circuit for correcting a delay when data is set in a timer.

[Conventional technology]

Conventionally, to compensate for the delay when setting data to this type of timer, the delay due to the transfer of data to be set is calculated in advance, and this delay is added to the data to be set. Is set in the timer, or if a delay occurs due to the transfer of data to be set, the data is set in the timer two or more times, the time difference per time is calculated, and the difference is added to the timer as the delay. The correction was performed by this.

[Problems to be solved by the invention]

The above-described conventional timer correction circuit calculates the delay amount calculated in advance or the time required for data setting to the timer per one time by continuously performing data setting to the timer two or more times. Since the delay is added to the timer, when the data to be set is transferred via the bus, it is not always possible to use the bus immediately. There is a drawback that a difference occurs between the delay and the delay, and there is a case where the correction is not appropriate.

[Means for solving the problem]

A timer correction circuit according to the present invention transfers time data of a first (or second) timer unit to a second (or first) timer unit. A counter for performing a count operation in synchronization with a clock of the timer based on a start instruction signal; and a memory unit for latching time data of the first (or second) timer unit based on the timer correction start instruction signal. A write circuit for adding the output of the counter and the output of the memory unit based on a write instruction signal and writing the added value to the timer;
A timer control circuit for generating a count end and reset instruction to the counter, a timer correction start instruction signal, and the write instruction signal is provided.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram including an embodiment of the present invention.

1a is a counter for timer correction, 2a is a writing circuit for adding the data to be written to the timer and the value of the counter 1a and writing the result to the timer, 3a is a timer having a time counting or clock function, and 4a is a timer 3a A reading circuit for reading a value from the counter 5a;
Each output of a count end instruction 52a, a counter reset instruction 53a, a write instruction 54a to the timer 3a, a count instruction 55a of the timer 3a, a respective output of a read instruction 56a from the timer 3a,
Furthermore, a timer control circuit for receiving a timer correction start instruction 6 from another unit and outputting a timer correction start instruction 7 to another unit, 8 is a clock signal, 9 is a timer
A bus for transmitting and receiving write data and the like to and from 3a, and 10 is a memory unit.

In this embodiment, it is assumed that the timer unit A20 includes the above-described counter 1a, write circuit 2a, timer 3a, read circuit 4a, and timer control circuit 5a.

Then, like timer unit A20, timer unit B
30 is a counter 1b, a write circuit 2b, a timer 3b, a read circuit
4b, a timer control circuit 5b (both are not shown), and a timer value can be transmitted and received via the bus 9 and the memory unit 10.

Next, the operation of the present invention will be described using a time chart.

FIG. 2 is a time chart when data is set from the timer unit B30 to the timer unit A20.

The timer 3b of the timer unit B30 is sequentially counted from "5" to "13" at the rising edge of the clock 8 between the stages S1 to S9. At stage S2, timer correction start instruction 6 is output from timer unit B30 to timer unit A20.

Then, the timer control circuit 5a generates a count start instruction 51a from the timer correction start instruction 6, and outputs the count start instruction 51a to the counter 1a.

The counter 1a sequentially starts counting at the rising edge of the clock 8 according to the count start instruction 51a. At stage S3, the value "7" of the timer 3b is output from the read circuit 4b of the timer unit B to the bus 9 and written into the memory unit 10.

At this time, the timer 3b is already "8". Also,
The counter 1a of the timer unit A20 is "2".

Next, at stage S6, data "7" to be written to the timer 3a is read from the memory unit 10 and stored in the register 21a in the write circuit 2a. At the stage S7, the counter 1a and the register 21a are added by the write instruction 54a, and the result “12” is obtained.
Is stored in the timer 3a.

The value of each timer in stage S8 is both "12".
Note that the read timing of the timer value, the storage in the memory unit, and the read timing from the memory unit are not necessarily limited to the timing chart.

〔The invention's effect〕

As described above, the present invention has a counter for timer correction, counts the time for transferring data to be set to the timer, and adds the data to be written and the value of the counter when writing data to the timer. However, by writing the result to the timer, there is an effect that correction at the time of data setting to the timer can be accurately performed.

[Brief description of the drawings]

FIG. 1 is a block diagram including an embodiment of the present invention, and FIG. 2 is a time chart when a timer value is set from a timer unit B to a timer unit A shown in FIG. 1a, 1b: Counter, 2a, 2b: Write circuit, 21a, 21b:
… Register, 3a, 3b …… timer, 4a, 4b …… readout circuit,
5a, 5b ... timer control circuit, 51a, 51b ... count start instruction, 52a, 52b ... count end instruction, 53a, 53b ... counter reset instruction, 54a, 54b ... timer write instruction, 5
5a, 55b: Timer count instruction, 56a, 56b: Read instruction from timer, 6, 7: Timer correction start instruction, 8:
... clock, 9 ... bus, 10 ... memory unit.

Claims (1)

(57) [Claims] 1. A timer for transferring time data of a first (or second) timer unit to a second (or first) timer unit, wherein the timer performs time counting and the like.
A counter for performing a count operation in synchronization with a clock of the timer based on a timer correction start instruction signal, and a memory for latching time data of the first (or second) timer unit based on the timer correction start instruction signal A unit, a write circuit for adding the output of the counter and the output of the memory unit based on a write instruction signal, and writing the added value to the timer; a count end / reset instruction to the counter; And a timer control circuit for generating the write instruction signal.