JPH01238343A - Buffer memory - Google Patents

Abstract

PURPOSE:To obtain a buffer memory suitable for LSI and high speed processing by using a phase synchronizing circuit so as to compare the phase between a write side reference pulse and a readout side window pulse and specifying the readout phase with respect to the write side phase so as to apply phase locking. CONSTITUTION:A phase locking circuit 14 uses the 1st ring counter 11 to apply phase comparison between the 1st phase write pulse output and the window pulse and when the reference pulse is at the outside of the window pulse in an event such as at application of power or signal input interruption, the 2nd ring counter 13 receives a reset pulse to reset the count to '0' and the count is restarted from the start. Thus, the write phase fluctuation due to CRL (subscriber clock 1) jitter is absorbed by the window pulse in the range of '1'. As a result, a parallel/serial converter 15 always outputs accurate readout data DRLP.

Description

[Detailed Description of the Invention] [Summary] Regarding a buffer memory for writing and reading transmitted data, the present invention aims to realize a buffer memory that is suitable for L,SI (collection fP1) and is suitable for high speed. , a first ring counter that receives subscriber clock 1, a serial-to-parallel converter that converts subscriber data into parallel data based on the output of the first ring counter, and performs jitter suppression processing on subscriber clock 1. The second ring counter receives the subscriber clock 2, the reference pulse from the Makki serial-to-parallel converter, and the wind pulse from the second ring counter, and the phases are compared, and the phase difference is determined by a predetermined m. an interphase IIIJ conversion circuit that outputs a reset pulse to the second ring counter when the value exceeds Configure.

[Industrial Application Field] The present invention relates to a buffer memory for storing and reading transmitted data.

BACKGROUND ART Conventionally, in the field of data transmission, buffer memories have been used to absorb the difference between the speed of transmitted data and the processing speed of a receiving device. in this case,
Since the write-side clock for storing data and the read-side clock for reading data are asynchronous, adjustment between these clocks is required.

[Conventional technology] FIG. 5 is a diagram without showing an example of the configuration of a conventional circuit.

In the figure, 1 is an elastic memory in which subscriber data (input data) Di is temporarily written and read, and 2 is an elastic memory in which subscriber data (input data) Di is temporarily written and read. The write-side address counter 3 is a first decoder that decodes the output of the write-side address counter 2. The subscriber clock 1 is inputted to the elastic memory 1 as a read clock (write clock) WC, and a write reset pulse WR defining the initial phase for writing is inputted from the decoder 3.

4 is a read-side address counter that counts the subscriber clock 2 obtained by applying jitter suppression processing to the subscriber clock 1 and generates an address at the time of reading; 5 is a second address counter that decodes the output of the subsequent-side address counter 4; This is a decoder. 6 compares the phase of the write-side phase comparison signal output w-pc of the first decoder 3 and the read-side phase comparison signal output R/PC of the second decoder 5, and when the phase difference exceeds a predetermined tooth, the output is continued. This is a phase comparison circuit that outputs a reset pulse to the side address counter 4. The subscriber clock 2 is input to the elastic memory 1 as a read clock (read clock > RC), and a read reset pulse RR that also defines the initial phase to be read to the elastic memory 1 is input from the second decoder 5. Then, read data output D from elastic memory 1
o is output.

FIG. 6 is a timing chart showing the operation of each part of the circuit shown in FIG. The subscriber data D1 shown in (a) is written into the elastic memory 1 by the write clock WC, with the initial phase defined by the write reset pulse Wπ, and the written data is written by the read reset pulse RR delayed from that. The initial phase of reading is defined by , and the readout is performed using a readout clock that is asynchronous with the write clock WC, resulting in a data output Do. In this case, the phase comparison circuit 6 compares the write side phase comparison signal output w-pc of the first decoder 3 and the read side phase comparison signal output R-PC of the second decoder 5. In this case, if there is a certain time difference between w-pc and R.PC as shown in (c) and (d), no reset pulse is generated and normal writing and reading are performed.

However, as shown in (c) and (g), when the time difference (phase difference) between the two approaches, the problem arises that data is read before data is written. Continuous address counter 4 from 6
A pulse is output as shown in (h) to reset the reading side and restart reading from the beginning. By performing such control, normal successive data as shown in (f) is output.

[WJI problem to be solved by the invention] In the conventional circuit as shown in FIG. 5, when the time difference (phase difference) between the writing side and the reading side disappears, the reading side is reset and the reading is performed again. In this way, correct data is output. however,
Conventional circuits like this use elastic memory for data storage and directly compare write reset pulses and read reset pulses, resulting in large circuit scale and unsuitability for high speeds. there were.

The present invention has been made in view of these points, and
It is an object of the present invention to provide a buffer memory suitable for LSI (integration) and high speed.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. In the figure,
11 is a first ring counter that receives subscriber clock 1; 12 is a serial-to-parallel converter that converts subscriber data into parallel data based on the output of first ring counter 11; and 13 is a serial-to-parallel converter that converts subscriber clock 1 into parallel data. This is a second ring counter that receives subscriber clock 2 that has been subjected to suppression processing. 14 is the serial/parallel converter 12
reference pulse from the second ring counter 1
A phase comparison is performed upon receiving the wind pulse from the second ring counter 13, and when the phase difference exceeds a predetermined amount, the second ring counter 13
15 is a parallel/serial converter that converts the output of the serial/parallel conversion 'a12 into serial data using the output of the second ring counter 13. And the parallel
The output of the serial converter 15 becomes the readout output.

[Operation] The phase synchronization circuit 14 is used to compare the phases of the reference pulse on the writing side and the wind pulse on the reading side, define the reading side phase with respect to the writing side phase, and perform phase synchronization. Further, by using a ring counter as a read-in counter and a read counter, a buffer memory that can be operated at high speed and has a simple configuration can be realized.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. Components that are the same as those in FIG. 1 are designated by the same reference numerals. In the figure, the phase synchronization circuit 14 receives the signal input interruption information @
(XiDN) and power-on reset signal @ (XPOR
) receiving gate (31, set/reset latch 14
a, gates G2, G3 and delay circuit (DLY) 14
It is composed of b. The output of the gate G1 enters one input of the set/reset latch 14a, the output of the set/reset latch 14a enters one input of the gate G2, the output of the gate G2 enters one input of the gate G3, The output of the gate G3 goes into the delay circuit 14b, and the output of the delay circuit 14b goes into the set/reset latch 1.
It is in the other input of 4a. The gate G2. G3 functions as a phase comparison section that compares the phases of the reference pulse and the wind pulse. Reference numeral 16 denotes a flip-flop which receives subscriber data DRL at its D input and receives subscriber clock CRL at its clock input C. The output of the flip-flop 16 enters a serial-to-parallel converter 12. Here, a case where the frequency division ratio n of the ring counters 11.13 is 24 is taken as an example. The operation of the circuit configured as described above will be explained below with reference to the timing chart shown in FIG.

The subscriber data DRL enters the flip-flop 16 and is synchronized with the subscriber clock 1, and then enters the serial/parallel converter 12 as serial data. On the other hand, the subscriber clock (write clock) 1 containing a jitter component enters the first ring counter 11 on the write side as a counter clock. As a result, the first ring counter 1
1 performs 1/n frequency division (n~24), and the third
As shown in the figure (a), n-phase (24-phase) parallel pulses are output and input to the serial-parallel converter 12. The serial-to-parallel converter 12 converts the subscriber data sent from the flip-flop 16 based on the parallel pulse output of the first ring counter 11 into the form shown in FIG.
Convert to parallel data as shown in b).

On the other hand, the subscriber clock 2 whose jitter is suppressed by PLO etc.
enters the second ring counter 13, and the second ring counter 13 performs frequency division by 1/n.

A frequency-divided pulse as shown in FIG. 3(C) is output as the output, and is applied to the parallel-to-serial converter 15 as a read pulse. In addition, a window (e) as shown in (e) of m-bit width < m + 1 < n created by this frequency division operation (
WINDOW) pulse (for the first phase readout pulse ■ shown in Figure 3 (c), the center phase of WINDOW is
It's in a different position. ) is input to the phase synchronization circuit 14.

Here, the phase synchronization circuit 14 outputs the first phase write pulse (the third phase) generated by the first ring counter 11.
Figure 3 (
Reference pulse (Refpu I) as shown in (d)
se) and the above-mentioned wind pulse.
0) If the reference pulse is outside the range of the wind pulse, a reset pulse (XCLR) is output to the second ring counter 13, and the count value is
Reset (initialize) to restart counting from the beginning.

The second ring counter 13 that received this reset pulse
creates a wind pulse at the timing of the next subscriber clock 2, sets the wind pulse to '0'' after m72 bits as shown in Figure 3 (e), and the reference pulse shown in (d) becomes the wind pulse. With this setting, the phase fluctuation due to jitter of CRL (subscriber clock 1) can be absorbed within the range (±m/2) of the wind pulse II 1 H. As a result, the parallel-to-serial converter 15 always outputs accurate read data DI'' (LP).

In addition, a predetermined delay tooth is created by the reset pulse generation delay circuit 14b, and a phase information latch circuit (set/delay circuit 14b) is used.
Since the reset latch 14a) is reset, the width of this reset pulse depends on the delay range of the delay circuit 14b.

FIG. 4 is a timing chart showing the operation of the phase synchronization circuit 14. Figure 4 (a) shows the power-on reset, Figure 4 (b) shows the reference pulse between the wind pulses (normal operation), and Figure 5 (c) shows the reference pulse between the wind pulses. Each shows a time when it fell out of line. In the event of an abnormality as shown in Figures 4(a) and 4(c), a reset pulse I know that there is. The reset pulse that actually enters the phase information latch section 14a is delayed by the delay circuit 14b, and as a result, it is generated slightly later than XCLR.
2 to 2t in the figure show waveforms at the illustrated positions in the phase synchronization circuit 14 in FIG. 2.

[Effects of the Invention] As described above in detail, the present invention uses the phase synchronization circuit 14 to compare the phases of the reference pulse on the write side and the wind pulse on the read side, and compares the phase of the read side with respect to the input side phase. In addition, by using a ring counter in the memory section, it is possible to increase the speed and eliminate the need for elastic memory, making it possible to realize a buffer memory with a simple configuration. can. Therefore, according to the present invention, LSI (i product)
Accordingly, it is possible to realize a buffer memory suitable for speeding up and speeding up.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a configuration block diagram showing an embodiment of the invention, Fig. 3 is a timing chart showing the operation of each part, and Fig. 4 is the operation of the phase synchronization circuit. 5 is a diagram showing an example of the configuration of a conventional circuit, and FIG. 6 is a timing chart showing the operation of each part. In FIG. 1, J3 includes: 11 a first ring counter, 12 a serial/parallel converter, 13 a second ring counter, 14 a phase synchronization circuit, and 15 a parallel/serial converter.

Claims (1)

[Claims] A first ring counter (11
), a serial-to-parallel converter (12) that converts subscriber data into parallel data based on the output of the first ring counter (11), and a subscriber clock 2 which is subjected to jitter suppression processing on the subscriber clock 1. A second ring counter (13) receives the reference pulse from the serial/parallel converter (12) and a wind pulse from the second ring counter (13), performs a phase comparison, and calculates the phase difference. a phase synchronization circuit (14) that outputs a reset pulse to the second ring counter (13) when the value exceeds a predetermined amount; A buffer memory composed of a parallel/serial converter (15) that converts the output into serial data.