JPH07200095A - Data transfer circuit - Google Patents

Abstract

PURPOSE:To enable transfer without errors between different clocks by evading transfer errors due to the difference of frequencies between two clocks and the transfer errors due to the difference of phases by separately adjusting timings. CONSTITUTION:Data outputted from a synchronous circuit 38 operated by the clock A are transferred to the synchronous circuit 26 operated by the clock B of the frequency f2 satisfying the condition of f1>=f2>=0 (Hz) to the frequency f1 of the clock A. In this case, the data from the synchronous circuit 38 are adjusted by a timing adjusting means 52 so as to prevent the transfer error due to the difference of the frequencies of the clocks A and B. Also, the timing adjusting means 56 controls the input to the synchronous circuit 26 of the data outputted from the synchronous circuit 38 so as to prevent the transfer error due to the difference of the phases of the clocks A and B. Thus, data transfer between the different clocks A and B is performed without the errors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a data transfer circuit that transfers data with different clocks.

[0002]

2. Description of the Related Art Conventionally, when data is transferred and received at different clocks, a FIFO (First In First Out) is generally used.
Memory is used. FIG. 7 shows its main configuration. The FIFO memory 100 includes a RAM 102,
It includes counters 104 and 106. The clock A of the input data of the RAM 102 is input to the counter 104,
The clock B of the output data of the RAM 102 is the counter 10
6 is input. And counter 1
Reference numeral 04 is connected to the write address input side of the RAM 102, and the counter 106 is connected to the read address input side.

Next, the operation will be described. The counter 104
In, the write address is generated by counting the clock A of the input data. In the RAM 102, data is input on one side and a write address is input from the counter 104, so that the input data is sequentially stored at the address of the RAM 102 designated by the write address.

On the other hand, the counter 106 counts the clock B of the output data and generates a read address.
In the RAM 102, since the read address is input from the counter 106, the data is sequentially output from the address of the RAM 102 designated by this read address.
This data output is performed in the order of data input to the RAM 102. In this way, the clock is converted from A to the asynchronous clock B and the data is transferred. As described above, conventionally, data transfer by an asynchronous clock is performed using a 2-port type RAM having 1 input port and 1 output port.

[0005]

However, the above conventional techniques have the following disadvantages. The two-port RAM generally has a large circuit area, and such an inconvenience becomes remarkable especially when the circuit is to be realized on the gate array. The clock of the circuit is changed between the input side and the output side, and in some cases a large change in the peripheral circuit configuration is required, which is not always convenient for using the peripheral circuit technology.

The present invention focuses on these points,
It is an object of the present invention to provide a data transfer circuit which can perform data transfer between different clocks without an error without using a 2-port RAM and is suitable for application to various circuits.

[0007]

In order to achieve the above-mentioned object, the present invention provides a first clock operated based on a first clock.
The data output from the second device is transferred to the second device operating based on the second clock having the frequency f2 satisfying the condition of f1 ≧ f2> 0 (Hz) with respect to the frequency f1 of the first clock. In the data transfer circuit, a first timing adjusting means for controlling data output from the first device in order to prevent a transfer error caused by a difference in frequency of the first and second clocks; And second timing adjusting means for controlling the input of the data output from the first device to the second device in order to prevent a transfer error caused by the phase difference of the second clock. Is characterized by.

[0008]

According to the present invention, in order to prevent the occurrence of a transfer error due to the difference between the frequencies of the first and second clocks, the data output from the first device on the data output side is controlled. This control is a control for adjusting the data output of the higher frequency to the lower frequency. Next, in order to prevent the occurrence of a transfer error due to the phase difference between the first and second clocks, the input of the data output from the first device to the second device is controlled. This control is
This is a timing control that accompanies the phase of the clock pulse changing every moment.

[0009]

Embodiments of the data transfer circuit according to the present invention will be described below in detail with reference to the accompanying drawings. <First Embodiment> FIG. 1 shows the main configuration of the first embodiment. In the figure, the input terminal T1 of the clock B
Is a latch circuit 10, 12, 14, 16, 18, 20,
It is connected to a pulse circuit 22, a counter 24, and a synchronization circuit 26, each of which is composed of a monostable multivibrator (one-shot multivibrator). Also,
The input terminal T2 of the clock A has latch circuits 30, 32,
34, 36, synchronization circuit 38, latch circuit 4 with enable
0, 42, 44, 46, respectively. An input terminal T3 of a transfer signal SP, which is a signal for instructing data transfer and which is synchronized with the clock B, is connected to one input side of the EXOR gate 50 in addition to the latch circuit 14.

Next, the output side of the latch circuit 10 is EXOR
This EX is connected to the other input side of the gate 50.
The output side of the OR gate 50 is connected to the input sides of the latch circuits 10 and 12, respectively. In addition, the latch circuit 12
The output side of the pulse circuit 22 is connected to the input sides of the latch circuits 30 and 32, and the output side of the pulse circuit 22 is connected to the latch circuit 3.
4 is connected to the input side. These latch circuits 30,
The output sides of 32 and 34 are connected to the multiplexer 52, respectively.

Next, the output side of the multiplexer 52 is connected to the input side of the latch circuit 36 and one input side of the EXOR gate 54, respectively.
The output side of 6 is connected to the other input side of the EXOR gate 54. The output side of the EXOR gate 54 is connected to the synchronizing circuit 38. The data output side of the synchronizing circuit 38 is connected to the input sides of the latch circuits 40, 42, 44 and 46 respectively, and the enable signal output side of the synchronizing circuit 38 is the enable terminal side of the latch circuits 40, 42, 44 and 46. Respectively connected to. And
The output sides of the latch circuits 40, 42, 44 and 46 are connected to the input side of the multiplexer 56, respectively.

On the other hand, on the output side of the latch circuit 14, latch circuits 16 and 18 are connected in series.
The output side of 8 is connected to a counter 24. And
The output side of the counter 24 is the multiplexer 56.
Connected to the control side of. The output side of the multiplexer 56 is connected to the latch circuit 20, and the output side of the latch circuit 20 is connected to the synchronizing circuit 26.

Next, each component will be described with reference to the time chart of FIG. In this embodiment, FIG.
As shown in (A) and (B) as an example, the frequencies f1 and f2 of the clocks A and B satisfy the condition of f1 ≧ f2> 0 (Hz) .......... (1) . Latch circuit 10, 12, EXO
The R gate 50 is for obtaining the signal SA shown in FIG. 9D based on the clock B and the transfer signal SP shown in FIG. The signal SA is a signal which changes periodically during the period of the logical value "H" of the transfer signal SP to represent enable.

The pulse circuit 22 is for outputting a pulse at the rising timing of the clock B. The latch circuit 30 receives the signal S at the rising timing of the clock A.
The latch circuit 32 has a function of latching A, and the latch circuit 32 has a function of latching the signal SA at the falling timing of the clock A. Further, the latch circuit 34 uses the clock A
Has a function of latching the output of the pulse circuit 22 at the rising edge of. The multiplexer 52 has a function of selecting one of the outputs of the latch circuits 30 and 32 in accordance with the output of the latch circuit 34 and outputting it as a signal SB shown in FIG.

In other words, when the logical value "H" is output from the latch circuit 34, the rising edges of the clocks A and B are close to each other, and the latch circuit 34 outputs the clock signal A,
It can be considered to have a function of detecting the proximity state of the rising timing of B. Then, according to the detection result, the output of the latch circuits 30 and 32 is selected by the multiplexer 52. For example, the output of the latch circuit 30 is selected when the rising timings of the clocks A and B are not close to each other, and the output of the latch circuit 32 is selected when they are close to each other. Of course, the reverse is also possible.

Next, the latch circuit 36 and the EXOR gate 54 are for obtaining a change point of the signal SB to obtain the enable signal SE of FIG. In other words, it is for obtaining the enable signal SE of the data output in the synchronizing circuit 38 by using the signal SB and the clock A whose output has been adjusted by the multiplexer 52 when the timing between the clocks is close. The number of pulses of the enable signal SE corresponds to the period (data transfer request period) of the logical value “H” in the transfer signal SP.

The synchronizing circuit 38 is a circuit which operates in synchronization with the clock A, outputs the data SC (FIG. 2 (G)) based on the enable signal SE, and controls the signal CA (FIG. 2 (H)). Has the function of outputting. The latch circuits 40, 42, 44 and 46 use the clock A
And has a function of latching the data SC based on the control signal CA (FIG. 2 (I)-
(L)).

The latch circuits 14, 16 and 18 delay the transfer signal SP to obtain the delayed transfer signal SPD (FIG. 2 (M)). The counter 24 counts the clock B in the period of the logical value “H” of the delayed transfer signal SPD to obtain the control signal CB (FIG. 2 (N)) corresponding to the length of the data transfer request period. is there.

The multiplexer 56 has a function of sequentially selecting the data outputs DA, DB, DC and DD of the latch circuits 40, 42, 44 and 46 based on the control signal CB. Specifically, data selection is performed in a section indicated by an arrow in FIGS. 2I to 2L so that a timing error does not occur. Latch circuit 20
Is for latching the input data at the timing of the clock B and outputting the signal SD. Synchronization circuit 26
Is a circuit that operates in synchronization with the clock B.

Next, the operation of the embodiment configured as described above will be described. In this embodiment, as shown in FIGS. 2A and 2B, the frequency is clock A> clock B. That is, the synchronizing circuit 38 operates on the clock A, the synchronizing circuit 26 operates on the clock B, and the synchronizing circuit 38 operates.
Is operating faster than the synchronizing circuit 26. Therefore,
In order to perform good data transfer between the two, it is necessary to adjust the timing between the clocks so that the data output from the synchronizing circuit 38 matches the data fetching operation of the synchronizing circuit 26. In the present embodiment, such adjustment is performed by the enable signal SE of the synchronizing circuit 38.

As shown in FIG. 2B, the transfer signal SP synchronized with the clock B is a signal whose logic value is "H" in the data transfer request period, and the number of data corresponding to the length of this period. This signal requests transfer. Transfer signal SP is EX
The signal is supplied to the OR gate 50, and the signal SA shown in FIG. 2C is produced by the operation of the EXOR gate 50 and the latch circuits 10 and 12. This signal SA is a signal that is repeatedly inverted by the clock B during the logical value "H" of the transfer signal SP. In other words, during the transfer request period, the clock B is repeated.
The pulse signal corresponds to the number of data that can be transferred in conformity with. In the latch circuit 30, the signal SA is latched at the rising timing of the clock A, and the latch circuit 32
Then, the signal SA is latched at the falling timing of the clock A.

On the other hand, the pulse circuit 22 generates pulses at the rising timing of the clock B. The latch circuit 34 latches the pulse at the rising timing of the clock A. Therefore, the output of the latch circuit 34 is a logical value "L" except when the clocks A and B are close to each other, and is a logical value "H" when the clocks A and B are close to each other. In the multiplexer 52, the outputs of the latch circuits 30 and 32 are selected according to the logical value of the latch circuit 34. For example, normally, the output of the latch circuit 30 is selected,
When the rising edges of the clocks A and B are close to each other, the output of the latch circuit 32 is selected.

As mentioned above, the frequency of the clock A is higher than that of the clock B. Therefore, at some point clock A,
Assuming that the rising timings of B coincide with each other, there will come a time when the rising timings of both coincide with each other in a cycle determined by the difference between the frequencies of the two. For example, clock A
It is assumed that the synchronizing circuit 38 that is synchronized with 11 can output data at a rate of 11 units per unit time, and the synchronizing circuit 26 that is synchronized with the clock B can receive data at a rate of 10 units per unit time. Then, the data cannot be transferred favorably at a rate of 1 in 11. The period in which the data transfer is hindered coincides with the period in which the rising timings of the clocks A and B are close to each other.

Therefore, in the present embodiment, the latch circuit 34 detects a cycle in which the rising timings of both clocks are close to each other, and the multiplexer 52 performs a selection operation according to the detection result, so that the signal SA changes to the signal SB (FIG. 2). (E))
Is converted to. As a result, data can be exchanged between the synchronization circuits 26 and 38 without causing a timing error. The signal SB is converted into an enable signal SE (FIG. 2 (F)) whose change point is converted into a pulse by the operation of the latch circuit 36 and the EXOR gate 54.
The number of pulses of the enable signal SE is equal to the length of the period of the logical value "H" in the transfer signal SP.

The synchronizing circuit 38 outputs data SC (FIG. 2 (G)) and control signal CA (FIG. 2 (H)) based on the enable signal SE. In the latch circuits 40, 42, 44 and 46, the data SC is sequentially latched based on the control signal CA (FIG. 2 (I)-
(L)).

On the other hand, the transfer signal SP is the latch circuits 14, 1
6, 18 are sequentially latched and the delayed transfer signal SPD
(FIG. 2 (M)) is obtained. The delayed transfer signal SPD is input to the counter 24, where the clock B is counted and the control signal CB is obtained (FIG. 2).
(N)). That is, the count operation is performed based on the clock B included in the period of the logical value "H" of the transfer signal SP, and the latch data DA, L of the latch circuits 40, 42, 44, 46 is output from the multiplexer 56 in accordance with the count value. D
B, DC and DD are sequentially selected. At this time, the multiplexer 56 selects the data in the section shown by the arrows in FIGS. 2I to 2L so that a timing error does not occur. The selected data is latched by the clock B in the latch circuit 20, and the latch signal SD (FIG. 2 (O)) is supplied to the synchronizing circuit 26.

Next, the operation of the above embodiment will be described as a whole with reference to FIG. The clocks A and B are as shown in FIGS. 3 (A) and 3 (B), for example. Since the frequencies of the two are different, the timing of the clock B is behind that of the clock A. Here, it is assumed that the data output from one synchronizing circuit 38 at the clock A1 is received by the other synchronizing circuit 26 at the clock B1 immediately thereafter (arrow F1). When this operation is sequentially performed, the data output at the clock A2 is received at the clock B2 (arrow F
2), the data output at clock A3 is clock B3
Is received (arrow F3), and the data output at clock A4 is received at clock B4 (arrow F4).

However, with respect to the next clocks A5 and B5, the clock B5 is delayed by one cycle of the clock A and becomes a clock immediately after the clocks A5 and A6. Then, as shown by arrows F5 and F6, the other synchronization circuit 2
6 must receive the data output from one of the synchronizing circuits 38 at the clocks A5 and A6 at the timing of the clock B5 at the same time.

In order to prevent such an inconvenience, in the present embodiment, the pulse circuit 22 and the latch circuit 34 detect a state in which the rising edges are close to each other like the clocks A6 and B5. Then, in order to stop the data output from the synchronization circuit 38 indicated by arrow F6, the outputs of the latch circuits 30 and 32 are selected by the multiplexer 52, the enable signal SE is generated based on this, and the synchronization circuit is generated based on this. 38 outputs the data signal SC.

Further, as shown by the arrows F1 to F5, F7, ..., Since the timings of the clock A and the clock B are changing every moment, the data transfer is favorably performed in consideration of the timing difference between the two. As can be seen, the latch circuit 40,
Timing control is performed by 42, 44, 46 and the multiplexer 56.

That is, the data output control of the synchronizing circuit 38 avoids the data transfer error caused by the periodical proximity of the clock timing, that is, the data transfer error caused by the difference in the clock frequency. Then, a data transfer error caused by a difference in transfer timing for each clock pulse, that is, a data transfer error caused by a difference in clock phase is generated.
This is avoided by the timing adjustment by the latch circuit and the multiplexer on the output side of the synchronizing circuit 38 (the input side of the synchronizing circuit 36).

As a result, the circuit is composed only of the random logic, and the 2-port RAM becomes unnecessary. Therefore, the application to the gate array becomes easy. This embodiment can be used as it is in the data input / output portion of the circuit to be applied, and the conventional circuit assets can be effectively utilized.

In the above embodiment, if the clock B is in the range satisfying the expression (1), the transfer operation can be performed satisfactorily no matter how the frequency changes.
Further, when the output of the data signal SC of the synchronizing circuit 38 has a delay with respect to the enable signal SE, it can be dealt with by increasing the number of stages of the latch circuits 40, 42, 44, 46 for holding data. Furthermore, before inputting the transfer signal SP, the data signal SC is transferred to the data holding latch circuits 40 and 4.
If they are stored in 2, 44, and 46 in advance, the output signal SD can be obtained immediately after the input of the transfer signal SP.

<Second to Fourth Embodiments> Next, the second embodiment of the present invention.
-A 4th Example is described. The same components as those in the first embodiment or components corresponding to the first embodiment are designated by the same reference numerals.

First, in the second embodiment shown in FIG. 4, a DSP (Digital Si) driven by a high-speed system clock is used.
In this embodiment, data is transferred from the gnal processor) 60 to the DSP 62 driven by another low-speed system clock. In the figure, the DSP 62 corresponds to the synchronizing circuit 26 of FIG. The other circuits in FIG. 1 are D
Built into SP60. According to this embodiment, the DS
Clock B, transfer signal SP from P62 side to DSP 60 side
Are supplied from the DSP 60, respectively.
The data signal SD is transferred to P62. The basic operation is as described above.

In the third embodiment shown in FIG. 5, the data signal SD is directly transferred from the DSP 70 to the display 72 based on the transfer signal SP supplied from the outside. In the fourth embodiment shown in FIG. 6, systems 82 and 8 having different clocks are used.
The output side of the transfer signals SP1, SP2, SP3 of 4, 86 and the output side of the clocks B1, B2, B3 are selectors 8.
8 is connected. The output side of the transfer signal SP and the clock B of the selector 88 is connected to the DSP 80. Further, the output side of the data signal SD of the DSP 80 is connected to the data input side of each system 82, 84, 86.

According to this embodiment, the transfer signal and clock of the system selected by the selector 88 are the DSP.
The data signal SD that is supplied to the system 80 and is output from the DSP 80 based on this is supplied to each system. Then, the capture is performed in the corresponding system.
Since the circuit shown in FIG. 1 can be applied to various clocks satisfying the condition of the expression (1), the present invention can be applied even when data is supplied to a plurality of systems having different clocks as in the fourth embodiment. Is valid.

<Other Embodiments> The present invention is not limited to the above-described embodiments. For example, although a latch circuit or a multiplexer is used in the above-mentioned embodiments, the circuit configuration has the same operation. As described above, various design changes are possible.

[0039]

As described above, according to the data transfer circuit of the present invention, the transfer error due to the frequency difference between the two clocks and the transfer error due to the phase difference are individually adjusted and avoided. Because I decided to do it, 2
There is an effect that data transfer between different clocks can be performed without an error without using a port RAM, which is convenient for application to various circuits.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of a data transfer circuit according to the present invention.

FIG. 2 is a time chart showing the operation of the embodiment.

FIG. 3 is an explanatory diagram showing an operation of the embodiment.

FIG. 4 is a configuration diagram showing a second embodiment of the present invention.

FIG. 5 is a configuration diagram showing a third embodiment of the present invention.

FIG. 6 is a configuration diagram showing a fourth embodiment of the present invention.

FIG. 7 is a configuration diagram showing an example of a conventional data transfer circuit.

[Explanation of symbols]

10, 12, 30, 32, 34, 36 ... Latch circuit (first timing adjusting means) 14, 16, 18 ... Latch circuit (second timing adjusting means) 20, 40, 42, 44, 46 ... Latch circuit (Second Timing Adjusting Means) 22 ... Pulse Circuit (First Timing Adjusting Means) 24 ... Counter (Second Timing Adjusting Means) 26 ... Synchronous Circuit (Second Device) 38 ... Synchronous Circuit (First Device) ) 50, 54 ... EXOR gate (first timing adjusting means) 52 ... Multiplexer (first timing adjusting means) 56 ... Multiplexer (second timing adjusting means) A ... Clock (first clock) B ... Clock ( Second clock) CA, CB ... Control signal SA, SB ... Signal SC, SD ... Data signal SE ... Enable signal

Claims (1)

[Claims] 1. A first operating according to a first clock
The data output from the second device is transferred to the second device operating based on the second clock having the frequency f2 satisfying the condition of f1 ≧ f2> 0 (Hz) with respect to the frequency f1 of the first clock. In the data transfer circuit, a first timing adjusting means for controlling data output from the first device to prevent a transfer error caused by a difference in frequency of the first and second clocks; And second timing adjusting means for controlling the input of the data output from the first device to the second device in order to prevent a transfer error caused by the phase difference of the second clock. Data transfer circuit characterized by.