JPS5927358A - Hardware tracing device - Google Patents

Abstract

PURPOSE:To execute tracing by keeping correctly a time interval, by inputting a trace timing signal by clock signals of opposite phase to each other by two FFs, and tracing it together with a trace data. CONSTITUTION:A trace data input signal and a trace timing signal are inputted to a register 1 and an FF4 by a clock signal on a clock signal line 108, respectively. Also, each output is sent to a memory address of a trace memory 2 addressed by an output of an address register 7, and is written by a clock 1. On the other hand, the trace timing signal is inputted to an FF5 by opposite polarity of a clock signal 109. At the same time, the output of the register 7 is inputted to a register 9, too. An output of the FF5 is sent to a memory address of a trace memory 6 addressed by the register 9, and is written by a clock 2. When reading out a trace data, an output of the memory 2 and an output of the memory 6 are read out to a register 3 by a positive polarity clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (Description of the technical field to which the invention pertains) The present invention relates to a hardware tracing device used in data processing equipment to search for faults, debug programs, etc., and record the state of hardware. .

(Description of the Prior Art) Conventionally, data processing devices have used high-speed memories for hardware tracing, which has had the disadvantage that as the speed of the devices increases, the cost of the device's hardware increases significantly.

Further, when a low-speed memory element is used to realize a trace function at low cost, trace data is generally stored based on a trace timing signal at each arrival timing of the trace timing signal. For this reason,
Unless the period of the trace timing signal is an integral multiple of the clock signal for storing trace data and always has a constant period, it is difficult to trace while keeping the time interval correct.

(Detailed Description of the Invention) An object of the present invention is to input trace timing signals into first and second flip-flops using clock signals having opposite phases to each other, and to input each clock signal, the trace data, and the trace timing signal to the first and second flip-flops, respectively. By storing the trace data in the second trace memory and correcting the trace data according to the trace state of the trace timing signal when reading the trace data, the above disadvantages are solved, and the time interval is correct while using an inexpensive low-speed memory element. It is an object of the present invention to provide a hardware tracing device that can maintain and trace information.

(Structure of the Invention) A hardware tracing device according to the present invention includes an input register, first and second flip-flops, first and second trace memories, and first and second address registers. It is.

The input register is a circuit for synchronizing input of trace data. i10) The 7 lip-flop is a circuit for setting the trace timing signal of trace data with the same clock signal as the clock signal for driving the input register. The first trace memory is a memory circuit for storing both the output of the input register and the output of the first flip-flop. The first address register is a circuit for sequentially addressing the contents of the first trace memory. This is the second flipping circuit. Second trace memory Vi is a memory circuit for storing the output of the second flip 70 tube. The second address register 2 is a circuit for sequentially addressing the second trace memory by setting the output of the first address register using a clock signal of opposite phase.

(Description of the principle and operation of the invention) In the hardware tracing device according to the present invention, a trace timing signal is input to the first and second 7-lip-flops using clock signals having opposite phases to each other, and trace data and trace timing are input for each clock. In order to trace the signals, tracing was performed every 1/2 clock by correcting the time of the trace data from the trace results of the trace timing signals assigned to the first and second flip-flops respectively during readout. become equivalent to something.

(Description of Examples) Next, the present invention will be described in detail with reference to the drawings. FIG. 1 shows a block diagram of a hardware tracing device according to the present invention. In FIG. 1, the hardware tracing device includes an input register 1 and first and second trace memories 2.
, 6, an output register 3, first and fs2 seven lip-flops 4, 5, first and second address registers 7.9, an increment/decrement circuit 8,
It is configured to include a clock signal driver 1o. In FIG. 1, trace data is input from a trace data input signal line 101 to an input register 1, and trace data is input from an input register 1 to a first trace memory 2 via an output signal 102. The trace data sent to the output signal line 103 from the first trace memory 2 is input to the output register 3.
The signal is output from the output signal line 104 to the outside. Trace timing signal line 105 F! input to the first flip-flop 4 and the second flip-flop 5;
The output of the flip-flop 4 is input to the first trace memory 2 via the signal line 106. The output of the second flip-flop is input to the second trace memory 176 via the signal line 107, and the output of the second trace memory 6 is input to the output register 3 via the signal line 113. The output of the first address register 7 is sent via a signal line 110 to an increment/decrement signal for incrementing or decrementing the contents of the first address register 7 itself.
a decrement circuit 8, a second address register 9,
and a first trace memory 2, respectively.

The output of the increment/decrement circuit 8 is the signal line 1
11 to the first address register 7, and further the output tt(, % return line 1
12 to the second trace memory 6.

a clock signal applied to the clock signal driver 10;
A positive output terminal 108 of the clock signal driver 10 is connected to the input register 1 , the output register 3 , the first flip-flop 4 and the first address register 7 . On the other hand, the negative output terminal 1 of the clock signal driver 10
09 C is connected to the second flip-flop 5 and the second address register 9. Further, the first write clock signal is supplied to the i-th tracer memory 2, and the second write clock signal is supplied to the second tracer memory 6. The respective signals are taken into the input register 1 and the first flip-flop 4 via the trace data input signal line 101 and the trace timing signal line 105 by the clock signal on the clock signal line 108, respectively. In addition, each output 1- is written to the memory address of the first trace memory 2 addressed by the output (i retrace line 110) of the first address register 7 by the first write clock.On the other hand, the trace timing signal The trace timing signal on the line 105 is taken into the second flip-flop 5 by the clock signal of opposite polarity on the clock signal line 109.At this time, the output of the first address register 7 is simultaneously sent via the signal line 110. It is also taken into the second address register 9 as 1.

The output of the second flip-flop 5 is input via the signal line 107 to the memory address of the @2 trace memory 6 addressed by the output of the second address register 9 by the second write clock 4). After tracing is completed, if the trace data is read f8, it is stored in the first trace memory 2.
and the output of the second trace memory 6 are read out to the output register 3 using a positive clock signal.

Next, the timing of tracing will be explained with reference to the timing chart shown in FIG. In FIG. 2, a is a clock signal, b is a trace data input, C is a trace timing signal, dHH2O7 state value of flip-flop 4, ei; i state value of second flip-flop 5, and f is input to input register 1. trace data,
g is the first write clock signal, h is the input of the first trace memory 2, iF'i is the second write clock signal, j
is the input data of the second trace memory 6, ktlj) is the correction signal after reading the trace memory. In FIG. 2, trace data is input by the clock signal a on the clock signal line 108, bl, b2, b3.
, b4, ))5.

Like b6, b7, 1/! It is input at intervals of nT. Here nFi is an integer and Tfl is a clock period.

In this embodiment, the trace timing signal cod is the second half of the trace data input. It is given in period T.

``The first flip-flop 4uEx operates on the rising edge of the clock signal.

Take in E2, E4, and E5. As a result, the output of the first flip-flop 4 becomes a value as indicated by the state value d.

On the other hand, since the second flip-flop 5 is supplied with a clock signal of opposite polarity via the signal line 109,
E3 and E6 are taken into the output of the second flip-flop 5 as shown by the state value e. As shown by input data f, trace data is zumbling and taken into the input register 1 at a period T. first flip-flop 4
The state value of the output of and the contents of the input trace data f of the input register 1 are transferred to the input data 11 in order to the given address of the first trace memory 7 by the first write clock g.
written as . Further, the output of the second flip-flop 5 is sequentially written as input data J to a given address of the second trace memory 6 by the second write clock i.

After reading the contents of the first and second trace memories 2 and 6, as shown in the correction in FIG. 2
By reproducing the trace timing signal based on both the contents of the first trace memory 2 and the contents of the first trace memory 2, and dividing the time from the trailing edge of the immediately preceding trace timing signal by the trailing edge of its own trace timing signal. The contents can be reproduced as original trace data.

(Detailed Description of the Invention) As explained above, the present invention takes in the trace timing signal as a clock signal with opposite phases to each other by the first and second flip-flops, and traces this together with the trace data, thereby achieving economic efficiency. This has the effect that it is possible to realize a hardware tracing device with good performance and high accuracy.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a hardware tracing device according to the present invention, and FIG. 2 is a timing diagram showing the operation of the hardware tracing device shown in FIG. 1... Input register 2, 6... Trace memory 3... Output register 4.5... Flip 70 knob 7.9... Address register 8... Increment/decrement circuit 10...・
Clock signal drivers 101 to 113...Signal line patent applicant Hisashi Inoro, agent for NEC Corporation, patent attorney

Claims (1)

[Claims] an input register for synchronizing the input of trace data; a first flip-flop for setting the trace timing signal of the trace data by the same clock signal as the clock signal for driving the input register; and the input register. a first trace memory for storing both the output of the register and the output of the first flip-flop; a first address register for sequentially addressing the contents of the first trace memory; and the trace timing. a second flip-flop 70 for setting the signal with a clock signal having an opposite phase to the clock signal; a second trace memory for storing the output of the second flip-flop; and the first address. The output of the register is converted into the opposite phase clock signal KJ:
F) a second address register for setting and sequentially addressing the second trace memory.