JPH0555217A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the density of wiring. CONSTITUTION:An inter-layer insulating film 4A on a semiconductor substrate 1 is flattened, and an inter-layer insulating film 4B is grown. The inter-layer insulating film 4B is etched while using a photo-resist film 5 having a desired wiring pattern as a mask. Through-holes 7A, 7B are formed, and a wiring metallic film 8 is grown on the whole surface through a sputtering method. Anisotropic etching is added from the oblique direction while turning the semiconductor substrate 1 in order to remove thin wiring metallic films 8C on side faces connecting wiring metallic films 8B grown on projecting sections by the inter-layer insulating film and wiring metallic films 8A grown in recessed sections. The wiring metallic films 8B on the projecting sections and the wiring metallic films 8A in the recessed sections are separated completely through the etching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming metal wiring.

[0002]

2. Description of the Related Art In the conventional wiring forming method of a semiconductor device, the wiring pattern of each wiring layer is formed on the same flat interlayer film by a photolithography technique. Fig.3 (a)-
(D) is sectional drawing of the semiconductor chip shown in the order of processes for explaining the conventional example.

First, as shown in FIG. 3A, a semiconductor substrate 1 having an uneven surface formed by contact pads 2 etc. is formed.
An interlayer insulating film 3 made of PSG or the like is formed on the surface of the. Next, as shown in FIG. 3B, the interlayer insulating film 3 is selectively etched using the photoresist film 6 as a mask to form a through hole 7 on the contact pad 2. Thereafter, as shown in FIG. 3C, a wiring metal film 8 is grown on the entire surface by a sputtering method or the like, and further, as shown in FIG. 3D, the wiring metal film 8 is formed using the photoresist film 9 as a mask. Selective etching is performed to obtain a desired wiring pattern.

[0004]

The limit of the wiring density can be evaluated by the sum of the minimum wiring width that can be formed and the minimum wiring interval (minimum wiring pitch).

However, in such a conventional wiring forming method, the minimum wiring width and the minimum wiring interval both depend on the same photolithographic ability, and therefore the values of both are almost the same (for example, the minimum wiring width is 1 μm. If so, the minimum wiring interval is also about 1 μm), and it has been difficult to reduce the minimum wiring pitch to about twice the minimum wiring width or the minimum wiring interval.

[0006]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming an insulating film on a semiconductor substrate, and an upper portion of the insulating film is patterned by anisotropic etching to obtain a vertical cross-sectional shape. A step of forming an uneven surface, a step of forming a metal film on the entire surface including the uneven surface, and anisotropy from an oblique direction with respect to the normal line while rotating the semiconductor substrate about the normal line of the central portion thereof. Etching the metal film by a conductive etching method to separate the metal film grown on the convex portion of the insulating film and the metal film grown in the concave portion.

[0007]

The present invention will be described below with reference to the drawings. 1A to 1E are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1 (a), a semiconductor substrate 1 having irregularities formed by contact pads 2 or the like on its surface is formed.
After planarizing the surface of the substrate with the interlayer insulating film 4A, the interlayer insulating film 4B is further grown so that the thickness of the interlayer insulating film becomes a desired thickness. At this time, the total thickness of the interlayer insulating films 4A and 4B is made thicker than the desired total thickness of the interlayer insulating film and the wiring. If the thickness of the interlayer insulating film 4A is sufficiently thick, the interlayer insulating film 4B does not necessarily have to grow. However,
Here, the interlayer insulating film 4A is formed to have a desired thickness, and the interlayer insulating film 4B is separately configured so that the etching on the interlayer insulating film 4 can be selectively performed. Next, using the photoresist film 5 having a desired wiring pattern as a mask, the interlayer insulating film 4B is selectively etched by an anisotropic etching method. At this time, the photoresist film 5 is formed so that the interlayer insulating film 4B above the lower contact pad 2 is also etched.
Design the pattern.

Next, as shown in FIG. 1B, after removing the photoresist film 5, the interlayer insulating film 4A is etched by an isotropic etching method using the new photoresist film 6 as a mask to make contact. A shallow through hole 7A and a deep through hole 7B are formed on the pad. The etching conditions at this time are set so that the etching rate of the interlayer insulating film 4B is the same as or slightly faster than the etching rate of the interlayer insulating film 4A.

Such etching is possible, for example, by using a CF ₄ / O ₂ gas when an SiO ₂ film is used for the interlayer insulating film 4A and a SiN film is used for the interlayer insulating film 4B. The sex-selective etching can be performed with an NF ₃ / Cl ₂ system gas. The shallow through hole is shown in Figure 1 (a).
The opening width of the photoresist film 5 in FIG. 1 is set wider than the opening width of the photoresist film 6 in FIG. On the contrary, the deep through-hole portion is formed by setting the opening width of the photoresist film 6 in FIG. 1B wider than the opening width of the photoresist film 5 in FIG. Deep through holes 7 due to the isotropic etching described above.
The tapered etching progresses from each surface of the interlayer insulating film 4B in the B portion, and a tapered sectional shape is obtained as a whole.

Next, as shown in FIG. 1C, a wiring metal film 8 is grown on the entire surface by a sputtering method. At this time, since the step coverage of the uneven portion due to the interlayer insulating film 4B formed by anisotropic etching is poor, the wiring metal film 8A grown to fill the concave portion and the wiring metal film 8B grown above the convex portion are thin. They are connected by a wiring metal film 8C on the side surface.

Then, while the semiconductor substrate 1 is rotated, anisotropic etching such as ion milling is performed in an oblique direction, so that the wiring metal film 8A in the concave portion and the wiring metal on the convex portion are formed as shown in FIG. 1D. Membrane 8B is separated. However, it is necessary to set the etching angle ψ at this time so that the wiring metal film 8B of the convex portion does not cause the wiring metal film 8C on the side surface to be a shadow of the etching. For example, if the etching angle ψ is set to 45 °, the etching rates of the wiring metal films 8A and 8B on the convex portions and the concave portions in the substrate normal direction are equal to the etching rates of the side wiring metal films 8C in the substrate surface direction. Become. The thickness of the wiring metal film 8C on the side surface can be set to 10% or less of the grown film thickness depending on the sputtering conditions. Therefore, even if the wiring metal film 8C is completely removed by anisotropic etching, the flat part of the wiring is A film thickness of about 60% can be secured. The side wall of the deep through hole 7B is tapered, and the taper angle at the worst part is 20%.
If the opening widths of the photoresist films 5 and 6 are designed to be about the same, the wiring metal film is formed on the side wall portion with a film thickness of about 30% or more of the flat portion. Since the metal film on the side wall portion is closer to vertical etching than the wiring metal film on the flat portion, it is etched at a faster etching rate.

However, assuming ion milling with gold as the wiring metal and anisotropic etching, the etching rate ratio of the etching angle of 0 ° to the etching angle of 45 ° is about 1.4 times. Membrane 8C
Even if it is completely removed, about 16% or more of the flat portion of the wiring metal film remains on the side wall of the through hole. Therefore, if the growth thickness of the wiring metal film is set to be sufficiently thick, there will be no problem in through-hole contact. When the wiring metal film is formed by vacuum vapor deposition, the wiring metal film 8C on the side surface can be made thinner, so that the film reduction of the wiring metal film due to anisotropic etching can be suppressed. Then, in order to remove unnecessary wiring portions, the photoresist film 9 shown in FIG.
The wiring metal film 8 is etched using the as a mask.

Since the wirings formed as described above can be formed with the distance between the adjacent wirings being substantially zero, the density of the wiring pattern can be increased.

2 (a) to 2 (c) are sectional views of a semiconductor chip in the order of steps for explaining the second embodiment of the present invention.

First, as shown in FIGS. 1 (a) to 1 (d),
A wiring metal film is formed in exactly the same process as in the first embodiment.
After that, when removing the unnecessary wiring metal film, etching was performed only in the photoresist process in the first embodiment. At this time, as shown in FIG. 1E, when the thin wiring pattern is removed, since the wiring interval is almost zero, the alignment margin is strict and only the photoresist film on the wiring metal film on the convex portion is exposed. It is necessary to devise such as controlling the amount of exposure.

Therefore, in the second embodiment, as shown in FIG. 2A, before the photoresist process, an interlayer insulating film 10 such as a SiN film is grown on the entire surface by a CVD method, and then a polyimide film or the like is used. The insulating coating film 11 is filled in the concave portion to planarize it. After that, the insulating coating film 11 is baked and solidified by heat treatment, and then the interlayer insulating film 10 and the insulating coating film 11 are etched back until the wiring metal film 8B on the convex portion is exposed as shown in FIG. 2B. ..

Through the above steps, the wiring metal film 8A in the recess is formed.
Is filled with the interlayer insulating films 4B and 10, and only the wiring metal film 8B on the convex portion is exposed, so that only the wiring metal film 8B can be selectively etched. At this time, as shown in FIG. 2C, the necessary wiring metal film is covered with the photoresist film 9, but the edge of the resist pattern is the interlayer insulating film filling the space between the wiring metal films 8B on the convex portions. Since the wiring metal film 8B on the adjacent convex portion can be separated if it is on 10 and the insulating coating film 11, a sufficient alignment margin can be obtained. Therefore, with respect to the wiring metal film 8B on the convex portion, it is possible to remove unnecessary portions even in a narrow portion by the above steps.

Regarding the recess wiring metal film 8A, it is difficult to selectively remove the narrow portion, but the photoresist film 5 (FIG. 1) when forming the unevenness of the interlayer insulating film 4B is used.
In the pattern design of (b), applying only the necessary wiring pattern to the recess does not cause a problem.

[0020]

As described above, according to the present invention, the adjacent wiring metal films are separated by utilizing the unevenness of the insulating film pattern. It will be possible. Therefore, there is an effect that the density of the wiring pattern can be increased by about twice as compared with the conventional method of manufacturing a semiconductor device.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor chip for explaining a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Contact Pad 3 Interlayer Insulation Film 4A, 4B Interlayer Insulation Film 5, 6 Photoresist Film 7, 7A, 7B Through Holes 8, 8A, 8B, 8C Wiring Metal Film 9 Photoresist Film 10 Interlayer Insulation Film 11 Insulation Coating film

Claims (1)

[Claims] 1. A step of forming an insulating film on a semiconductor substrate, and a step of patterning an upper portion of the insulating film by an anisotropic etching method to form an uneven surface having a vertical sectional shape,
The step of forming a metal film on the entire surface including this uneven surface, and the metal film is formed by an anisotropic etching method from an oblique direction with respect to the normal line while rotating the semiconductor substrate about the normal line at the center thereof. A method of manufacturing a semiconductor device, comprising: a step of etching to separate a metal film grown on a convex part of the insulating film and a metal film grown on a concave part of the insulating film.