JPH0549991B2 - - Google Patents

Info

Publication number
JPH0549991B2
JPH0549991B2 JP58184720A JP18472083A JPH0549991B2 JP H0549991 B2 JPH0549991 B2 JP H0549991B2 JP 58184720 A JP58184720 A JP 58184720A JP 18472083 A JP18472083 A JP 18472083A JP H0549991 B2 JPH0549991 B2 JP H0549991B2
Authority
JP
Japan
Prior art keywords
memory
data
supplied
arithmetic processing
depth direction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58184720A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6076790A (ja
Inventor
Hiroshi Takigawa
Masaaki Oka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Sony Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Sony Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP58184720A priority Critical patent/JPS6076790A/ja
Publication of JPS6076790A publication Critical patent/JPS6076790A/ja
Publication of JPH0549991B2 publication Critical patent/JPH0549991B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Controls And Circuits For Display Device (AREA)
  • Image Input (AREA)
  • Memory System (AREA)
JP58184720A 1983-10-03 1983-10-03 メモリ装置 Granted JPS6076790A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58184720A JPS6076790A (ja) 1983-10-03 1983-10-03 メモリ装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58184720A JPS6076790A (ja) 1983-10-03 1983-10-03 メモリ装置

Publications (2)

Publication Number Publication Date
JPS6076790A JPS6076790A (ja) 1985-05-01
JPH0549991B2 true JPH0549991B2 (US06534493-20030318-C00166.png) 1993-07-27

Family

ID=16158181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58184720A Granted JPS6076790A (ja) 1983-10-03 1983-10-03 メモリ装置

Country Status (1)

Country Link
JP (1) JPS6076790A (US06534493-20030318-C00166.png)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6215593A (ja) * 1985-07-15 1987-01-23 株式会社　アスキ− 記憶装置
US5195056A (en) * 1987-05-21 1993-03-16 Texas Instruments, Incorporated Read/write memory having an on-chip input data register, having pointer circuits between a serial data register and input/output buffer circuits
JPS6465596A (en) * 1987-08-05 1989-03-10 Texas Instruments Inc Memory
JPH0754545B2 (ja) * 1987-12-23 1995-06-07 松下電器産業株式会社 データ構造変換装置
JPH032896A (ja) * 1989-05-31 1991-01-09 Fujitsu Ltd Ｖ―ｒａｍ表示装置
JPH0737378A (ja) * 1993-07-19 1995-02-07 Nec Corp メモリ素子
DE60100862T3 (de) * 2000-05-29 2011-03-17 Valeo Thermique Moteur Endkammer für einen gelöteten wärmetauscher

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5631154A (en) * 1979-08-23 1981-03-28 Victor Co Of Japan Ltd Memory device
JPS59192285A (ja) * 1983-04-15 1984-10-31 株式会社日立製作所 画像メモリ回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5631154A (en) * 1979-08-23 1981-03-28 Victor Co Of Japan Ltd Memory device
JPS59192285A (ja) * 1983-04-15 1984-10-31 株式会社日立製作所 画像メモリ回路

Also Published As

Publication number Publication date
JPS6076790A (ja) 1985-05-01

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