JPH0548492B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a microprogram-controlled information processing device using a virtual computer method, and particularly to an exception interrupt method. [Prior Art] Conventionally, this type of information processing device, when an exception is detected when the device is operating as a virtual computer,
A specific microprogram that handles exception interrupts is started, and the launched microprogram determines the type of exception that has occurred, and depending on the type of exception, either handles the exception interrupt in virtual machine mode or in real computer mode. mode (virtual machine mode) to determine whether to handle exception interrupts. [Problems to be Solved by the Invention] In the conventional information processing device described above, a microprogram determines the type of exception, and when the device is operating in virtual machine mode, directly performs exception interrupt processing in virtual machine mode. If the exception cannot be directly handled in virtual machine mode, the microprogram resets the VM (virtual machine mode) flag and executes it from virtual machine mode. Since mode transition is performed to the computer mode, there are drawbacks such as a decrease in performance and an increase in the number of microprogram steps. [Means for solving the problem] The information processing device of the present invention has a VM mode flag indicating that the device is operating as a virtual machine, and a memory access exception related to the instruction word and operand of the instruction to be processed. an exception detection means for detecting an exception that occurs due to the execution of an instruction; an encoding means for converting an exception detection signal detected by the exception detection means into an exception code; Therefore, a memory decoder is provided with an address and outputs the start address of a series of microprograms that perform exception processing corresponding to the exception code, attribute information, and a signal indicating whether to reset the VM mode flag; and an output from the memory decoder. It has an attribute display means for holding attribute information and displaying the attribute information on the microprogram, and a control memory storing a plurality of microinstruction words, and has a control memory that stores a plurality of microinstruction words. and control storage means for sequentially outputting command words. [Function] When the device is operating in VM mode, an exception detected by the exception detection means is converted into an exception code, and this exception code is used to trigger a memory decoder to execute a series of microprograms that performs exception processing corresponding to the exception code. is activated, and attribute information consisting of an interrupt code to be notified to a software program that performs exception processing and attributes of the interrupt code is notified to the microprogram using an attribute display means. At this time, if the exception to be handled cannot be handled directly in VM mode, the VM mode flag is reset by the output of the memory decoder, and the mode is automatically changed from VM mode to real computer mode. In this way, since the determination of the type of exception and the reset of the VM mode flag are performed without using the microprogram, the processing performance of a series of microprograms that perform interrupt processing can be improved. [Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the information processing apparatus of the present invention, FIG. 2 is a diagram showing the data format of the memory decoder 3 in FIG. 1, and FIG. 3 is an attribute display means in FIG. 1. 4 is a diagram showing the data format of the attribute display register No. 4. FIG. This information processing device includes an exception detection means 1, an encoding means 2, a memory decoder 3, an attribute display means 4, a control storage means 5, and a VM mode flag 6.
It has The exception detection means 1 is a circuit that detects access exceptions to memory (not shown) related to instruction words and operands of software instructions to be processed by the information processing device, arithmetic exceptions generated by execution of instructions, etc. Connect the detected 16 exception signals e _x0 to e _x15 to signal line 1.
00 to the encoding means 2. The encoding means 2 is composed of an encoder 20 and an exception register 21. The encoder 20 prioritizes the exception detection signals e _x0 to e _x15 , encodes them into 4 bits, and outputs the exception code Ei to the exception register 21 via the signal line 200. The exception code Ei held by the exception register 21 is connected to the signal line 201
is applied to the memory decoder 3 as an address signal. The following table is a truth table for encoder 20.

【table】

〔Effect of the invention〕

As explained above, the present invention stores, for each exception, the start address of a series of microprograms that perform exception handling, attribute information, and information on whether or not the exception to be handled can be directly handled in VM mode in memory (memory decoder). ), and when the device is operating in VM mode, it is converted into an exception code detected by the exception detection means, and this exception code is used to draw the memory decoder and perform exception processing corresponding to the exception code. The interrupt code to be notified to the software program corresponding to the exception code and the attribute information consisting of the attributes of the interrupt code are notified to the microprogram using the attribute display means, and the exception to be handled is determined to be in VM mode. By resetting the VM mode flag with the output of the memory decoder and automatically transitioning from VM mode to real computer mode, the processing performance of a series of microprograms that perform interrupt processing can be improved. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the information processing apparatus of the present invention, FIG. 2 is a diagram showing the data format of the memory decoder 3 in FIG. 1, and FIG. 3 is an attribute display means in FIG. 1. 4 is a diagram showing the data format of the attribute display register No. 4. FIG. 1... Exception detection means, 2... Encoding means,
3...Memory decoder, 4...Attribute display means, 5
...Control storage means, 6...VM mode flag, 2
0...Encoder, 21...Exception register, 50
... Address circuit, 51 ... Address register,
52...Control memory, 53...Control register, 10
0,200,201,300~302,400,
500-504,600-602,700...Signal line.

Claims (1)

[Scope of Claims] 1. In a microprogram-controlled information processing device that uses a virtual computer system, a VM mode flag indicating that the device is operating as a virtual computer, and memory information regarding instruction words and operands of instructions to be processed. exception detection means for detecting access exceptions and exceptions generated by instruction execution; encoding means for converting the exception detection signal detected by the exception detection means into an exception code; a memory decoder that is given an address by an exception code and outputs the start address of a series of microprograms that performs exception processing corresponding to the exception code, attribute information, and a signal indicating whether to reset a VM mode flag; It has an attribute display means for holding attribute information output from the decoder and displaying the attribute information on the microprogram, and a control memory storing a plurality of microinstruction words, and has a control memory that stores attribute information output from the memory decoder. An information processing apparatus characterized by comprising: control storage means for sequentially outputting microinstructions.