JPS61112240A - Data processor - Google Patents

Abstract

PURPOSE:To attain the calculation of a memory indirect to address without increasing considerably the hardware by using a DA unit for execution of processes up to the calculation of the memory indirect address and then using an E unit for the rest calculation including the access of a memory. CONSTITUTION:In case the addressing mode of an operand means the states excluding a memory indirect state, an executing address needed for operand fetching is calculated by a DA unit 3. In a memory indirect address calculation mode, the unit 3 is used to execute the processes up to an address (IA) for a memory indirect state. Then the address IA is sent to an E unit 4 for execution of the executing address. Thus it is possible to perform calculation of a memory indirect to address without adding any memory access function to an address calculation unit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data processing device controlled by a microprogram, and particularly to a data processing device employing a pipeline system.

[Background of the invention]

The process of executing microinstructions (machine language instructions) in an electronic computer is generally an instruction fetch (IF).

Instruction decoding (D), operand address calculation (A)
), fetch operand (OF), execute instruction (E)
, and each stage (process) of result storage (ST).

In recent high-performance computers, noting that each of these stages performs independent processing, each stage has its own control mechanism and the instruction execution stage is carried out in a so-called assembly line. Pipeline control is used. However, in reality, 1gA is limited due to constraints on the amount of hardware, etc.
Each stage cannot be made independent, and in general, ■I
F (IF unit) ■D&A (DA unit), ■O
It is divided into three stages: F&E&ST (E unit). The DA unit decodes instructions and calculates operand addresses, but in order to perform address calculations that involve memory references, that is, memory indirect address calculations, the DA unit must be provided with a means of memory access. .

JP-A No. 58-146941 r Microprogram Control Data Processing Device" has a dedicated stage for memory access, so even indirect memory address calculations can be performed without A.
There was no need to provide the unit with a means of memory access. However, providing a memory access means in the DA unit for address calculation increases the amount of hardware and increases the complexity of control.On the other hand, if the E unit performs memory indirect address calculation, the memory Instructions that include indirect operands must be placed in a separate microprogram from operands in other addressing modes, which increases the size of the microprogram.
The method of calculating up to the memory address for memory indirection in the A unit and passing information indicating that the address is for memory indirection to the E unit along with the address does not increase the amount of hardware and increases the number of microprograms. There are also few.

However, in order to implement this method, it is necessary to determine what the address passed on the E unit side is.
The disadvantage is that the execution time of any instruction that accesses memory increases regardless of whether its operands use memory indirect addressing.

[Purpose of the invention]

The purpose of the present invention is to perform memory indirect addressing calculations by
The present invention provides a data processing device that can be executed without adding an access mechanism to an address calculation unit.

[Summary of the invention]

Computer instructions are becoming more sophisticated year by year, but at the same time, many methods for specifying the operands to be operated on by the instructions, that is, addressing, have been proposed in many complex ways, and calculating the effective addresses of the operands is also complex and time-consuming. It's starting to look like this. In particular, memory indirect address calculation requires memory access in the process of obtaining an effective address.

In order to perform this address calculation using a pipeline computer with a low number of stages, such as about three stages, the above-mentioned method can be considered. However, since memory indirect addressing is considered to be used less frequently than memory direct addressing, such as base register relative, it is not possible to reduce instruction execution time in order to efficiently perform memory indirect address calculations. , it is not a good choice, nor is it a good choice because the amount of hardware increases considerably.Therefore, even if it takes some time to calculate the memory indirect address, it is not a good choice to use other addressing modes. It is necessary to not slow down the execution of the currently used instructions and to suppress the increase in hardware as much as possible. In the present invention, in memory indirect address calculation, the DA unit performs the memory indirect address calculation, and the remaining address calculation including memory access is performed by the E.
We provide a way to do it in units. In other words, if the address calculated by the DA unit is for memory indirection, the memory indirection instruction plug in the E unit is set, and the E
When the unit accesses the memory of the operand, it determines the flag in hardware, and if memory indirection is specified, it suppresses the memory access and forcibly jumps to the microprogram for calculating the address of memory indirection. .

[Embodiment of the Invention] FIG. 2 shows an overall configuration diagram of a data processing device using a pipeline-controlled microprogram control method. Basic processor BPUI, main memory 5, and address bus 16 connecting them. The data bus 17 constituted a data processing device.

The BPUI includes an instruction fetch unit (IF) 2, a unit (D&A) 3 that performs instruction decoding (D) and operand address calculation (A), and an operand fetch (OF) and instruction execution (E) unit. unit (O
F&E) 4, and an internal bus 9.

The instruction fetch unit 2 reads instructions stored in the main memory 5, and the decode and address calculation unit 3
decodes the instruction passed from the instruction fetch unit 2 via the signal line 6 and calculates the execution address of the operand. The unit 4 performs operand access and instruction execution according to the start address of the microprogram for instruction execution and the operand address passed from the unit 3 via the signal line 7, and also performs memory indirect address calculation which is a feature of the present invention. Execute some.

In FIG. 2, signal lines 12, 14.18 are signal lines for carrying data, signal lines 13, 15.19 are signal lines for carrying addresses, and signal lines 8, 10.11 are interfaces with internal bus 9. It is a line.

The internal configuration of the unit 4 is shown in FIG.
Control circuit (CONT) 41, arithmetic unit (ALU & RF
) 42, address register 43, data register 44.
It consists of address lines 46, 47, status signal lines 45, and control signal lines 48. The configuration of this unit 4 is an important feature of the present invention.

The internal configuration of the control circuit 41 is shown in FIG.

The arithmetic unit 42 in FIG. 2 is operated by a control signal 48 output from a control circuit 41, and has an arithmetic unit (ALU) function and a register file (RF) that are found in a normal computer.
The address register 43, which performs functions, takes in either the memory address 47 from the signal [7 or the address of the calculation unit 42.

Data register 44 temporarily holds data sent from memory.

The signal line 7 carries the memory address 47, the start address 47 of the microprogram of the E unit 4 generated by decoding the instruction, and the status signal 45 output from the DA unit 3. Control circuit 41 in FIG.
is the control circuit of the instruction execution unit 4, and its contents are as follows:
Flip-flop 401, stack register 402. selector 403, incrementer 404, address register 405, microprogram storage memory 406,
9! Instruction register 407. It consists of a selector 408, a specific microinstruction holding register 409, a register 410, and gates 411, 412, and 413.

Memory 406 is a memory that stores microprograms;
The address register 405 is a register that holds the address of a microinstruction read from the memory 406, and the instruction register 407 is a register that holds the microinstruction that is the output of the memory 406.

Furthermore, the selector 403 selects the source of the address register 405, the incrementer 404 generates the address of the next microinstruction, and the stack register 402 stores the return address when the microprogram branches to a subroutine.

The status signal 45 sent from the DA unit is
A signal 414 indicating that a memory address is prepared in R43, a signal 423 indicating whether the data in MAR43 is an effective address or a memory address for memory indirect address calculation, and memory indirect address calculation. It consists of a signal 415 that indicates what kind of data is further added to the value obtained by memory reference when performing the memory reference. The values of signals 423 and 415 are held in 1-bit and 2-bit registers 401 and 410.

Register 409 holds specific microinstructions. The selector 408 selects the register 4 according to the value of the signal line 418.
A 6-bit area 424 that selects and outputs either the data of 09 or the data of the instruction register 407 is located in the memory 4.
Stores 1 bit of the microinstruction read from 06.

With the configuration shown in Figure 1 above, 402, 403, 404° 40
5.406 and 407 are well known in computers that perform microprogram control. Therefore, the new component according to the invention is 401,408°409.410,41
It is 1,412,413.

Next, the operation of this embodiment will be explained. If the addressing mode of the operand is other than memory indirect, the effective address required for fetching the operand is DA unit 3.
It can be calculated completely. For example, in register relative addressing where the effective address is the pace register plus the displacement.

It is sent from the pace register in the DA unit and the IF unit 2. The displacement can be added by the DA unit 3. On the other hand, in memory indirect address calculation where the effective address is expressed by the following formula, EA=[IA] +X.

I A = A, +disp Here EA is the effective address A, is the base register disp is displacement X, is the index register [IA] is the memory value at address IA IA is the address for memory indirection.

The DA unit 3 calculates up to IA and sends it to the IAttE unit 4 (7) MAR 43. At the same time, the value of the register 401 of the control circuit 41 of the E unit 4 is set to "1", and the value of the register 410 is calculated according to the data length to be accessed. value,
In order to indicate that the MAR 43 contains valid data, the signal line 414 is set to ``1''. Also, the register 401 is set to 110'' in the case of direct access to the memory.

Here, memory direct addressing and memory indirect addressing are distinguished by where the effective address is created.Memory direct addressing is when the address becomes the effective address as it is, and memory indirect addressing is when the address is calculated by the DA unit. The address is not an effective address, but the contents of the memory specified by this address are the effective address. The key point of this embodiment is that the calculation of the effective address is performed by the E unit.

Now, part of the microprogram for a certain instruction is in the fourth
Assume that the situation is as shown in Figure (a). This flow is part of the flowchart for reading memory under a microprogram, and in step 101, a read is started from the memory, and the wait is performed until the result is returned (
102). E unit 4 and 1
01(7)? When trying to execute a macro instruction, 1
The 32-decimal bit pattern corresponding to 01 is the control memory 4.
It is read from 06 and held in -carrier 407.
There are 1. At this time, bit 424 of the microinstruction is.

Because it is a microinstruction that performs memory access.

Therefore, the value of the selection signal 418 to the selector 408 is 418 = (416 + 414) · 424 Here, is given by exclusive OR and is logical product, so 418 is “1” ″, and the selector is
A specific microinstruction stored in a register 409 as a control signal 48 to the arithmetic unit 42 is selected in place of the microinstruction held in 407 that should originally be executed. The microinstructions stored in the register 409 are shown in FIG.
This is an instruction to call the subroutine shown in b). Therefore, if the above conditions are met, microinstruction 10
1 will not be executed, but the microinstruction that calls (b) will be executed. (b) is from DA unit 3 to M
This is a microprogram that waits when no address is set in the AR 43 and determines whether the address set in the MAR 43 is an address for memory indirection.

And if you need to handle memory indirection.

The microprogram (c) in FIG. 4 that performs memory indirect address calculation is called.

According to this embodiment, when memory indirect address calculation is required, from the perspective of the microprogram (a) of the E unit 4, it appears as if an interrupt has occurred, and (a) is unaware of it. After the memory indirect address calculation microprograms (b) and (c) are executed, the next microinstruction 102 is executed. In addition, the instruction execution speed does not decrease when memory indirect address calculation is not required, and memory indirect addressing, which is an advanced form of addressing, does not affect the existing E unit 4 microprogram, and requires relatively little hardware. There is an effect that can be achieved with clothing.

〔Effect of the invention〕

According to the present invention, when implementing memory indirect addressing in a pipeline-configured computer that has an address calculation unit without a memory access function, a large amount of hardware such as adding a memory access function to the address calculation unit is required. Even when there is no increase and addressing other than memory indirect addressing is used, memory indirect address calculation can be performed without reducing the conventional execution speed.

[Brief explanation of drawings]

FIG. 1 is an embodiment diagram of a control circuit of the present invention, FIG. 2 is an overall configuration diagram of the present invention, and FIG. 3 is an operand fetch, operation (O
FIG. 4 is a flow chart showing the relationship between the F&E section and the memory. 4... E unit, 41... E unit control circuit,
401...Memory indirection instruction flag, 414...Memory address ready signal, 409...Specific instruction storage register, 410...Register indicating processing after memory indirection, 407...Microinstruction register, 408...
·selector.

Claims (1)

[Claims] 1. A main memory that stores instructions or data, an instruction read unit (referred to as an IF unit) that reads instructions from the main memory, and a decode and address that decodes the instruction and calculates the effective address of the operand of the instruction. a calculation unit (referred to as a DA unit); an instruction execution unit (E unit) that executes the instruction and reads or writes data to a portion of the main memory specified by the effective address according to a microprogram; DA);
The unit calculates a direct address or an indirect address, and the E unit sets the direct address or indirect address instruction from the DA unit as a flag, and when a direct address is specified, memory access is performed from the direct address as an effective address. , a data processing device that creates an effective address from the indirect address as an address for memory access when an indirect address is specified, and performs memory access using this effective address.