JPH0547787B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a test signal generation circuit for logic circuits, and more specifically, it is capable of changing the waveform width and timing of a test signal. This relates to a test signal generation circuit.

(b) Purpose of the Invention This invention enables the waveform width and timing of a test signal to be changed by controlling two counters with one reference signal and setting independent delay times for these counters. The present invention provides a test signal generation circuit with the following characteristics.

(c) Embodiment of the invention First, a configuration diagram of an embodiment of the invention will be shown in the first example.
As shown in the figure.

In FIG. 1, 1A and 1B are gates, 2A and 2B are setters, 3A and 3B are counters, 4 is a flip-flop, 11A and 11B are digital signals, 12 is a reference signal, 13 is a clock pulse, and 14 is a test signal.

1A and 1B, 2A and 2B, 3A and 3B in Figure 1
Since they are the same, the A side of FIG. 1 will be mainly explained below, and only the necessary parts of the B side will be explained.

The digital signal 11A and the digital signal 11B in FIG. 1 are composed of "1" and "0".

The reference signal 12 is the digital signal 11A, 11B.
The digital signals 11A and 11B are configured so that the repetition period is the same as the period of the reference signal 12.

A digital signal 11A and a reference signal 12 are input to the gate 1A, and when the digital signal 11A is "1", the reference signal 12 is transmitted to the counter 3A.

Clock pulse 13 is a signal having a shorter repetition period than reference signal 12, and is input to counter 3A and counter 3B.

The setter 2A is for setting the delay time on the counter 3A, and can be configured with a memory or the like, for example. Then, a setting value corresponding to the delay time is stored in advance from a CPU (not shown).

The set value corresponding to the first delay time is sent from the setter 2A to the counter 3A, and the set value corresponding to the first delay time is set in the counter 3A.

The counter 3A counts the clock pulses 13 by the set value, outputs a signal delayed by the first delay time from the reference signal 12, and sets the flip-flop 4.

For example, in order to set the first delay time to 9 μs when the period of the clock pulse 13 is 10 ns, the set value of the counter 3A may be set to 900.

A second delay time is also set in the counter 3B, and the counter 3B resets the flip-flop 4 with a signal delayed by the second delay time.

Therefore, flip-flop 4 is counter 3
A is set by the output of counter 3B, and is reset by the output of counter 3B to output test signal 14.

Note that the first delay time and the second delay time may be the same time or may be different times.

Next, the time chart shown in FIG. 1 is shown in FIG. 2.

FIG. 2A shows the waveform of the digital signal 11A, which changes from "1" to "0" to "1".

FIG. 2A shows the waveform of the digital signal 11B, which is an inverted waveform of the digital signal 11A.

FIG. 2C is a waveform diagram of the reference signal 12, and the second
Figure E is a waveform diagram of the clock pulse 13.

Figure 2 O is the reference signal 12 that the gate 1A outputs when the digital signal 11A in Figure 2 A is "1".
This is a waveform diagram of A1 in Fig. 2 E and A in Fig. 2 C.
corresponds to

Figure 2 F is an output waveform diagram of the counter 3A when the first delay time is set to T1 with the setting device 2A in Figure 1, and A2 in Figure 2 F is only T1 from A1 in Figure 2 E. It's a delayed signal.

Figure 2 (g) is the reference signal 1 output by the gate 1B when the digital signal 11B in Figure 2 (a) is "1".
2, and B1 in FIG. 2G corresponds to B in FIG. 2C.

In Fig. 2, the second delay time T is set using the setting device 2B.
This is an output waveform diagram of the counter 3B when set to 2, and B2 in FIG.
This is a delayed signal.

FIG. 2B is a waveform diagram of the test signal 14 output from the flip-flop 4 when the flip-flop 4 in FIG. 1 is set at A2 in FIG. 2F and reset at B2 in FIG.

Although only one period of the output waveform of the flip-flop 4 is displayed in FIG. obtained from the output.

(d) Effects of the Invention According to the present invention, since the first delay time is set in the counter 3A and the second delay time is set in the counter 3B, the clock pulses 13 are counted by the counters 3A and 3B. The width and timing of the test signal output by the flip-flop 4 can be easily changed.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an embodiment according to the present invention, and FIG.
The figure is the time chart shown in Figure 1. 1A...Gate, 1B...Gate, 2A...Setting device, 2B...Setting device, 3A...Counter, 3B
...Counter, 4...Flip-flop, 11A
...Digital signal, 11B...Digital signal, 12...Reference signal.

Claims (1)

[Claims] 1. A first setting device for setting a first delay time;
a first gate receiving a reference signal and a first digital signal; a first counter receiving a clock pulse and a first gate output and counting the clock pulses by a set value of a first setting device; a second setter for setting the second delay time; a second gate for receiving the reference signal and the second digital signal as input; a second setting device for setting the second delay time; A second counter that counts the clock pulses by a set value of the counter, and a flip-flop whose inputs are the output of the first counter and the output of the second counter, and the test signal is generated from the output of the flip-flop. test signal generation circuit.