JPH0545419A - Waveform forming circuit of semiconductor testing device - Google Patents

Abstract

PURPOSE:To enable a minimum interval between a set pulse and a reset pulse to be reduced. CONSTITUTION:A set pulse and a reset pulse from a waveform control circuit 11 within a semiconductor testing device are selected by a selector 21, the selector 21 selects the set pulse in initial state, and then a D-type flip flop 22 is triggered by falling of the output. A q output of the flip flop 22 is fed back to a data terminal D and the selector 21 is controlled by the q output. The q output is inverted by triggering of the flip flop 22 and the flip flop 22 is triggered by falling of a next reset pulse, thus enabling the Q output of the flip flop 22 to output pulses ranging from falling of the set pulse to that of the reset pulse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generates a pulse having corresponding edge intervals of a set pulse and a reset pulse for converting pattern data into various waveforms to be applied to an IC device under test in a semiconductor test apparatus. The present invention relates to a waveform shaping circuit.

[0002]

2. Description of the Related Art FIG. 2A shows a conventional waveform shaping circuit. Pattern data and a plurality of timing clocks are input to the waveform control circuit 11, and in response thereto, set pulses and reset pulses shown in, for example, a and b of FIG. 2B are output from the terminals 12 and 13, respectively. Is a corresponding one of the edges of the pulsars 14 and 15, respectively, which is a falling edge in FIG. 2B.
Each of the pulses is converted into a pulse having a constant width rising as indicated by c and d, the SR flip-flop 16 is set by the output pulse of the pulser 14, and the SR flip-flop 16 is reset by the output pulse of the pulser 15, and the SR flip-flop is reset. From the Q output of 16 as shown in FIG. 2Be,
A pulse having a pulse width from the falling edge of the set pulse to the falling edge of the reset pulse is output, and this pulse is supplied to one pin of the IC device under test (not shown) through the driver 17.

[0003]

As shown in the right half of FIG. 2B, when the set pulse and the reset pulse are close to each other and the interval between the compatible falling edges is smaller than the pulse width P _W of the pulse output from the pulser 14. , SR flip-flop 1
6 is set and controlled at the rear of the output pulse of the pulser 14,
In addition, the state 18 under reset control occurs at the front of the output pulse of the pulser 15, and the output becomes uncertain in this state.

The pulse width of each output pulse of the pulsars 14 and 15, that is, the minimum pulse width with which the SR flip-flop 16 is controlled is the P _W pulser 14 and 15 operation variation is α,
_Assuming that the delay of the SR flip-flop 16 is T _pd , the minimum interval between the set pulse and the reset pulse is P _W + P _W
It becomes α + T _pd . For example, P _W = 3 nS, α = 0.5-
1.5 and T _pd = 1 nS, the minimum interval is 3.0 nS
× 1.5 / 0.5 + 1nS = 10nS, which was relatively large. In the semiconductor test apparatus, the smaller the minimum interval, the more accurate the test can be performed, that is, the performance is improved.

An object of the present invention is to provide a waveform shaping circuit which can make the minimum interval between a set pulse and a reset pulse smaller than before.

[0006]

According to the present invention, a set pulse and a reset pulse are supplied to a selector, one of them is selectively output, and an edge of the output pulse triggers a D-type flip-flop, The inverted output of the D-type flip-flop is fed back to its data terminal, one output of the D-type flip-flop is supplied to the selector as a control signal, and one output is output as an output pulse.

[0007]

FIG. 1A shows an embodiment of the present invention, in which parts corresponding to those in FIG. 2A are designated by the same reference numerals. Waveform control circuit 1
The set pulse and the reset pulse from the first terminals 12 and 13 are supplied to the selector 21, respectively, and the selector 21 outputs one of the both input pulses according to the control signal.
On one edge of the output pulse of the selector 21, the falling edge in this example, the D flip-flop 22 is triggered. Inverted output of D-type flip-flop 22, that is, q
The output is fed back to the data terminal D of the D-type flip-flop 22 to form a toggle-type flip-flop.
Further, one output of the D-type flip-flop 22, q output in this example, is supplied to the selector 21 as a control signal.

According to this structure, when a set pulse and a reset pulse are output from the terminals 12 and 13, for example, as shown in FIGS.
1 has a high level "1" as shown in FIG. 1Bc, and the selector 21 selects the set pulse. Therefore, the set pulse passes through the selector 21, its falling edge triggers the flip-flop 22, the Q output of the flip-flop 22 rises, and the q output thereof falls. Therefore, the selector 21 comes to select the reset pulse.

The reset pulse at the terminal 13 is the selector 21.
And the falling edge thereof triggers the flip-flop 22 to take a low level into the flip-flop 22, and its Q output becomes low level and q output becomes high level.
Thus, as shown in FIG. 1Be, a pulse having a pulse width from the falling edge of the set pulse to the falling edge of the reset pulse is obtained from the Q output of the flip-flop 22.

As shown in the right half of FIG. 1B, even when the set pulse and the reset pulse are close to each other, the falling edge of the set pulse triggers the flip-flop 22 and the q output of the flip-flop 22 becomes low level. If the falling edge of the reset pulse is input after the selector 21 has been inverted and the reset pulse is selected by the low level of the q output, this circuit operates normally. That is, as shown in FIG. 1Bd, the falling edge of the reset pulse may come after the low-level section 23 occurs in the q output based on the falling edge of the set pulse.

In this configuration, the flip-flop 22
Is the width T _{p of the} clock pulse required to capture the data,
The sum of the minimum time T _h for holding the data after the flip-flop 22 is triggered is the minimum interval between the set pulse and the reset pulse, for example, T _p = 3 nS,
When T _h = 1 nS, the minimum interval is 4 nS, and the minimum interval between the set pulse and the reset pulse can be reduced to half or less as compared with the conventional circuit shown in FIG. 2A.

In the above description, the q output of the flip-flop 22 may be taken out as the pulse output. Further, the flip-flop 22 may be triggered at each rising edge of the set pulse and the reset pulse.

[0013]

As described above, according to the present invention, the q output of the D flip-flop is fed back to the data terminal D to be a toggle flip flop, and the D flip flop is triggered by the edge of the set pulse. After that, since it is configured to trigger at the edge of the reset pulse, the interval between the set pulse and the reset pulse can be made narrower than in the past, and the performance of the semiconductor test apparatus can be improved accordingly.

[Brief description of drawings]

FIG. 1A is a circuit diagram showing an embodiment of the present invention, and B is a time chart showing an operation example thereof.

FIG. 2A is a circuit diagram showing a conventional waveform shaping circuit, and B is a time chart showing its operation.

Claims (1)

[Claims] 1. A waveform shaping circuit of a semiconductor test apparatus for generating a pulse from one edge of a set pulse to a corresponding edge of a reset pulse, the set pulse and the reset pulse being supplied,
A selector that selects and outputs one of them, is triggered by the edge of the output of that selector, the inverted output is fed back to the data terminal, one output is supplied to the above selector as a control signal, and one output is pulse output And a D-type flip-flop, and a waveform shaping circuit of a semiconductor testing device.