JPS62284518A - Integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a desired delay time by providing a delay circuit constituted by connecting plural logic elements in series and a control circuit which selects outputs of the respective logic elements. CONSTITUTION:This integrated circuit incorporates the delay circuit 1 constituted by connecting plural logic elements 11-1n in series, a counter 2 which counts input pulses supplied to the delay circuit 1, and the selecting circuit 3 which selects the output pulses of the logic elements 11-1n. A figure shows that the time Td from the trailing edge to the leading edge of the output (o) of a monostable multivibrator when the monostable multivibrator is connected between the selecting circuit 3 and delay circuit 1 is equal to the sum of delay times of the logic elements 11-1m. This time Td is found from the counted value of the counter 2 within a specific time, so the logic elements 11-1m are so selected that the time has a desired value. Consequently, the desired delay time Td is obtained.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] A delay circuit configured by connecting a plurality of logic elements in series in an integrated circuit such as a high-density integrated circuit (LSI), and each logic element. A desired delay time can be obtained by providing a control circuit that selects the output of the delay time.

[Industrial application field]

The present invention relates to improvements in integrated circuits.

For example, four types of control signals are used to control reading and writing of memory: a row address strobe signal (RAS), a column address strobe signal (CAS), a write enable signal (WE), and an output enable signal (OE). The memory control/control circuit for creating is usually 9,1
integrated into individual high-density integrated circuits.

By the way, for these control signals, the minimum value determined in consideration of the characteristics of the memory to be controlled is determined as the allowable limit value for each control signal itself and the on/off timing □ between each control signal. It is being

Furthermore, in memory control, it is particularly important to shorten access time. Therefore, when designing a memory control circuit, these timings are brought as close as possible to the allowable limits so that a series of controls can be performed in the shortest possible time.

On the other hand, a clock is used to control these timings, and if the period of the clock is, for example, 50n3, a signal with a pulse width of 50 ns can be generated directly from the clock.

However, to create a signal with a pulse width of 60n3, for example, you need to create a signal with a pulse width of 50ns and a signal with a pulse width of 10n3.
A method is used in which a signal delayed by n3 is generated and the logical sum of the two signals is calculated.

To serve such applications, high-density integrated circuits often use delay circuits to create a desired delay.

At this time, as described above, it is very important to obtain an accurate delay time in order to bring the timing of the control signal as close to the allowable limit as possible.

[Conventional technology]

When a precise time unit delay time is required inside a high-density integrated circuit, conventionally, for example, the delay time is l ns
A method has been adopted in which a plurality of front and rear logic elements connected in series are provided inside a high-density integrated circuit (first conventional example) or externally (second conventional example).

[Problem that the invention seeks to solve]

In the first conventional example, it is necessary to give a considerable tolerance limit to one delay time in consideration of product variations, temperature changes, etc., and it cannot be applied to high-speed memory control circuits and the like.

Further, in the second conventional example, it has been an obstacle to miniaturization and cost reduction of the dual-purpose device.

That is, an object of the present invention is to provide an integrated circuit with a built-in delay circuit that passes through a high-speed memory control circuit.

(Means for Solving Problems) As shown in the principle diagram of FIG. 1, the integrated circuit according to the present invention includes a delay circuit 1 configured by connecting a plurality of logic elements 11 to 1n in series, 1, and a selection circuit 3 for selecting output pulses from each of a plurality of logic elements 11 to 1n.

[Effect]

Figure 2 shows the output (0) of the monostable multivibrator and the outputs (1) to (m This is a time chart showing the relationship between There is.

“This time Td can be obtained from the count value of the counter 2 within a predetermined time, so by selecting the outputs of the logic elements 11 to 1m so that this becomes the desired value, the desired delay time Td can be obtained. Obtainable.

〔Example〕

FIG. 3 is a block diagram of an embodiment of the present invention, in which the first logic element 11 of the delay circuit 1 is an OR discard, and the subsequent logic elements 12
~1n+ is an AND element.

When the monostable multivibrator 4 is started by inputting a starting pulse through the OR circuit 5.

The generated signal with a predetermined pulse width is input to the delay circuit 1, and after being delayed in the delay circuit 1, is input to the monostable multivibrator 4, and continuous pulses tO) at regular intervals are generated.

This is counted by a counter 2, a delay time is calculated from the count value by firmware (not shown) provided externally, and a selection circuit 3 is controlled by a control circuit (not shown) also provided externally, so that the desired delay time is determined. The outputs of the logic elements 11 to 1m are selected so as to obtain the desired result.

This is done at appropriate times such as when the device is powered on or during operation, and after the desired delay time is obtained, the monostable multi-bi break 4 is stopped and the delay created by the delay circuit 1 and the selection circuit 3 is transferred to the internal circuit 6. Use with. - Since the delay time in each logic element 11 to 1m is about 103, the desired delay time can be created with an accuracy of about 1 ns.

Therefore, it is possible to compensate for variations in timing of control signals due to product variations in high-density integrated circuits, temperature changes, etc. with high accuracy.

〔Effect of the invention〕

As explained above, in the high-density integrated circuit according to the present invention, a desired delay time can be created with high precision. Therefore, in a memory control circuit, for example, the timing of the control signal can be brought closer to the permissible limit, and a great effect can be obtained in shortening the access time.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention. FIG. 2 is an explanatory diagram of the action. FIG. 3 is a configuration diagram of the embodiment. In the figure. 1 is a delay circuit, and 11 to 1n are logic elements. 2 is a counter, 3 is a selection circuit. 4 refers to a monostable multibibreak. Figure 1 (island Diagram of action Figure 2 Figure 3

Claims (1)

[Scope of Claims] A delay circuit (1) configured by connecting a plurality of logic elements (11 to 1n) in series; a counter (2) that counts input pulses applied to the delay circuit (1); An integrated circuit comprising: a selection circuit (3) for selecting an output pulse of each of the plurality of logic elements (11 to 1n).