JPH054703B2 - - Google Patents

Info

Publication number
JPH054703B2
JPH054703B2 JP61063663A JP6366386A JPH054703B2 JP H054703 B2 JPH054703 B2 JP H054703B2 JP 61063663 A JP61063663 A JP 61063663A JP 6366386 A JP6366386 A JP 6366386A JP H054703 B2 JPH054703 B2 JP H054703B2
Authority
JP
Japan
Prior art keywords
channel
request
control unit
micro
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61063663A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62247443A (ja
Inventor
Seiichi Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6366386A priority Critical patent/JPS62247443A/ja
Publication of JPS62247443A publication Critical patent/JPS62247443A/ja
Publication of JPH054703B2 publication Critical patent/JPH054703B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP6366386A 1986-03-20 1986-03-20 チヤネル制御方式 Granted JPS62247443A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6366386A JPS62247443A (ja) 1986-03-20 1986-03-20 チヤネル制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6366386A JPS62247443A (ja) 1986-03-20 1986-03-20 チヤネル制御方式

Publications (2)

Publication Number Publication Date
JPS62247443A JPS62247443A (ja) 1987-10-28
JPH054703B2 true JPH054703B2 (enrdf_load_html_response) 1993-01-20

Family

ID=13235807

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6366386A Granted JPS62247443A (ja) 1986-03-20 1986-03-20 チヤネル制御方式

Country Status (1)

Country Link
JP (1) JPS62247443A (enrdf_load_html_response)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5920031A (ja) * 1982-07-23 1984-02-01 Nec Corp デ−タ転送装置
JPS59172030A (ja) * 1983-03-22 1984-09-28 Fujitsu Ltd デ−タチヤネル制御方式
JPS59189430A (ja) * 1983-04-13 1984-10-27 Nec Corp 割込み制御方式

Also Published As

Publication number Publication date
JPS62247443A (ja) 1987-10-28

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