JPS6229831B2 - - Google Patents

Info

Publication number
JPS6229831B2
JPS6229831B2 JP21797982A JP21797982A JPS6229831B2 JP S6229831 B2 JPS6229831 B2 JP S6229831B2 JP 21797982 A JP21797982 A JP 21797982A JP 21797982 A JP21797982 A JP 21797982A JP S6229831 B2 JPS6229831 B2 JP S6229831B2
Authority
JP
Japan
Prior art keywords
input
dma
output
register
data transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP21797982A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59108134A (ja
Inventor
Hajime Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP21797982A priority Critical patent/JPS59108134A/ja
Publication of JPS59108134A publication Critical patent/JPS59108134A/ja
Publication of JPS6229831B2 publication Critical patent/JPS6229831B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP21797982A 1982-12-13 1982-12-13 入出力制御方式 Granted JPS59108134A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21797982A JPS59108134A (ja) 1982-12-13 1982-12-13 入出力制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21797982A JPS59108134A (ja) 1982-12-13 1982-12-13 入出力制御方式

Publications (2)

Publication Number Publication Date
JPS59108134A JPS59108134A (ja) 1984-06-22
JPS6229831B2 true JPS6229831B2 (enrdf_load_html_response) 1987-06-29

Family

ID=16712722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21797982A Granted JPS59108134A (ja) 1982-12-13 1982-12-13 入出力制御方式

Country Status (1)

Country Link
JP (1) JPS59108134A (enrdf_load_html_response)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4780813A (en) * 1985-02-25 1988-10-25 Itt Corporation Data transport control apparatus
AU1671688A (en) * 1987-06-03 1988-12-08 Honeywell Bull Inc. Peripheral controller and adapter interface

Also Published As

Publication number Publication date
JPS59108134A (ja) 1984-06-22

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