JPH0544049B2 - - Google Patents

Info

Publication number
JPH0544049B2
JPH0544049B2 JP58502792A JP50279283A JPH0544049B2 JP H0544049 B2 JPH0544049 B2 JP H0544049B2 JP 58502792 A JP58502792 A JP 58502792A JP 50279283 A JP50279283 A JP 50279283A JP H0544049 B2 JPH0544049 B2 JP H0544049B2
Authority
JP
Japan
Prior art keywords
instruction
address
instructions
register
branch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58502792A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59501426A (ja
Inventor
Deiuitsudo Rojaa Deitozeru
Fubaato Rae Junya Matsukuriran
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Technologies Inc filed Critical AT&T Technologies Inc
Publication of JPS59501426A publication Critical patent/JPS59501426A/ja
Publication of JPH0544049B2 publication Critical patent/JPH0544049B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
JP58502792A 1982-08-23 1983-07-22 次段アドレスの計算を前もつて実行する機構 Granted JPS59501426A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US41043082A 1982-08-23 1982-08-23
US410430FREGB 1982-08-23

Publications (2)

Publication Number Publication Date
JPS59501426A JPS59501426A (ja) 1984-08-09
JPH0544049B2 true JPH0544049B2 (OSRAM) 1993-07-05

Family

ID=23624698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58502792A Granted JPS59501426A (ja) 1982-08-23 1983-07-22 次段アドレスの計算を前もつて実行する機構

Country Status (6)

Country Link
EP (2) EP0411679B1 (OSRAM)
JP (1) JPS59501426A (OSRAM)
CA (1) CA1193738A (OSRAM)
DE (2) DE3382250D1 (OSRAM)
GB (1) GB2126384B (OSRAM)
WO (1) WO1984000833A1 (OSRAM)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0190484A3 (en) * 1985-01-28 1988-09-21 Data General Corporation Enhanced speed digital computer and method of speed enhancement
CA1250667A (en) * 1985-04-15 1989-02-28 Larry D. Larsen Branch control in a three phase pipelined signal processor
CA1254661A (en) * 1985-06-28 1989-05-23 Allen J. Baum Method and means for instruction combination for code compression
US5101341A (en) * 1988-08-25 1992-03-31 Edgcore Technology, Inc. Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
US5131086A (en) * 1988-08-25 1992-07-14 Edgcore Technology, Inc. Method and system for executing pipelined three operand construct

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL262931A (OSRAM) * 1960-03-29
US3764988A (en) * 1971-03-01 1973-10-09 Hitachi Ltd Instruction processing device using advanced control system
FR2226079A5 (OSRAM) * 1973-04-13 1974-11-08 Honeywell Bull Soc Ind
US3900835A (en) * 1973-09-24 1975-08-19 Digital Equipment Corp Branching circuit for microprogram controlled central processor unit
US3961313A (en) * 1974-12-04 1976-06-01 International Business Machines Corporation Computer control apparatus
US4210960A (en) * 1977-09-02 1980-07-01 Sperry Corporation Digital computer with overlapped operation utilizing conditional control to minimize time losses
US4200927A (en) * 1978-01-03 1980-04-29 International Business Machines Corporation Multi-instruction stream branch processing mechanism
US4298927A (en) * 1978-10-23 1981-11-03 International Business Machines Corporation Computer instruction prefetch circuit
US4323967A (en) * 1980-04-15 1982-04-06 Honeywell Information Systems Inc. Local bus interface for controlling information transfers between units in a central subsystem
US4371928A (en) * 1980-04-15 1983-02-01 Honeywell Information Systems Inc. Interface for controlling information transfers between main data processing systems units and a central subsystem

Also Published As

Publication number Publication date
EP0116600A1 (en) 1984-08-29
EP0411679B1 (en) 1996-05-01
WO1984000833A1 (en) 1984-03-01
GB2126384A (en) 1984-03-21
DE3382805D1 (de) 1996-06-05
DE3382805T2 (de) 1996-09-26
EP0411679A3 (en) 1991-07-10
CA1193738A (en) 1985-09-17
EP0411679A2 (en) 1991-02-06
EP0116600B1 (en) 1991-04-10
EP0116600A4 (en) 1987-08-12
JPS59501426A (ja) 1984-08-09
DE3382250D1 (de) 1991-05-16
GB8322134D0 (en) 1983-09-21
GB2126384B (en) 1986-03-19

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