JPH05327144A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH05327144A JPH05327144A JP4080153A JP8015392A JPH05327144A JP H05327144 A JPH05327144 A JP H05327144A JP 4080153 A JP4080153 A JP 4080153A JP 8015392 A JP8015392 A JP 8015392A JP H05327144 A JPH05327144 A JP H05327144A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit device
- heat dissipation
- substrate
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は混成集積回路装置に関
し、特に有機基板上にＩＣチップ等を搭載する表面実装
型の混成集積回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device, and more particularly to a surface mount type hybrid integrated circuit device in which an IC chip or the like is mounted on an organic substrate.
【０００２】[0002]
【従来の技術】従来の有機基板上にＩＣチップ等を搭載
する表面実装型の混成集積回路装置の構造は図３を参照
し説明すると、ガラスエポキシ基板１に座ぐりが形成さ
れ座ぐり上にＩＣチップ６が接着樹脂５により接着・搭
載されている。金線又はアルミ線７でＩＣチップ６と有
機基板上の導体２が電気的に接続され、樹脂封止８によ
り、ＩＣチップ６と金線又はアルミ線７が保護されてい
る。2. Description of the Related Art The structure of a conventional surface mount type hybrid integrated circuit device in which an IC chip or the like is mounted on an organic substrate will be described with reference to FIG. The IC chip 6 is bonded and mounted with the adhesive resin 5. The IC chip 6 and the conductor 2 on the organic substrate are electrically connected by the gold wire or the aluminum wire 7, and the IC chip 6 and the gold wire or the aluminum wire 7 are protected by the resin sealing 8.
【０００３】主基板１１との接続はガラスエポキシ基板
１に半円型の金メッキされた電極２を設けてあり、その
電極と主基板１１にあらかじめ形成された搭載用ランド
１０に実装する事により行う。Connection with the main board 11 is made by providing a semi-circular gold-plated electrode 2 on a glass epoxy board 1 and mounting the electrode on a mounting land 10 formed in advance on the main board 11. ..
【０００４】図３（Ａ）は従来の有機基板表面実装型混
成集積回路装置の断面図である。又、図３（Ｂ）は、外
形を表わした斜視図である。樹脂封止用の枠４は基板保
護体３の上に実装する。主基板１１への実装は半田９を
用いて実装する。FIG. 3A is a sectional view of a conventional organic substrate surface mounting type hybrid integrated circuit device. Further, FIG. 3B is a perspective view showing the outer shape. The resin-sealing frame 4 is mounted on the substrate protector 3. The main board 11 is mounted using solder 9.
【０００５】[0005]
【発明が解決しようとする課題】従来の有機基板表面実
装型混成集積回路装置は、セラミック基板等に比較し、
放熱性が悪い為、ＩＣチップの内部発熱が低く抑えられ
る回路にしか使用出来ないという使用上の制約があっ
た。The conventional organic substrate surface mounting type hybrid integrated circuit device has a
Since the heat dissipation is poor, there is a restriction in use that it can be used only in a circuit that can suppress the internal heat generation of the IC chip.
【０００６】[0006]
【課題を解決するための手段】本発明の有機基板上にＩ
Ｃチップ等を搭載する表面実装型の混成集積回路装置
は、混成集積回路装置を実装する主基板と電気的接続を
する電極パターン以外に半田で接続する放熱用のパター
ンを備えている。Means for Solving the Problems I on the organic substrate of the present invention
A surface-mount type hybrid integrated circuit device having a C chip or the like is provided with a heat radiation pattern to be connected by solder in addition to an electrode pattern for electrical connection with a main board on which the hybrid integrated circuit device is mounted.
【０００７】[0007]
【実施例】次に本発明について図面を参照して説明す
る。図１は本発明実施例（１）の断面図である。有機基
板（ガラスエポキシ基板）１に座ぐりを設け、ＩＣチッ
プを接着樹脂５により接着・搭載し、Ａｕ又はアルミ線
７によりガラスエポキシ基板１に設けられた導体（電極
パターン）２に電気的接続をする。保護体３上にあらか
じめ搭載された樹脂枠４の内部を樹脂８で封止する。１
２はガラスエポキシ基板裏面に設けた放熱用接続パター
ンである。上述の混成集積回路装置の主基板１１への実
装は、図１に示すように、半田９により行う。主基板１
１上に形成された接続ランド１０と、電極パターン２，
放熱用接続パターン１２を半田９で各々接続し実装す
る。The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of an embodiment (1) of the present invention. A counterbore is provided on an organic substrate (glass epoxy substrate) 1, an IC chip is bonded and mounted with an adhesive resin 5, and an electrical connection is made with a conductor (electrode pattern) 2 provided on the glass epoxy substrate 1 by Au or an aluminum wire 7. do. The inside of the resin frame 4 previously mounted on the protector 3 is sealed with the resin 8. 1
Reference numeral 2 is a heat radiation connection pattern provided on the back surface of the glass epoxy substrate. The above-mentioned hybrid integrated circuit device is mounted on the main substrate 11 by solder 9 as shown in FIG. Main board 1
1, the connection land 10 and the electrode pattern 2,
The heat-dissipating connection patterns 12 are connected and mounted by solder 9 respectively.
【０００８】主基板１１と放熱用接続パターン１２を接
続する事により、混成集積回路装置を動作させた際の発
熱が主基板にも放熱される為、温度上昇が軽減される。By connecting the main board 11 and the heat dissipation connection pattern 12, the heat generated when the hybrid integrated circuit device is operated is also radiated to the main board, so that the temperature rise is reduced.
【０００９】図２は本発明実施例（２）の断面図であ
る。有機基板（ガラスエポキシ基板）１に座ぐりを設け
ＩＣチップ６を接着樹脂５により接着・搭載し、Ａｕ又
はアルミ線７によりガラスエポキシ基板１に設けられた
導体（電極パターン）２に電気的接続をする。保護体３
上にあらかじめ搭載された樹脂枠４の内部を樹脂８で封
止する。１２は放熱用接続パターンである。この実施例
では、ガラスエポキシ基板１の放熱用接続パターン１２
が形成される部分は座ぐりが設けられている。その他は
先の実施例と同じである。FIG. 2 is a sectional view of the embodiment (2) of the present invention. A counterbore is provided on an organic substrate (glass epoxy substrate) 1 to bond and mount an IC chip 6 with an adhesive resin 5, and an electrical connection is made to a conductor (electrode pattern) 2 provided on the glass epoxy substrate 1 with Au or an aluminum wire 7. do. Protector 3
The inside of the resin frame 4 previously mounted above is sealed with the resin 8. Reference numeral 12 is a heat dissipation connection pattern. In this embodiment, the heat dissipation connection pattern 12 of the glass epoxy substrate 1 is used.
A counterbore is provided in the portion where the is formed. Others are the same as in the previous embodiment.
【００１０】上述の混成集積回路装置の主基板１１への
実装は、半田９により行う。主基板１１上に形成された
接続ランド１０と、電極パターン２、放熱用接続パター
ン２を半田９により各々接続し、実装する。この実施例
の放熱用パターン１２は、ガラスエポキシを基板の座ぐ
りを設けた部分に形成してあり、発熱源のＩＣチップ６
に近い為、先の実施例よりも放熱効果が良い。The above-mentioned hybrid integrated circuit device is mounted on the main substrate 11 by solder 9. The connection land 10 formed on the main board 11, the electrode pattern 2, and the heat dissipation connection pattern 2 are connected by solder 9 and mounted. The heat dissipation pattern 12 of this embodiment is formed of glass epoxy on the portion of the substrate where the counterbore is provided, and the IC chip 6 of the heat source is formed.
Therefore, the heat radiation effect is better than that of the previous embodiment.
【００１１】[0011]
【発明の効果】以上説明したように本発明は、裏面に設
けられた接続パターンと、主基板とを半田で接続する様
にしたことにより、搭載部品の発熱を主基板側に放熱出
来る為、裏面の放熱性は、従来に対して実施例（１）で
は大幅に改善された、さらに実施例（２）では有機基板
の厚みを約半分にした場合は実施例（１）よりも約３０
％放熱性が改善されるという効果を有する。As described above, according to the present invention, since the connection pattern provided on the back surface and the main board are connected by solder, the heat of the mounted components can be radiated to the main board side. The heat dissipation on the back surface was significantly improved in Example (1) as compared with the conventional one, and in Example (2), when the thickness of the organic substrate was reduced to about half, it was about 30 compared to Example (1).
% This has the effect of improving heat dissipation.
【図１】本発明実施例（１）の断面図。FIG. 1 is a sectional view of an embodiment (1) of the present invention.
【図２】実施例（２）の断面図。FIG. 2 is a sectional view of Example (2).
【図３】従来装置の構造図であり、（Ａ）は断面図、
（Ｂ）は外形の斜視図。FIG. 3 is a structural view of a conventional device, (A) is a sectional view,
(B) is a perspective view of the outer shape.
１ 有機基板（ガラスエポキシ樹脂等） ２ 電極パターン ３ 保護体（絶縁樹脂） ４ 樹脂枠 ５ 接着樹脂 ６ ＩＣチップ ７ Ａｕ又はアルミ線 ８ 樹脂 ９ 半田 １０ 接続ランド １１ 主基板 １２ 放熱用接続パターン 1 Organic Substrate (Glass Epoxy Resin etc.) 2 Electrode Pattern 3 Protective Body (Insulating Resin) 4 Resin Frame 5 Adhesive Resin 6 IC Chip 7 Au or Aluminum Wire 8 Resin 9 Solder 10 Connection Land 11 Main Board 12 Heat Dissipation Connection Pattern
Claims (1)
プ等を搭載した表面実装型の混成集積回路装置におい
て、混成集積回路装置を実装する主基板と接続する放熱
用のパターンを前記有機基板の裏面に備えた事を特徴と
する混成集積回路装置。1. In a surface-mount type hybrid integrated circuit device in which an IC chip or the like is mounted on an organic substrate having electric wiring, a heat radiation pattern for connecting to a main substrate on which the hybrid integrated circuit device is mounted is provided on the organic substrate. A hybrid integrated circuit device characterized by being provided on the back surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4080153A JP2730388B2 (en) | 1992-04-02 | 1992-04-02 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4080153A JP2730388B2 (en) | 1992-04-02 | 1992-04-02 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05327144A true JPH05327144A (en) | 1993-12-10 |
| JP2730388B2 JP2730388B2 (en) | 1998-03-25 |
Family
ID=13710356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4080153A Expired - Lifetime JP2730388B2 (en) | 1992-04-02 | 1992-04-02 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2730388B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006216674A (en) * | 2005-02-02 | 2006-08-17 | Sharp Corp | Printed circuit with improved heat dissipation performance and circuit module comprising the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0263146A (en) * | 1988-08-29 | 1990-03-02 | Hitachi Ltd | Radiating structure of heat-generating component mounted on printed-circuit board |
| JPH0442989A (en) * | 1990-06-06 | 1992-02-13 | Ibiden Co Ltd | Electronic component placing board and manufacture thereof |
| JP3038653U (en) * | 1996-12-10 | 1997-06-24 | 認 小松 | Beer automatic volume selling device |
-
1992
- 1992-04-02 JP JP4080153A patent/JP2730388B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0263146A (en) * | 1988-08-29 | 1990-03-02 | Hitachi Ltd | Radiating structure of heat-generating component mounted on printed-circuit board |
| JPH0442989A (en) * | 1990-06-06 | 1992-02-13 | Ibiden Co Ltd | Electronic component placing board and manufacture thereof |
| JP3038653U (en) * | 1996-12-10 | 1997-06-24 | 認 小松 | Beer automatic volume selling device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006216674A (en) * | 2005-02-02 | 2006-08-17 | Sharp Corp | Printed circuit with improved heat dissipation performance and circuit module comprising the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2730388B2 (en) | 1998-03-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19971118 |