JPH05190586A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05190586A JPH05190586A JP4004286A JP428692A JPH05190586A JP H05190586 A JPH05190586 A JP H05190586A JP 4004286 A JP4004286 A JP 4004286A JP 428692 A JP428692 A JP 428692A JP H05190586 A JPH05190586 A JP H05190586A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- semiconductor chip
- wire bonding
- wire
- chip mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＰＧＡやＬＣＣ、ＱＦ
ＰなどＩＣ等の半導体装置に関するものである。The present invention relates to PGA, LCC, QF
The present invention relates to a semiconductor device such as IC such as P.
【０００２】[0002]
【従来の技術】プリント配線板などで形成される基板１
にＩＣチップ等の半導体チップ６を実装して半導体装置
を作成するにあたって、図４に示すような基板１が使用
されている。この基板１の表面には半導体チップ搭載部
２が金属箔や金属メッキなどで設けてあり、半導体チッ
プ搭載部２の周囲において多数のワイヤーボンディング
パッド３，３…が金属箔や金属メッキなどで設けてあ
る。各ワイヤーボンディングパッド３は基板１に設けら
れる回路に接続されている。そして図３に示すように半
導体チップ搭載部２の上に半導体チップ６を搭載し、半
導体チップ６に設けた多数の各電極７と各ワイヤーボン
ディングパッド３との間に金線等のワイヤー８をボンデ
ィングすることによって、半導体チップ６をワイヤーボ
ンディングパッド３を介して基板１の回路に接続するこ
とができるものであり、このようにして基板１に半導体
チップ６を実装して半導体装置を作成することができる
ものである。2. Description of the Related Art Substrate 1 formed of a printed wiring board or the like
A substrate 1 as shown in FIG. 4 is used when a semiconductor device is produced by mounting a semiconductor chip 6 such as an IC chip on the substrate. A semiconductor chip mounting portion 2 is provided on the surface of the substrate 1 by metal foil or metal plating, and a large number of wire bonding pads 3, 3 ... Are provided by metal foil or metal plating around the semiconductor chip mounting portion 2. There is. Each wire bonding pad 3 is connected to a circuit provided on the substrate 1. Then, as shown in FIG. 3, the semiconductor chip 6 is mounted on the semiconductor chip mounting portion 2, and wires 8 such as gold wires are provided between the respective electrodes 7 and the wire bonding pads 3 provided on the semiconductor chip 6. By bonding, the semiconductor chip 6 can be connected to the circuit of the substrate 1 through the wire bonding pad 3. In this way, the semiconductor chip 6 is mounted on the substrate 1 to form a semiconductor device. Can be done.
【０００３】[0003]
【発明が解決しようとする課題】しかし、図３にみられ
るように、半導体チップ６の電極７とワイヤーボンディ
ングパッド３との間にボンディングされるワイヤー８の
本数が多いために、ワイヤーボンディングパッド３への
ワイヤー８のボンディング密度が高くなって、ワイヤー
ボンディングの歩留りが悪いという問題があった。However, as shown in FIG. 3, since the number of wires 8 bonded between the electrode 7 of the semiconductor chip 6 and the wire bonding pad 3 is large, the wire bonding pad 3 is formed. There is a problem that the bonding density of the wires 8 to the wire is increased and the yield of wire bonding is poor.
【０００４】本発明は上記の点に鑑みてなされたもので
あり、ワイヤーボンディングの歩留りを高くすることが
でき、加えて電気特性を向上させることもできる半導体
装置を提供することを目的とするものである。The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device capable of increasing the yield of wire bonding and also improving the electrical characteristics. Is.
【０００５】[0005]
【課題を解決するための手段】本発明に係る半導体装置
は、基板１の表面にチップ搭載部２を設けると共にチッ
プ搭載部２の周囲に多数のワイヤーボンディングパッド
３を設け、このチップ搭載部２とワイヤーボンディング
パッド３の間において基板１の表面にチップ搭載部２を
囲む回路４を設け、回路４の一部を露出させて回路４の
表面に絶縁被膜５を被覆し、チップ搭載部２の上に半導
体チップ６を搭載し、半導体チップ６の電極７とワイヤ
ーボンディングパッド３とを絶縁被覆５の上を通過する
ワイヤー８で接続すると共に半導体チップ６の電極７と
回路４の露出部４ａとをワイヤー８で接続して成ること
を特徴とするものである。In a semiconductor device according to the present invention, a chip mounting portion 2 is provided on a surface of a substrate 1 and a large number of wire bonding pads 3 are provided around the chip mounting portion 2, and the chip mounting portion 2 is provided. The circuit 4 surrounding the chip mounting portion 2 is provided on the surface of the substrate 1 between the wire bonding pad 3 and the wire bonding pad 3, and a part of the circuit 4 is exposed to cover the surface of the circuit 4 with the insulating film 5. A semiconductor chip 6 is mounted on the semiconductor chip 6, and the electrode 7 of the semiconductor chip 6 and the wire bonding pad 3 are connected by a wire 8 passing over the insulating coating 5, and the electrode 7 of the semiconductor chip 6 and the exposed portion 4a of the circuit 4 are connected to each other. Is connected by a wire 8.
【０００６】[0006]
【作用】チップ搭載部２とワイヤーボンディングパッド
３の間において基板１の表面にチップ搭載部２を囲む回
路４を設け、半導体チップ６の電極７と回路４の露出部
４ａとをワイヤー８で接続しているために、半導体チッ
プ６の電極７とワイヤーボンディングパッド３との間に
ボンディングされるワイヤー８の本数がその分少なくな
る。半導体チップ６の電極７とワイヤーボンディングパ
ッド３とは回路４に被覆した絶縁被覆５の上を通過する
ワイヤー８で接続するようにしているために、このワイ
ヤー８が回路４に接触して短絡等が発生することを防止
できる。半導体チップ６の電極７と回路４は近接してい
るために、この両者を接続するワイヤー８は短くなって
抵抗値等の電気特性が向上する。The circuit 4 surrounding the chip mounting portion 2 is provided on the surface of the substrate 1 between the chip mounting portion 2 and the wire bonding pad 3, and the electrode 7 of the semiconductor chip 6 and the exposed portion 4a of the circuit 4 are connected by the wire 8. Therefore, the number of wires 8 bonded between the electrode 7 of the semiconductor chip 6 and the wire bonding pad 3 is reduced accordingly. Since the electrode 7 of the semiconductor chip 6 and the wire bonding pad 3 are connected by the wire 8 passing over the insulating coating 5 covering the circuit 4, the wire 8 comes into contact with the circuit 4 to cause a short circuit or the like. Can be prevented from occurring. Since the electrode 7 of the semiconductor chip 6 and the circuit 4 are close to each other, the wire 8 connecting them is shortened and the electrical characteristics such as the resistance value are improved.
【０００７】[0007]
【実施例】以下本発明を実施例によって詳述する。プリ
ント配線板などで形成される基板１の表面には正方形状
の半導体チップ搭載部２が金属箔や金属メッキなどで設
けてあり、半導体チップ搭載部２の周囲において多数の
ワイヤーボンディングパッド３，３…が金属箔や金属メ
ッキなどで設けてある。そして図２に示すように、半導
体チップ搭載部２とワイヤーボンディングパッド３，３
…との間のスペースにおいて、基板１の表面に半導体チ
ップ回路４が金属箔や金属メッキなどで設けてある。EXAMPLES The present invention will be described in detail below with reference to examples. A square semiconductor chip mounting portion 2 is provided on the surface of a substrate 1 formed of a printed wiring board or the like with metal foil or metal plating, and a large number of wire bonding pads 3, 3 are provided around the semiconductor chip mounting portion 2. ... are provided by metal foil or metal plating. Then, as shown in FIG. 2, the semiconductor chip mounting portion 2 and the wire bonding pads 3, 3
A semiconductor chip circuit 4 is provided on the surface of the substrate 1 by a metal foil, a metal plating, or the like in a space between.
【０００８】この回路４は搭載部２を囲むようにロ字形
に形成されるものであり、基板１に設けた給電回路やア
ース回路などに接続してある。そして回路４の表面には
ソルダーレジストなどで形成される絶縁被膜５が被覆し
てある。この絶縁被膜５は回路４の数カ所を除いて被覆
するようにしてあり、絶縁被膜５が被覆されていない部
分において回路４に露出部４ａが形成されるようにして
ある。The circuit 4 is formed in a square shape so as to surround the mounting portion 2 and is connected to a power supply circuit or a ground circuit provided on the substrate 1. The surface of the circuit 4 is covered with an insulating film 5 made of solder resist or the like. The insulating coating 5 is formed so as to cover the circuit 4 except at a few places, and an exposed portion 4a is formed in the circuit 4 in a portion where the insulating coating 5 is not covered.
【０００９】このように形成される基板１の半導体チッ
プ搭載部２の上に接着等することによってＩＣチップな
ど半導体チップ６を搭載し、図１に示すように、半導体
チップ６に設けた各電極７とワイヤーボンディングパッ
ド３との間に金線等のワイヤー８をボンディングすると
共に一部の電極７と回路４の露出部４ａとの間にワイヤ
ー８をボンディングすることによって、基板１に半導体
チップ６を実装して半導体装置を作成することができ
る。A semiconductor chip 6 such as an IC chip is mounted on the semiconductor chip mounting portion 2 of the substrate 1 thus formed by bonding or the like, and each electrode provided on the semiconductor chip 6 as shown in FIG. 7 and the wire bonding pad 3, a wire 8 such as a gold wire is bonded, and the wire 8 is bonded between a part of the electrode 7 and the exposed portion 4a of the circuit 4, so that the semiconductor chip 6 is attached to the substrate 1. Can be mounted to manufacture a semiconductor device.
【００１０】ここで、半導体チップ６の電極７とワイヤ
ーボンディングパッド３との間にボンディングするワイ
ヤー８が絶縁被覆５の上を通過するように絶縁被覆５を
形成してあり、従ってこのワイヤー８が回路４に接触す
るようなことを絶縁被覆５で防ぐことができ、このワイ
ヤー８と回路４との間の電気的絶縁を確保して短絡等が
発生することを防止できるものである。そして上記のよ
うに半導体チップ６の一部の電極７と回路４とをワイヤ
ー８で接続する結果、半導体チップ６の電極７とワイヤ
ーボンディングパッド３との間にボンディングされるワ
イヤー８の本数がその分少なくなる。従ってワイヤーボ
ンディングパッド３へのワイヤー８のボンディング密度
を低くすることができることになり、ワイヤーボンディ
ングの歩留りを高めることができるものである。また、
回路４は半導体チップ６とワイヤーボンディングパッド
３との間に位置するために、半導体チップ６と回路４と
の間にボンディングするワイヤー８の長さは半導体チッ
プ６とワイヤーボンディングパッド３との間にボンディ
ングするワイヤー８よりも短くなる。このために半導体
チップ６と回路４との間にボンディングするワイヤー８
の抵抗値が小さくなるなど電気特性を向上させることが
できるものである。Here, the insulating coating 5 is formed so that the wire 8 to be bonded between the electrode 7 of the semiconductor chip 6 and the wire bonding pad 3 passes over the insulating coating 5. Therefore, the wire 8 is formed. The insulating coating 5 can prevent contact with the circuit 4, and electrical insulation between the wire 8 and the circuit 4 can be secured to prevent a short circuit or the like from occurring. As a result of connecting some of the electrodes 7 of the semiconductor chip 6 and the circuit 4 with the wires 8 as described above, the number of wires 8 bonded between the electrodes 7 of the semiconductor chip 6 and the wire bonding pads 3 is It becomes less. Therefore, the bonding density of the wires 8 to the wire bonding pads 3 can be lowered, and the yield of wire bonding can be increased. Also,
Since the circuit 4 is located between the semiconductor chip 6 and the wire bonding pad 3, the length of the wire 8 bonded between the semiconductor chip 6 and the circuit 4 is between the semiconductor chip 6 and the wire bonding pad 3. It is shorter than the wire 8 to be bonded. For this purpose, a wire 8 is bonded between the semiconductor chip 6 and the circuit 4.
The electrical characteristics can be improved such that the resistance value of is reduced.
【００１１】[0011]
【発明の効果】上記のように本発明は、基板の表面にチ
ップ搭載部を設けると共にチップ搭載部の周囲に多数の
ワイヤーボンディングパッドを設け、このチップ搭載部
とワイヤーボンディングパッドの間において基板の表面
にチップ搭載部を囲む回路を設け、半導体チップの電極
と回路の露出部とをワイヤーで接続するようにしたの
で、半導体チップの電極とワイヤーボンディングパッド
との間にボンディングされるワイヤーの本数をその分少
なくすることができるものであり、ワイヤーボンディン
グパッドへのワイヤーのボンディング密度を低くしてワ
イヤーボンディングの歩留りを高めることができるもの
である。また、回路の一部を露出させて回路の表面に絶
縁被膜を被覆し、半導体チップの電極とワイヤーボンデ
ィングパッドとを絶縁被覆の上を通過するワイヤーで接
続するようにしたので、このワイヤーが回路に接触する
ことを絶縁被覆で防ぐことができ、このワイヤーと回路
との間の電気的絶縁を確保して短絡等が発生することを
防止できるものである。さらに、回路は半導体チップと
ワイヤーボンディングパッドとの間に位置するので、半
導体チップと回路との間にボンディングするワイヤーの
長さが短くなり、半導体チップと回路との間にボンディ
ングするワイヤーの抵抗値が小さくなって電気特性を向
上させることができるものである。As described above, according to the present invention, the chip mounting portion is provided on the surface of the substrate and a large number of wire bonding pads are provided around the chip mounting portion, and the substrate is provided between the chip mounting portion and the wire bonding pads. Since the circuit surrounding the chip mounting part was provided on the surface and the electrode of the semiconductor chip and the exposed part of the circuit were connected by a wire, the number of wires to be bonded between the electrode of the semiconductor chip and the wire bonding pad was determined. The amount can be reduced by that amount, and the wire bonding yield can be increased by lowering the wire bonding density to the wire bonding pad. In addition, a part of the circuit is exposed to cover the surface of the circuit with an insulating film, and the electrode of the semiconductor chip and the wire bonding pad are connected by a wire passing over the insulating film. It is possible to prevent contact with the wire with an insulating coating, and to secure electrical insulation between the wire and the circuit to prevent a short circuit or the like from occurring. Further, since the circuit is located between the semiconductor chip and the wire bonding pad, the length of the wire bonded between the semiconductor chip and the circuit is shortened, and the resistance value of the wire bonded between the semiconductor chip and the circuit is reduced. Is smaller and the electrical characteristics can be improved.
【図１】本発明の一実施例の一部の拡大した平面図であ
る。FIG. 1 is a partially enlarged plan view of an embodiment of the present invention.
【図２】同上に用いる基板の一部の拡大した平面図であ
る。FIG. 2 is an enlarged plan view of a part of the substrate used in the above.
【図３】従来例の一部の拡大した平面図である。FIG. 3 is a partially enlarged plan view of a conventional example.
【図４】同上に用いる基板の一部の拡大した平面図であ
る。FIG. 4 is an enlarged plan view of a part of the substrate used in the above.
１ 基板 ２ チップ搭載部 ３ ワイヤーボンディングパッド ４ 回路 ４ａ 露出部 ５ 絶縁被覆 ６ 半導体チップ ７ 電極 ８ ワイヤー 1 substrate 2 chip mounting portion 3 wire bonding pad 4 circuit 4a exposed portion 5 insulating coating 6 semiconductor chip 7 electrode 8 wire
Claims (1)
にチップ搭載部の周囲に多数のワイヤーボンディングパ
ッドを設け、このチップ搭載部とワイヤーボンディング
パッドの間において基板の表面にチップ搭載部を囲む回
路を設け、回路の一部を露出させて回路の表面に絶縁被
膜を被覆し、チップ搭載部の上に半導体チップを搭載
し、半導体チップの電極とワイヤーボンディングパッド
とを絶縁被覆の上を通過するワイヤーで接続すると共に
半導体チップの電極と回路の露出部とをワイヤーで接続
して成ることを特徴とする半導体装置。1. A circuit for providing a chip mounting portion on the surface of a substrate and a plurality of wire bonding pads around the chip mounting portion, and enclosing the chip mounting portion on the surface of the substrate between the chip mounting portion and the wire bonding pads. A part of the circuit is exposed to cover the surface of the circuit with an insulating film, the semiconductor chip is mounted on the chip mounting portion, and the electrode of the semiconductor chip and the wire bonding pad are passed over the insulating coating. A semiconductor device characterized in that the electrodes of the semiconductor chip and the exposed portions of the circuit are connected by wires while being connected by wires.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4004286A JPH05190586A (en) | 1992-01-14 | 1992-01-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4004286A JPH05190586A (en) | 1992-01-14 | 1992-01-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05190586A true JPH05190586A (en) | 1993-07-30 |
Family
ID=11580291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4004286A Withdrawn JPH05190586A (en) | 1992-01-14 | 1992-01-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05190586A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010124001A (en) * | 2010-03-08 | 2010-06-03 | Rohm Co Ltd | Semiconductor device |
| JP2014056966A (en) * | 2012-09-13 | 2014-03-27 | Renesas Electronics Corp | Semiconductor device manufacturing method |
-
1992
- 1992-01-14 JP JP4004286A patent/JPH05190586A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010124001A (en) * | 2010-03-08 | 2010-06-03 | Rohm Co Ltd | Semiconductor device |
| JP2014056966A (en) * | 2012-09-13 | 2014-03-27 | Renesas Electronics Corp | Semiconductor device manufacturing method |
| US9589923B2 (en) | 2012-09-13 | 2017-03-07 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990408 |