JP3221072B2 - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JP3221072B2
JP3221072B2 JP18525692A JP18525692A JP3221072B2 JP 3221072 B2 JP3221072 B2 JP 3221072B2 JP 18525692 A JP18525692 A JP 18525692A JP 18525692 A JP18525692 A JP 18525692A JP 3221072 B2 JP3221072 B2 JP 3221072B2
Authority
JP
Japan
Prior art keywords
resin
chip
semiconductor chip
semiconductor device
inner lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP18525692A
Other languages
Japanese (ja)
Other versions
JPH0637238A (en
Inventor
友規 西野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP18525692A priority Critical patent/JP3221072B2/en
Publication of JPH0637238A publication Critical patent/JPH0637238A/en
Application granted granted Critical
Publication of JP3221072B2 publication Critical patent/JP3221072B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明はQuad Flat Package (Q
FP)型樹脂封止型半導体装置に係り、特に高発熱の半
導体チップ(以降、チップと略称する)を内蔵したQF
P型樹脂封止型半導体装置(以降、QFP型半導体装置
と略称する)に関するものである。
The present invention relates to a Quad Flat Package (Q
The present invention relates to an FP) type resin-encapsulated semiconductor device, and particularly relates to a QF having a built-in semiconductor chip (hereinafter abbreviated as a chip) having high heat generation.
The present invention relates to a P-type resin-sealed semiconductor device (hereinafter abbreviated as a QFP semiconductor device).

【0002】[0002]

【従来の技術】コンピュータやパーソナルコンピュータ
などに使用される半導体装置は、電子機器の小型化、薄
型化、軽量化、そしてその製造時の生産効率を高める目
的でQFP型半導体装置のような、いわゆる表面実装対
応の樹脂封止型半導体装置を多数使用している。図4に
従来のガルウィング型のアウターリードを有するQFP
型半導体装置の断面図を示す。また、Small Out-line J
-bend Package (SOJ)型樹脂封止型半導体装置で
は、半導体メモリを対象に規格化された大きさのパッケ
ージに大型化するチップを収納するために、インナーリ
ードの一部の上部に絶縁体フィルムを介して半導体メモ
リのチップを接着したChip-On-Lead(COL)構造と呼
ばれる表面実装対応の樹脂封止型半導体装置が提案され
ている。(特開昭61−218139号公報参照)
2. Description of the Related Art Semiconductor devices used in computers, personal computers, and the like are so-called QFP type semiconductor devices for the purpose of reducing the size, thickness, and weight of electronic devices, and increasing production efficiency in the production thereof. Many resin-encapsulated semiconductor devices for surface mounting are used. FIG. 4 shows a conventional QFP having a gull-wing type outer lead.
1 shows a cross-sectional view of a semiconductor device. Also, Small Out-line J
-bend Package (SOJ) type resin-encapsulated semiconductor devices have an insulator film on top of a part of the inner leads to accommodate the chip to be enlarged in a package of standardized size for semiconductor memory. There has been proposed a resin-encapsulated semiconductor device compatible with surface mounting called a Chip-On-Lead (COL) structure in which a chip of a semiconductor memory is adhered through a semiconductor device. (See JP-A-61-218139)

【0003】[0003]

【発明が解決しようとする課題】ところで、QFP型半
導体装置は、従来比較的低発熱の半導体装置として用い
られていたものであり、例えば1ワットを越えるような
消費電力の大きな、すなわち発熱量の大きな半導体装置
のチップの放熱には、熱放散性が低いが故に適していな
かった。最近では、電子機器内のプリント基板上に搭載
される半導体装置の単位面積当たりの端子密度は著しく
上昇し、半導体装置は多素子化、高速化にともなう発熱
量が増大しているため、電子機器の放熱対策はもちろん
のこと半導体装置自身の放熱対策が電子機器の小型化、
薄型化、軽量化、高速化そして多機能化のための大きな
要因となろうとしている。
By the way, the QFP type semiconductor device has been conventionally used as a semiconductor device having relatively low heat generation. For example, the QFP type semiconductor device has a large power consumption exceeding 1 watt, that is, a heat generation amount. It is not suitable for heat dissipation of a chip of a large semiconductor device because of its low heat dissipation. Recently, the terminal density per unit area of a semiconductor device mounted on a printed circuit board in an electronic device has significantly increased, and the amount of heat generated by the semiconductor device has been increased due to the increase in the number of elements and the speed. The heat dissipation measures of the semiconductor device itself, as well as the heat dissipation measures of
It is about to become a major factor for thinner, lighter, faster and more multifunctional.

【0004】一方、半導体メモリを対象としたCOL構
造の半導体装置も、熱放散性を主眼としたものでなく、
高い熱放散性を必要とするQFP型半導体装置に適用さ
れるまでには至っていない。
[0004] On the other hand, a semiconductor device having a COL structure for a semiconductor memory also does not focus on heat dissipation.
It has not yet been applied to a QFP semiconductor device requiring high heat dissipation.

【0005】本発明は、発熱量の大きいチップを搭載し
た小型で高密度実装に適した表面実装対応のQFP型半
導体装置を提供することを目的とするものである。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a small-sized QFP semiconductor device suitable for high-density mounting, on which a chip generating a large amount of heat is mounted.

【0006】[0006]

【課題を解決するための手段】前述のような課題を解決
するために本発明は、アウターリードから引きのばされ
たインナーリードの上部に絶縁体フィルムを介してチッ
プを接着し、チップに形成された電極とインナーリード
を電気的に接続し、インナーリードの先端をチップの中
心に向かうように放射状に配置したQFP型半導体装置
であり、このQFP型半導体装置のインナーリードはチ
ップ外縁部のインナーリードの幅をチップ内縁部のイン
ナーリードの幅より大きく形成し、チップの対角線によ
り形成される三角形、もしくはチップの中心点を含む三
角形の頂角を等角に分割した三角形の内側に配設された
インナーリードがチップを覆う領域の面積は、各々の三
角形において等しくし、樹脂封止部の四隅の吊りリード
は樹脂封止部のみに配置されチップにまで達しない長さ
であり、場合によっては吊りリードを取り去ってしまう
ように構成される。そして、前述した全てのQFP型半
導体装置の絶縁体フィルムの上面のチップの周縁部に額
縁状の導電膜を形成するように構成する。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention is to form a chip by bonding a chip via an insulating film to an upper part of an inner lead extended from an outer lead. Is electrically connected to the inner leads and the inner leads are radially arranged such that the tips of the inner leads are directed toward the center of the chip. The inner leads of the QFP type semiconductor device have inner leads at the outer edge of the chip. The width of the lead is formed larger than the width of the inner lead at the inner edge of the chip, and the lead is disposed inside a triangle formed by a diagonal line of the chip or a triangle obtained by equally dividing the apex angle of the triangle including the center point of the chip. The area of the area where the inner lead covers the chip is equal in each triangle, and the suspension leads at the four corners of the resin A layout is a length that does not reach the chip, configured thus removing the suspension leads in some cases. Then, a frame-shaped conductive film is formed on the peripheral portion of the chip on the upper surface of the insulator film of all the QFP semiconductor devices described above.

【0007】[0007]

【作用】したがって、本発明のQFP型半導体装置は、
アウターリードから引きのばされたインナーリードの上
部に絶縁体フィルムを介してチップを接着し、チップに
形成された電極とインナーリードを電気的に接続し、イ
ンナーリードの先端をチップの中心に向かうように放射
状に配置するように構成されており、チップに発生した
熱は薄い絶縁体フィルムを経由して複数のインナーリー
ドに接続されたアウターリードからプリント基板へ効率
的に伝導される。インナーリードはチップ外縁部のイン
ナーリードの幅がチップ内縁部のインナーリードの幅よ
り大きく形成されており、チップの対角線により形成さ
れる三角形、もしくはチップの中心点を含む三角形の頂
角を等角に分割した三角形の内側に配設されたインナー
リードがチップを覆う領域の面積は、各々の三角形にお
いて等しくされているので、インナーリードピッチが微
細になり、インナーリード本数が多くなっても、チップ
よりも内側から引きのばせるインナーリードの本数を多
くすることができる。また、チップの中央付近にまでイ
ンナーリードを寄せることができる。このため、各種の
インナーリードピッチ、インナーリード本数を持つパッ
ケージの熱を均一に効率よく放熱することができ、チッ
プ全体の電気特性を均一にすることができる。
Therefore, the QFP semiconductor device of the present invention
A chip is adhered to the upper part of the inner lead extended from the outer lead via an insulating film, an electrode formed on the chip is electrically connected to the inner lead, and a tip of the inner lead is directed toward the center of the chip. The heat generated in the chip is efficiently transmitted from the outer leads connected to the plurality of inner leads to the printed circuit board via the thin insulating film. The inner lead is formed such that the width of the inner lead at the outer edge of the chip is larger than the width of the inner lead at the inner edge of the chip, and the apex angle of the triangle formed by the diagonal line of the chip or the triangle including the center point of the chip is conformal. The area of the area where the inner leads disposed inside the divided triangles cover the chip is equal in each triangle, so that the inner lead pitch becomes finer, and even if the number of inner leads increases, the chip The number of inner leads that can be extended from the inside can be increased. Also, the inner lead can be brought close to the center of the chip. Therefore, the heat of the package having various inner lead pitches and the number of inner leads can be uniformly and efficiently radiated, and the electrical characteristics of the entire chip can be made uniform.

【0008】樹脂封止部の四隅の吊りリードは樹脂封止
部のみに配置されチップにまで達しない長さであり、場
合によっては吊りリードを取り去ってしまうように構成
されており、従来のチップを固定するダイパッドを支え
る吊りリードがなくなるため、インナーリードの引きま
わしスペースが大きくなり、インナーリードの引きまわ
しの自由度が向上する。このため、インナーリードのチ
ップよりも内側に配設可能な本数が増大して熱放散性が
向上するとともに、インナーリドピッチの微細化に対応
しやすく、半導体装置の端子密度の上昇に対応しやすく
なる。全てのQFP型半導体装置の絶縁体フィルムの上
面のチップの周縁部に額縁状の導電膜を形成するように
構成されており、導電膜を例えば接地線として用いるこ
とにより、高速で動作して発熱量が大きいチップを搭載
しても熱放散性がよいので、高速動作の保証が可能とな
る一方で電源ノイズなどの副作用に対して安定な半導体
装置を提供することができる。
The suspending leads at the four corners of the resin sealing portion are arranged only in the resin sealing portion and have a length that does not reach the chip. In some cases, the suspending leads are configured to be removed. Since there is no suspension lead for supporting the die pad for fixing the inner lead, the space for routing the inner lead is increased, and the degree of freedom in the routing of the inner lead is improved. Therefore, the number of inner leads that can be arranged inside the chip is increased, so that heat dissipation is improved, and it is easy to cope with miniaturization of the inner lid pitch, and it is easy to cope with an increase in the terminal density of the semiconductor device. Become. A frame-shaped conductive film is formed on the periphery of the chip on the upper surface of the insulator film of all the QFP type semiconductor devices. By using the conductive film as, for example, a ground line, it operates at high speed and generates heat. Even if a large amount of chips is mounted, heat dissipation is good, so that high-speed operation can be guaranteed, and a semiconductor device which is stable against side effects such as power supply noise can be provided.

【0009】[0009]

【実施例】以下、本発明のQFP型半導体装置を、図示
実施例にしたがって詳細に説明する。図1は本発明の第
1の実施例のQFP型半導体装置を示すもので、Aは封
止樹脂上面部の一部を切り欠いて示す平面図、Bは断面
図である。図1に示すように、1はQFP型半導体装置
の樹脂封止部であり、溶融石英フィラーとエポキシ樹脂
を主成分とする樹脂からなっている。2はゲートアレ
イ、スタンダードセルといったApplied specific IC
(ASIC)のチップであり、チップ2の周縁部にはパ
ッド電極(図示せず)が配置されている。チップ2の裏
面には、例えばエポキシ系の熱硬化性接着剤(図示せ
ず)により額縁状の絶縁体フィルム3(以降、フィルム
3と略称)が接着されている。このフィルム3は、例え
ば0.1mmのポリイミド樹脂からなり、後述のインナ
ーリードとチップ2との電気的絶縁を保つと同時に、イ
ンナーリード上に搭載されるチップ2を固定する働きを
有している。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a QFP semiconductor device according to the present invention will be described in detail with reference to the illustrated embodiments. 1A and 1B show a QFP type semiconductor device according to a first embodiment of the present invention, wherein A is a plan view showing a part of an upper surface of a sealing resin cut away, and B is a sectional view. As shown in FIG. 1, reference numeral 1 denotes a resin sealing portion of a QFP semiconductor device, which is made of a resin mainly composed of a fused quartz filler and an epoxy resin. 2. Applied specific IC such as gate array and standard cell
(ASIC) chip, and pad electrodes (not shown) are arranged on the periphery of the chip 2. A frame-shaped insulating film 3 (hereinafter abbreviated as film 3) is adhered to the back surface of the chip 2 by, for example, an epoxy-based thermosetting adhesive (not shown). The film 3 is made of, for example, a 0.1 mm polyimide resin and has a function of maintaining electrical insulation between an inner lead described later and the chip 2 and fixing the chip 2 mounted on the inner lead. .

【0010】ここで、4、4・・は信号伝送経路となる
Fe−Ni合金もしくはCu合金からなるインナーリー
ドであり、インナーリード4、4・・の先端はチップ2
の外周よりも内側に引きのばされ、例えばエポキシ系熱
硬化型接着剤もしくは熱可塑性接着剤(図示せず)によ
りフィルム3を介してチップ2の裏面に接着、固定され
ている。インナーリード4、4・・はチップ2の中心点
より外側に向けて放射状に引きのばされて、樹脂封止部
1の外側でアウターリード5、5・・となる。アウター
リード5、5・・は赤外線リフローによる一括はんだ付
けが可能となるように、ガルウィングと呼称される形状
に曲げ加工される。インナーリード4、4・・には、良
好な樹脂成形性を得るのに不可欠となるチップ2の上側
の樹脂封止部1の厚みとチップ2の下側の樹脂封止部1
の厚みとが等しくなるようにデプレスと呼ばれる曲げ加
工が施されているそして、チップ2のパッド電極とイン
ナーリード4、4・・とはAuワイヤ6、6・・により
電気的に接続されている。このAuワイヤ6、6・・と
インナーリード4、4・・との接続点は前述のデプレス
部の外側でも内側もよい。
Here, 4, 4,... Are inner leads made of an Fe--Ni alloy or a Cu alloy which are signal transmission paths, and the tips of the inner leads 4, 4,.
Is stretched inward from the outer periphery of the chip 2 and is adhered and fixed to the back surface of the chip 2 via the film 3 with, for example, an epoxy-based thermosetting adhesive or a thermoplastic adhesive (not shown). The inner leads 4, 4,... Are extended radially outward from the center point of the chip 2 to become outer leads 5, 5,. The outer leads 5, 5,... Are bent into a shape called a gull wing so that batch soldering by infrared reflow can be performed. The thickness of the resin sealing portion 1 on the upper side of the chip 2 and the resin sealing portion 1 on the lower side of the chip 2 which are indispensable for obtaining good resin moldability are formed on the inner leads 4.
And the pad electrodes of the chip 2 are electrically connected to the inner leads 4, 4,... By Au wires 6, 6,. . The connection points between the Au wires 6, 6,... And the inner leads 4, 4,.

【0011】正方形をなす樹脂封止部1の4つのコーナ
ー部の内側には0.5mm程度の吊りリード7、7・・
が配設され、かつ、樹脂封止部1の直近で切断されてい
る。この吊りリード7、7・・の目的はリードフレーム
状態で樹脂成形された半導体装置のアウターリード5、
5・・をリードフレームから切断し曲げ加工をするとき
に半導体装置がリードフレームから落下してばらばらに
なるのを防ぐことである。但し、この吊りリード7、7
・・は、先に述べた目的に供さない、すなわち、アウタ
ーリード5、5・・の切断、曲げ加工時にばらばらにな
っても差し支えがない場合にはなくてもよい。このよう
に、樹脂封止部1の4隅の吊りリード7、7・・がチッ
プ2に達しない、もしくは、取り除かれた構成にするこ
とにより、樹脂封止部1の隣合う辺の隅に位置するイン
ナーリード4、4・・には引きまわしのスペースが生
じ、インナーリード4、4・・の引きまわしの自由度が
広がる。この結果、配設すべきインナーリード4、4・
・の本数が多くなってもインナーリード4、4・・の先
端をチップ2の下に引きのばすことができる。
On the inside of the four corners of the resin sealing portion 1 forming a square, suspension leads 7 of about 0.5 mm are provided.
Are arranged, and are cut in the immediate vicinity of the resin sealing portion 1. The purpose of the suspension leads 7, 7,... Is to provide outer leads 5 of the semiconductor device resin-molded in a lead frame state.
The purpose of the present invention is to prevent the semiconductor device from falling from the lead frame and falling apart when cutting and bending from the lead frame. However, the suspension leads 7, 7
Are not used for the above-mentioned purpose, that is, they may not be provided when there is no problem if the outer leads 5, 5,. In this manner, by forming the suspension leads 7, 7,... At the four corners of the resin sealing portion 1 not to reach the chip 2 or by removing them, the corners of the adjacent sides of the resin sealing portion 1 There is a space in which the inner leads 4, 4,... Are arranged, and the degree of freedom of the arrangement of the inner leads 4, 4,. As a result, the inner leads 4, 4,.
Can be extended below the chip 2 even if the number of the leads becomes large.

【0012】以上述べてきたような実施例によれば、チ
ップ2に発生した熱は薄いフィルム3を経由して全ての
インナーリード4、4・・に係合したアウターリード
5、5・・からプリント基板(図示せず)へと熱伝導性
が非常によい金属材料からなる熱伝導経路を通り、効率
的に半導体装置の外部へ放熱することができる。
According to the embodiment as described above, the heat generated in the chip 2 is transmitted from the outer leads 5, 5,... Engaged with all the inner leads 4, 4,. It is possible to efficiently radiate heat to the outside of the semiconductor device through a heat conduction path made of a metal material having very good heat conductivity to a printed board (not shown).

【0013】つぎに、本発明の第2の実施例のQFP型
半導体装置について説明する。図2は、本発明の第2の
実施例のQFP型半導体装置の樹脂封止上面部の一部を
切り欠いて示す平面図である。図2に示すように、チッ
プ2の下部において、チップ2の対角線により形成され
る直角2等辺三角形内に配設されるインナーリード4、
4・・により囲まれる面積が4つの直角2等辺三角形に
対して等しく、また、チップ2の中心点を含む4つのそ
れぞれの三角形内に配設されるインナーリード4、4・
・により囲まれる面積が2つもしくは4つの三角形に対
して等しくなるようにインナーリード4、4・・がチッ
プ2の下に引きまわされている。また、実施例における
インナーリード4、4・・はチップ2の外縁部のインナ
ーリード4の幅がチップ2の内縁部のインナーリード4
の幅よりも太くしてあり、容易にインナーリード4の先
端をチップ2の中心方向へ引きのばすことができる。以
上のことから、チップ2に発生した熱の排熱均一性は向
上し、チップ2の全体にわたる電気特性を均一にするこ
とができ、かつ、排熱効果も向上させることができるよ
うになる。さらに、インナーリードピッチが微細にな
り、あるいはインナリード本数が多くなっても、チップ
2よりも内側に引きのばせるインナーリード4の本数を
多くすることができ、各種パッケージの排熱性を向上さ
せることができる。
Next, a description will be given of a QFP type semiconductor device according to a second embodiment of the present invention. FIG. 2 is a plan view of a QFP semiconductor device according to a second embodiment of the present invention, in which a part of a resin-encapsulated upper surface is cut away. As shown in FIG. 2, an inner lead 4 disposed in a right isosceles triangle formed by a diagonal line of the chip 2 below the chip 2.
The area enclosed by 4... Is equal to four right-angled isosceles triangles, and the inner leads 4, 4.
The inner leads 4, 4,... Are drawn under the chip 2 so that the area surrounded by... Is equal for two or four triangles. The width of the inner lead 4 at the outer edge of the chip 2 is equal to the width of the inner lead 4 at the inner edge of the chip 2.
The tip of the inner lead 4 can be easily extended toward the center of the chip 2. As described above, the uniformity of the heat generated in the chip 2 can be improved, the electric characteristics of the entire chip 2 can be made uniform, and the heat discharging effect can be improved. Furthermore, even if the inner lead pitch becomes finer or the number of inner leads increases, the number of inner leads 4 that can be extended inward from the chip 2 can be increased, and the heat dissipation of various packages can be improved. it can.

【0014】最後に、本発明の第3の実施例のQFP半
導体装置について説明する。図3Aは本発明の第3の実
施例のQFP半導体装置の封止樹脂上面部の1つの象限
を切り欠いて示す平面図、図3Bは断面図である。図3
A、Bに示すように、絶縁体フィルム3は額縁状をな
し、その外縁部の大きさはチップ2よりも大きく、内縁
部はチップ2よりも小さい。そして、絶縁体フィルム3
の上面にはチップ2の周縁部に額縁状に例えばAuメッ
キが施されたCu合金薄膜からなる導電膜8が形成され
ている。導電膜8は例えばVss(接地)電位となるよ
うにVssインナーリード4sからAuワイヤにより導
通されており、導電膜8からチップ2の任意のVss電
極へリード本数を増やすことなく給電できる。このた
め、チップ2が高速動作し、かつ、発熱量が大きくて
も、排熱性が良い故に高速動作保証が可能となる一方で
懸念される電源ノイズについても、導電膜8により電源
ノイズを吸収できるようになる。
Finally, a description will be given of a QFP semiconductor device according to a third embodiment of the present invention. FIG. 3A is a plan view of a QFP semiconductor device according to a third embodiment of the present invention, in which one quadrant of an upper surface of a sealing resin is cut away, and FIG. 3B is a sectional view. FIG.
As shown in A and B, the insulator film 3 has a frame shape, and its outer edge is larger than the chip 2 and its inner edge is smaller than the chip 2. And the insulator film 3
A conductive film 8 made of a Cu alloy thin film plated with, for example, Au on the periphery of the chip 2 is formed on the upper surface of the chip 2. The conductive film 8 is electrically connected to the Vss inner lead 4 s by an Au wire so as to have a Vss (ground) potential, for example, and can supply power from the conductive film 8 to an arbitrary Vss electrode of the chip 2 without increasing the number of leads. Therefore, even if the chip 2 operates at high speed and generates a large amount of heat, high-speed operation can be assured because of good heat-dissipating property. On the other hand, power supply noise, which is a concern, can be absorbed by the conductive film 8. Become like

【0015】[0015]

【発明の効果】本発明により得られる効果を簡単に説明
すれば、発熱量の大きいチップを搭載した小型、高集積
のQFP型樹脂封止半導体装置を提供することができる
ようになる。
The effects obtained by the present invention will be briefly described. It is possible to provide a small, highly integrated QFP type resin-sealed semiconductor device equipped with a chip generating a large amount of heat.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例のQFP型半導体装置を
示すもので、Aは封止樹脂上面部の一部を切り欠いて示
す平面図、Bは断面図である。
FIG. 1 shows a QFP type semiconductor device according to a first embodiment of the present invention, wherein A is a plan view showing a part of an upper surface of a sealing resin cut away, and B is a sectional view.

【図2】本発明の第2の実施例のQFP型半導体装置の
樹脂封止上面部の一部を切り欠いて示す平面図である。
FIG. 2 is a plan view of a QFP type semiconductor device according to a second embodiment of the present invention, in which a part of a resin-encapsulated upper surface is cut away.

【図3】本発明の第3の実施例のQFP半導体装置を示
すもので、Aは封止樹脂上面部の一部を切り欠いて示す
平面図、Bは断面図である。
3A and 3B show a QFP semiconductor device according to a third embodiment of the present invention, wherein A is a plan view showing a part of an upper surface of a sealing resin cut away, and B is a sectional view.

【図4】従来技術の樹脂封止型半導体装置の断面図であ
る。
FIG. 4 is a cross-sectional view of a conventional resin-encapsulated semiconductor device.

【符号の説明】[Explanation of symbols]

1 樹脂封止部 2 チップ 3 絶縁体フィルム 4 インナーリード 4s Vssインナーリード 5 アウターリード 6 Auワイヤ 7 吊りリード 8 導電膜 DESCRIPTION OF SYMBOLS 1 Resin sealing part 2 Chip 3 Insulator film 4 Inner lead 4s Vss inner lead 5 Outer lead 6 Au wire 7 Suspension lead 8 Conductive film

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平1−280343(JP,A) 特開 昭63−306648(JP,A) 特開 平4−168759(JP,A) 特開 平3−132063(JP,A) 実開 昭63−82950(JP,U) 実開 平1−95759(JP,U) 実開 平3−65244(JP,U) 実開 平3−32425(JP,U) (58)調査した分野(Int.Cl.7,DB名) H01L 23/50 H01L 23/28 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-280343 (JP, A) JP-A-63-306648 (JP, A) JP-A-4-168759 (JP, A) JP-A-3-308 132063 (JP, A) Japanese Utility Model Showa 63-82950 (JP, U) Japanese Utility Model 1-95759 (JP, U) Japanese Utility Model 3-65244 (JP, U) Japanese Utility Model Utility Model 3-32425 (JP, U) (58) Field surveyed (Int.Cl. 7 , DB name) H01L 23/50 H01L 23/28

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】アウターリードから引きのばされたインナ
ーリードの上部に絶縁体フィルムを介して半導体チップ
を接着し、該半導体チップに形成された電極と前記イン
ナーリードを電気的に接続して、該インナーリードの先
端を前記半導体チップの中心点に向かうように放射状に
配置した樹脂封止型半導体装置において、樹脂封止部の
四隅の吊りリードが樹脂封止部のみに配置され、半導体
チップにまで達しない長さであることを特徴とする樹脂
封止型半導体装置。
A semiconductor chip is adhered to an upper part of an inner lead extended from an outer lead via an insulating film, and an electrode formed on the semiconductor chip is electrically connected to the inner lead . The tip of the inner lead
Radially edge toward the center of the semiconductor chip
In the placed resin-encapsulated semiconductor device,
Hanging leads at the four corners are placed only in the resin sealing part, and semiconductor
Resin characterized by a length that does not reach the chip
Sealed semiconductor device.
【請求項2】アウターリードから引きのばされたインナ
ーリードの上部に絶縁体フィルムを介して半導体チップ
を接着し、該半導体チップに形成された電極と前記イン
ナーリードを電気的に接続して、該インナーリードの先
端を前記半導体チップの中心点に向かうように放射状に
配置し、半導体チップ外縁部のインナーリードの幅が半
導体チップ内縁部のインナーリードの幅より大きい樹脂
封止型半導体装置において、前記絶縁体フィルムが額縁
状であり、半導体チップの対角線により形成される三角
形、もしくは半導体チップの中心点を含む三角形の頂角
を等角に分割した三角形の内側に配設されたインナーリ
ードが半導体チップを覆う領域の面積は、各々の前記三
角形において等しいことを特徴とする樹脂封止型半導体
装置。
2. An inner member extended from an outer lead.
-Semiconductor chip on top of the lead via insulator film
And bonding the electrodes formed on the semiconductor chip to the electrodes.
Electrically connect the inner lead to the end of the inner lead.
Radially edge toward the center of the semiconductor chip
In the resin-encapsulated semiconductor device, wherein the width of the inner lead at the outer edge of the semiconductor chip is larger than the width of the inner lead at the inner edge of the semiconductor chip, the insulator film has a frame shape and is formed by a diagonal line of the semiconductor chip. The area of the area where the inner lead disposed inside the triangle or a triangle obtained by dividing the apex angle of the triangle including the center point of the semiconductor chip into equal angles, covering the semiconductor chip is equal in each of the triangles. Resin-encapsulated semiconductor device.
【請求項3】樹脂封止部の四隅の吊りリードが樹脂封止
部のみに配置され、半導体チップにまで達しない長さで
あることを特徴とする請求項2記載の樹脂封止型半導体
装置。
3. The suspension leads at four corners of the resin sealing portion are resin-sealed.
Part only, not to reach the semiconductor chip
3. The resin-encapsulated semiconductor according to claim 2, wherein
apparatus.
【請求項4】前記絶縁体フィルムの上面の半導体チップ
の周縁部に額縁状の導電膜を形成したことを特徴とする
請求項2記載の樹脂封止型半導体装置。
4. A semiconductor chip on an upper surface of said insulator film.
Characterized in that a frame-shaped conductive film is formed on the periphery of
The resin-encapsulated semiconductor device according to claim 2.
JP18525692A 1992-07-13 1992-07-13 Resin-sealed semiconductor device Expired - Fee Related JP3221072B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18525692A JP3221072B2 (en) 1992-07-13 1992-07-13 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18525692A JP3221072B2 (en) 1992-07-13 1992-07-13 Resin-sealed semiconductor device

Publications (2)

Publication Number Publication Date
JPH0637238A JPH0637238A (en) 1994-02-10
JP3221072B2 true JP3221072B2 (en) 2001-10-22

Family

ID=16167638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18525692A Expired - Fee Related JP3221072B2 (en) 1992-07-13 1992-07-13 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JP3221072B2 (en)

Also Published As

Publication number Publication date
JPH0637238A (en) 1994-02-10

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