JP2006216674A - Printed circuit with improved heat dissipation performance and circuit module comprising the same - Google Patents

Printed circuit with improved heat dissipation performance and circuit module comprising the same Download PDF

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JP2006216674A
JP2006216674A JP2005026402A JP2005026402A JP2006216674A JP 2006216674 A JP2006216674 A JP 2006216674A JP 2005026402 A JP2005026402 A JP 2005026402A JP 2005026402 A JP2005026402 A JP 2005026402A JP 2006216674 A JP2006216674 A JP 2006216674A
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pattern layer
circuit
heat
circuit board
insulating layer
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Atsushi Shimonaka
淳 下中
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Sharp Corp
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Sharp Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape

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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an improved printed circuit board whose heat dissipation is improved, in which high density mounting is achieved and a circuit pattern is easily made into multiple layers. <P>SOLUTION: The circuit board is provided with a circuit upper face pattern layer 2a and an intermediate pattern layer 3 which are arranged by intervening a first insulating layer 5, and a circuit lower face pattern layer 4 which is disposed on an opposite side of the intermediate pattern layer 3 by intervening a second insulating layer 6. A first back facing hole 9 formed from a surface toward an inner part is formed at least in the first insulating layer 5 or the second insulating layer 6. The circuit upper face pattern layer 2a or the circuit lower face pattern layer 4 and the intermediate pattern layer 3 are connected by a conductor film 2b with thermal conductivity of 50 W/(m K) or above, which is continuously formed on an inner wall face of the first back facing hole 9. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は、一般にプリント回路基板に関するものであり、より特定的には、放熱性が向上し、また高密度実装可能で、さらに回路パターンの多層化が容易に行えるように改良されたプリント回路基板に関する。この発明はまたそのようなプリント回路基板を用いた回路モジュールに関する。   BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a printed circuit board, and more specifically, an improved printed circuit board that has improved heat dissipation, can be mounted at high density, and can easily make multiple circuit patterns. About. The present invention also relates to a circuit module using such a printed circuit board.

近年、通信機器、情報機器は携帯電話に代表される“手のひら”型商品へ大きく移行している。このような状況において、これまで以上に部品の高密度実装化がなされる様になってきた。一方で、通信機器又は情報機器としての携帯電話の機能も向上し、今後その消費電力が大きく減少する事も期待できない。したがって、単位体積あたりの消費電力は増加の一途である。   In recent years, communication devices and information devices have greatly shifted to “palm” type products represented by mobile phones. Under such circumstances, higher-density mounting of components has been made more than ever. On the other hand, the function of a mobile phone as a communication device or an information device is also improved, and it cannot be expected that the power consumption will greatly decrease in the future. Therefore, power consumption per unit volume is increasing.

特に、半導体レーザ、発光ダイオードなど発光素子を搭載した通信機器においては、電流−光変換効率が、温度の影響を直接受ける。かつ光の放射/検出といった動作がアナログ的であることから、温度変化は消費電力のみならず、通信距離の減少といった性能にまで直接影響を及ぼしかねない。   In particular, in a communication device equipped with a light emitting element such as a semiconductor laser or a light emitting diode, the current-light conversion efficiency is directly affected by temperature. In addition, since the operation such as light emission / detection is analog, the temperature change may directly affect not only power consumption but also performance such as a reduction in communication distance.

放熱性を改善したプリント基板の構成例としては、たとえば特許文献1に示されるものがある。代表的な構成を図9に示す。   An example of the configuration of a printed circuit board with improved heat dissipation is disclosed in Patent Document 1, for example. A typical configuration is shown in FIG.

図9を参照して、無機フィラーを含んだ絶縁層(ガラスエポキシ基板)5を介在させて、回路パターン2と内層の配線パターン31が設けられている。回路パターン2には、回路部品8a,8bが接続されている。絶縁層5の裏面に絶縁層(ガラスエポキシ基板)6を介在させて放熱体12が設けられている。絶縁層5の上面にはザグリ穴9が設けられている。回路パターン2は、ザグリ穴9の内壁面にまで延びて形成されている。ザグリ穴9の底面に形成された回路パターン2には発熱回路部品である発光ダイオード1が接続されている。ザグリ穴9には発光ダイオード1を覆うように透明樹脂が充填されている。この従来例では、発光ダイオード1から発した熱は無機フィラーを含んだ絶縁層5を通じて放熱板12へと伝達される。また、基板上面に設けられた回路パターン2から、放熱用ビア7、配線パターン31を経て放熱板12へと伝達される。ここでは熱の流れを矢印付き破線で示している。   Referring to FIG. 9, a circuit pattern 2 and an inner wiring pattern 31 are provided with an insulating layer (glass epoxy substrate) 5 containing an inorganic filler interposed. Circuit components 8 a and 8 b are connected to the circuit pattern 2. A heat radiator 12 is provided on the back surface of the insulating layer 5 with an insulating layer (glass epoxy substrate) 6 interposed therebetween. A counterbore 9 is provided on the upper surface of the insulating layer 5. The circuit pattern 2 is formed to extend to the inner wall surface of the counterbore hole 9. A light emitting diode 1 that is a heat generating circuit component is connected to the circuit pattern 2 formed on the bottom surface of the counterbore 9. The counterbore 9 is filled with a transparent resin so as to cover the light emitting diode 1. In this conventional example, the heat generated from the light emitting diode 1 is transmitted to the heat sink 12 through the insulating layer 5 containing an inorganic filler. Further, the heat is transmitted from the circuit pattern 2 provided on the upper surface of the substrate to the heat dissipation plate 12 through the heat dissipation via 7 and the wiring pattern 31. Here, the heat flow is indicated by a broken line with an arrow.

また特許文献2に示される例では、図10に示すように厚さ100μmの回路基板5本体にヒートパイプ13を樹脂16にて固定している。ヒートパイプ13を設けた事で熱伝導を高め、回路基板5で発生した熱を反対面へ逃がす構造となっている。ここでも熱の流れを矢印付き破線にて示した。図中、1は発光ダイオード、2は回路上面パターン層である。   In the example shown in Patent Document 2, the heat pipe 13 is fixed to the main body of the circuit board 5 having a thickness of 100 μm with a resin 16 as shown in FIG. By providing the heat pipe 13, heat conduction is increased, and the heat generated in the circuit board 5 is released to the opposite surface. Again, the heat flow is indicated by broken lines with arrows. In the figure, 1 is a light emitting diode, and 2 is a circuit upper surface pattern layer.

特開2004―39691号公報Japanese Patent Laid-Open No. 2004-39691

特開平03−242997号公報Japanese Patent Laid-Open No. 03-242997

特許文献1に記載の方法では、絶縁層5に無機フィラーを含ませる事により熱伝導率を1〜10W/(m・K)にする事が記載されている。これは通常のガラスエポキシ樹脂と比較して約3〜30倍程度であるが、金属(例えば銅)と比較すると、約1/40〜1/400の小さい値でしかない。さらに絶縁層5は実装される半導体素子の熱伝導率より小さいため、この絶縁層5が熱抵抗となり、半導体素子の劇的な温度低下には至らない。また、特許文献1では、基板上面から放熱用ビア7を用いる事で、熱を放熱板12近くまで伝達させている。この方法では、回路パターン2である金属層が薄いために半導体素子から発生した熱がビア7まで伝達しにくく、また、ビア内面の金属部断面積が小さいことから十分な熱伝導路となり得ていないことから、半導体素子の温度低下が抑制されてしまう。加えていうならば、回路上面にこのような放熱用ビア7を設ける事は高密度実装の妨げになり必ずしも好ましいものではない。   In the method described in Patent Document 1, it is described that the thermal conductivity is set to 1 to 10 W / (m · K) by including an inorganic filler in the insulating layer 5. This is about 3 to 30 times that of a normal glass epoxy resin, but is only a small value of about 1/40 to 1/400 compared to a metal (for example, copper). Furthermore, since the insulating layer 5 is smaller than the thermal conductivity of the semiconductor element to be mounted, the insulating layer 5 becomes a thermal resistance and does not lead to a dramatic temperature drop of the semiconductor element. In Patent Document 1, heat is transmitted from the upper surface of the substrate to the vicinity of the heat radiating plate 12 by using the heat radiating via 7. In this method, since the metal layer that is the circuit pattern 2 is thin, it is difficult for heat generated from the semiconductor element to be transmitted to the via 7 and the cross-sectional area of the metal part on the inner surface of the via is small, so that a sufficient heat conduction path can be obtained. As a result, the temperature drop of the semiconductor element is suppressed. In addition, it is not always preferable to provide such a heat dissipation via 7 on the upper surface of the circuit because it hinders high-density mounting.

ヒートパイプ13を用いた特許文献2の例では、ヒートパイプ13の本数に依存するものの、放熱性はかなり高まる事が期待される。しかしながら、回路基板全体が2mm程度と厚くなってしまうこと、高密度実装に対応するための回路の多層化が困難などの課題が存在する。   In the example of Patent Document 2 using the heat pipe 13, although it depends on the number of the heat pipes 13, it is expected that the heat dissipation performance is considerably increased. However, there are problems such that the entire circuit board becomes as thick as about 2 mm, and it is difficult to make a multilayer circuit for high-density mounting.

この発明の目的は、上記のような課題を解決するためになされたもので、放熱性が向上し、また高密度実装可能で、さらに回路パターンの多層化が容易に行えるように改良されたプリント回路基板を提供することにある。   An object of the present invention is to solve the above-described problems, and is an improved print that improves heat dissipation, can be mounted at high density, and can easily make multiple circuit patterns. It is to provide a circuit board.

この発明の他の目的は、そのようなそのようなプリント回路基板を用いた回路モジュールを提供することにある。   Another object of the present invention is to provide a circuit module using such a printed circuit board.

この発明に従うプリント回路基板は、第1の絶縁層を間に介在させて設けられた上面パターン層と中間パターン層とを備える。第2の絶縁層を介在させて、上記中間パターン層の向かい側に下面パターン層が設けられている。上記第1の絶縁層又は上記第2の絶縁層の少なくとも一方に、表面から内方に向かって形成された第1のザグリ穴が設けられている。上記上面パターン層又は上記下面パターン層のいずれか1つと上記中間パターン層が、上記第1のザグリ穴の内壁面に連続して形成された熱伝導率50W/(m・K)以上の熱伝導体膜で接続されている。上記上面パターン層および上記下面パターン層は回路パターンで形成され、上記中間パターン層は金属で形成され、回路パターンであってもよい。   A printed circuit board according to the present invention includes a top pattern layer and an intermediate pattern layer provided with a first insulating layer interposed therebetween. A lower surface pattern layer is provided on the opposite side of the intermediate pattern layer with a second insulating layer interposed. At least one of the first insulating layer and the second insulating layer is provided with a first counterbore hole formed inward from the surface. Thermal conductivity of 50 W / (m · K) or more in which any one of the upper surface pattern layer or the lower surface pattern layer and the intermediate pattern layer are continuously formed on the inner wall surface of the first counterbore hole. Connected by body membranes. The upper surface pattern layer and the lower surface pattern layer may be formed of a circuit pattern, and the intermediate pattern layer may be formed of a metal and may be a circuit pattern.

この発明によれば、上記上面パターン層又は上記下面パターン層のいずれか1つと上記中間パターン層が、上記第1のザグリ穴の内壁面に連続して形成された熱伝導率50W/(m・K)以上の熱伝導体膜で接続されているので、第1のザグリ穴に設けられた実装部品で発生した熱を効率よく中間パターン層にまで伝達する事が可能である。また、中間パターン層に到達した熱を効率よく裏面にまで伝達し放散する事が可能である。   According to this invention, either one of the upper surface pattern layer or the lower surface pattern layer and the intermediate pattern layer are continuously formed on the inner wall surface of the first counterbore hole. K) Since the heat conductor films are connected to each other, it is possible to efficiently transfer the heat generated in the mounting component provided in the first counterbore to the intermediate pattern layer. Further, it is possible to efficiently transfer and dissipate the heat that has reached the intermediate pattern layer to the back surface.

この発明の好ましい実施態様によれば、上記上面パターン層又は上記下面パターン層のいずれか1つと上記中間パターン層との接続は、上記第1のザグリ穴の底面部分に形成された上記熱伝導体膜を介して行われるのが好ましい。このように構成することにより、部品実装面に実装された発熱性部品の直下に位置する中間パターン層を介して放熱されることになり、放熱性が向上する。   According to a preferred embodiment of the present invention, the connection between the one of the upper surface pattern layer or the lower surface pattern layer and the intermediate pattern layer is the thermal conductor formed on the bottom surface portion of the first counterbore hole. It is preferably carried out through a membrane. By comprising in this way, it will thermally radiate via the intermediate | middle pattern layer located directly under the exothermic component mounted in the component mounting surface, and heat dissipation improves.

この発明の他の実施態様によれば、上記第1のザグリ穴が設けられていない他方の上記第1の絶縁層又は上記第2の絶縁層に、表面から内方に向かって形成され、かつその底面と上記中間パターン層との距離が100μm以下である第2のザグリ穴が設けられている。   According to another embodiment of the present invention, the other first insulating layer or the second insulating layer not provided with the first counterbore hole is formed inward from the surface, and A second counterbore hole having a distance of 100 μm or less between the bottom surface and the intermediate pattern layer is provided.

熱伝導率50W/(m・K)以上の熱伝導体膜は、ニッケル、銅、金、銀のいずれか1つを含む材料で形成されるのが好ましい。   The thermal conductor film having a thermal conductivity of 50 W / (m · K) or more is preferably formed of a material containing any one of nickel, copper, gold, and silver.

本発明の他の局面に従う回路モジュールは、上記第1又は第2のザグリ穴の内部に回路部品を実装してなる。上記回路部品は半導体レーザ素子であることが好ましい。   A circuit module according to another aspect of the present invention is formed by mounting circuit components inside the first or second counterbore hole. The circuit component is preferably a semiconductor laser element.

本願発明により、実装部品で発生した熱を効率よく中間パターン層にまで伝達する事が可能である。また、中間パターン層に到達した熱を効率よく裏面にまで伝達し放散する事が可能である。中間パターン層は部品実装面積より大きく設定する事が可能で、放熱面を従来より大きく取る事が可能である。このため、放散効果が増し実装部品ひいては基板の温度上昇を抑制する効果がある。   According to the present invention, it is possible to efficiently transfer the heat generated in the mounted component to the intermediate pattern layer. Further, it is possible to efficiently transfer and dissipate the heat that has reached the intermediate pattern layer to the back surface. The intermediate pattern layer can be set larger than the component mounting area, and the heat radiation surface can be made larger than before. For this reason, the diffusion effect is increased, and there is an effect of suppressing the temperature rise of the mounted component and consequently the substrate.

特に実装部品の直下で中間パターン層から放熱する場合においては、熱伝達の経路が最短化され、熱抵抗の低減、部品の温度上昇抑制の効果がさらに向上する。   In particular, when heat is radiated from the intermediate pattern layer directly under the mounted component, the heat transfer path is minimized, and the effects of reducing the thermal resistance and suppressing the temperature rise of the component are further improved.

熱伝導体膜の熱伝導率が50W/(m・K)以上である場合、半導体材料そのものの熱伝導率が最大約50W/(m・K)であるため、半導体で発生した熱が実装面に設けられた回路パターン内で蓄積するようなボトルネックとならない効果がある。   When the thermal conductivity of the thermal conductor film is 50 W / (m · K) or more, the heat conductivity of the semiconductor material itself is about 50 W / (m · K) at the maximum, so the heat generated in the semiconductor is mounted on the mounting surface. There is an effect that does not become a bottleneck that accumulates in the circuit pattern provided in the circuit.

放熱性が向上し、また高密度実装可能で、さらに回路パターンの多層化が容易に行えるように改良されたプリント回路基板を提供するという目的を、上面パターン層又は下面パターン層のいずれか1つと、中間パターン層とを、第1のザグリ穴の内壁面に連続して形成された熱伝導率50W/(m・K)以上の熱伝導体膜で接続することによって実現した。以下、本願発明の実施例について説明する。なお、以下の図面において、同一または相当する部分には同一の参照番号を付す。   For the purpose of providing a printed circuit board that has improved heat dissipation, can be mounted at high density, and can be easily multi-layered with a circuit pattern, one of an upper surface pattern layer and a lower surface pattern layer is used. The intermediate pattern layer is connected by a thermal conductor film having a thermal conductivity of 50 W / (m · K) or more continuously formed on the inner wall surface of the first counterbore hole. Examples of the present invention will be described below. In the following drawings, the same or corresponding parts are denoted by the same reference numerals.

図1は実施例1にかかるプリント回路基板を用いた回路モジュールの断面図である。まず、作製方法について述べた後、その機能について説明する。   FIG. 1 is a cross-sectional view of a circuit module using a printed circuit board according to the first embodiment. First, after describing a manufacturing method, its function will be described.

両面に銅箔の形成された厚さ0.4mmのガラスエポキシ基板5を準備し、その上面および下面に、通常のフォトリソグラフィ技術を用いて銅箔から回路上面パターン層2aおよび中間パターン層3を形成する。このとき、中間パターン層3を形成する銅箔の厚さは、この層を高周波線路として使用しない場合には、例えば0.1mm厚以上に設定することも可能である。次に、その一方の面に回路下面パターン層4が形成された厚さ0.4mmのガラスエポキシ基板6を準備し、これらの基板5,6を接着剤を用いて接合し、図に示すような3層(回路上面パターン層2a,中間パターン層3,回路下面パターン層4)からなる回路基板を形成する。接着後の回路基板に、上面(回路上面パターン層2aの面)から下面(回路下面パターン層4の面)にまで至る貫通穴7,17を形成する。そして、発熱量が大きく、高い放熱性が要求される部品1を実装するためのザグリ穴9を上面側から形成する。このときザグリ穴9は、中間パターン層3を超えて、ガラスエポキシ基板6内にまで及んで形成されるようにその深さを設定しておく。貫通穴7、17、ザグリ穴9を形成後、貫通穴7,17の内部に銅、ニッケル、金の順にメッキ処理し、ザグリ穴9の内壁面に、同時に、銅、ニッケル、金の順にメッキ処理し、回路パターンとなる連続した熱伝導体膜2bを形成する。これらの金属はガラスエポキシ基板5,6との密着性が高く、安定した回路パターンを得ることが可能である。   A glass epoxy substrate 5 having a thickness of 0.4 mm with copper foil formed on both sides is prepared, and circuit upper surface pattern layer 2a and intermediate pattern layer 3 are formed on the upper surface and lower surface of the copper foil from the copper foil using a normal photolithography technique. Form. At this time, the thickness of the copper foil forming the intermediate pattern layer 3 can be set to a thickness of 0.1 mm or more, for example, when this layer is not used as a high-frequency line. Next, a 0.4 mm thick glass epoxy substrate 6 having a circuit lower surface pattern layer 4 formed on one surface thereof is prepared, and these substrates 5 and 6 are bonded using an adhesive, as shown in the figure. A circuit board composed of three layers (circuit upper surface pattern layer 2a, intermediate pattern layer 3, and circuit lower surface pattern layer 4) is formed. Through holes 7 and 17 extending from the upper surface (the surface of the circuit upper surface pattern layer 2a) to the lower surface (the surface of the circuit lower surface pattern layer 4) are formed in the circuit board after bonding. And the counterbore hole 9 for mounting the components 1 with large calorific value and high heat dissipation required is formed from the upper surface side. At this time, the depth of the counterbore 9 is set so as to extend beyond the intermediate pattern layer 3 and into the glass epoxy substrate 6. After the through holes 7 and 17 and the counterbore 9 are formed, the inside of the through holes 7 and 17 is plated in the order of copper, nickel and gold, and the inner wall surface of the counterbore 9 is simultaneously plated in the order of copper, nickel and gold. Processing is performed to form a continuous heat conductor film 2b to be a circuit pattern. These metals have high adhesion to the glass epoxy substrates 5 and 6, and a stable circuit pattern can be obtained.

実際の部品実装は、パターン上の所望の位置に、発熱部品1、その他部品8a、8bなどをダイボンド/ワイヤボンド工程にて実装し、所望の回路を構成する。場合によっては半導体回路素子の保護の目的から、回路上面パターン層2a、2bの面は、樹脂によりモールドされる事がある。この場合には、発熱部品1に対する応力を緩和する目的で硬度の低いゲル、ゴムなどの材料でザグリ穴9を満たしておくとよい。   In actual component mounting, the heat generating component 1, the other components 8a and 8b, and the like are mounted at a desired position on the pattern by a die bond / wire bond process to form a desired circuit. In some cases, the surface of the circuit upper surface pattern layers 2a and 2b may be molded with resin for the purpose of protecting the semiconductor circuit element. In this case, the counterbore 9 is preferably filled with a material such as gel or rubber having low hardness for the purpose of relieving stress on the heat generating component 1.

次に、発熱部品1から発生した熱の流れについて説明する。発熱部品1で発生した熱は、点線の矢印で示すように、ザグリ穴9の底面部分の熱伝導体膜2bに達し、熱伝導体膜2bからは直ちに中間パターン層3へ達する。中間パターン層3から、ガラスエポキシ基板6を経て、回路下面パターン層4へと伝達し、空気中又は、接続される機器の筐体、マザー基板へと放散される。中間パターン層3はその面積を実装面上の熱伝導体膜2bのパターンより広く取れる事、中間パターン層3から下面までの距離が全体の厚みの約1/2であることから、中間パターン層3がある事による熱抵抗の低減の効果は格段である。これにより、300K/Wであった熱抵抗は約150K/Wにまで低減した。なお、熱抵抗とは、発熱量に対する温度上昇の度合いを示し、熱抵抗が大きければ、使用状態での実装部品の温度が大きく上昇する。   Next, the flow of heat generated from the heat generating component 1 will be described. The heat generated in the heat generating component 1 reaches the heat conductive film 2b at the bottom surface portion of the counterbore 9 as shown by the dotted arrow, and immediately reaches the intermediate pattern layer 3 from the heat conductive film 2b. The intermediate pattern layer 3 is transmitted to the circuit lower surface pattern layer 4 through the glass epoxy substrate 6 and is dissipated in the air or to the casing of the connected device and the mother substrate. The intermediate pattern layer 3 has a larger area than the pattern of the heat conductive film 2b on the mounting surface, and the distance from the intermediate pattern layer 3 to the lower surface is about 1/2 of the entire thickness. The effect of reducing thermal resistance due to the presence of 3 is remarkable. Thereby, the thermal resistance which was 300 K / W was reduced to about 150 K / W. The thermal resistance indicates the degree of temperature rise with respect to the amount of heat generated. If the thermal resistance is large, the temperature of the mounted component in use is greatly increased.

一方、比較例として、図2に示すように今回の発熱部品1を通常部品8bと入れ替えて実装し、上下に通じる放熱用ビア(サーマルビアともいう)7で放熱させる。なお、この上下に通じる放熱用ビア7による放熱機構そのものは従来技術である。この場合、発熱部品1で発生した熱は、点線の矢印で示すように、放熱用ビア7を通って放熱される。図2に示す構造で、この放熱ビア7の数を変えて、熱抵抗を調べた結果を図3に示す。図3には、実施例1および後述する実施例2−4の場合の熱抵抗も重ねて併記する。   On the other hand, as a comparative example, as shown in FIG. 2, the heat generating component 1 of this time is replaced with a normal component 8b and mounted, and heat is radiated by a heat radiating via (also referred to as a thermal via) 7 leading up and down. Note that the heat dissipation mechanism itself by the heat dissipation vias 7 leading up and down is a conventional technique. In this case, the heat generated in the heat generating component 1 is dissipated through the heat dissipating vias 7 as indicated by dotted arrows. FIG. 3 shows the result of examining the thermal resistance with the structure shown in FIG. In FIG. 3, the thermal resistance in the case of Example 1 and Example 2-4 described later is also shown together.

比較例の場合、サーマルビアを10本程度にまでする事でようやく熱抵抗150K/Wを得る事ができた。これに対して、本実施例のように、中間パターン層3を設け、これに、ザグリ穴9の内壁面に設けられた高熱伝導性材料で形成された熱伝導体膜2bを接合させたとき、その熱抵抗を大幅に低減できる。ここで、熱伝導体膜2b(メッキで形成する)に用いられた銅、ニッケル、金などはその熱伝導率が何れも90W/(m・K)以上であり、通常の熱伝導性ペーストなどと比較して100倍以上の値を示す。一般には半導体材料そのものの熱伝導率を下回らない値の材料を用いる事で効果的な放熱が可能であり、熱伝導体膜2bの熱伝導率は、50W/(m・K)程度あればよい。   In the case of the comparative example, the thermal resistance of 150 K / W was finally obtained by reducing the number of thermal vias to about 10. On the other hand, when the intermediate pattern layer 3 is provided and the heat conductive film 2b formed of the high heat conductive material provided on the inner wall surface of the counterbore hole 9 is joined thereto as in the present embodiment. The thermal resistance can be greatly reduced. Here, copper, nickel, gold, etc. used for the heat conductor film 2b (formed by plating) all have a thermal conductivity of 90 W / (m · K) or more, and a normal heat conductive paste, etc. The value is 100 times or more. In general, effective heat dissipation is possible by using a material whose value does not fall below the thermal conductivity of the semiconductor material itself, and the thermal conductivity of the thermal conductor film 2b should be about 50 W / (m · K). .

図9に示したような放熱用ビア7は、部品実装面の集積度が増してくるとその形成が困難になってくる。したがって、部品実装面には十分な数の放熱用ビアを設ける事はできないことが多く、本実施例によって放熱性の向上を図ることが、小型回路部品実現のために効果がある事が確認できる。さらに加えて言うならば、放熱用ビア7は、1つ1つドリルにより加工するため、基板作製上の工程数が多く、低価格への対応が困難である。一方ザグリ穴9は、1回の工程で作製できるので、低価格化が可能である。   The heat dissipation via 7 as shown in FIG. 9 becomes difficult to form as the integration level of the component mounting surface increases. Therefore, it is often impossible to provide a sufficient number of heat dissipation vias on the component mounting surface, and it can be confirmed that the improvement of heat dissipation by this embodiment is effective for realizing a small circuit component. . In addition, since the heat radiating vias 7 are processed one by one with a drill, the number of steps in manufacturing the substrate is large, and it is difficult to cope with a low price. On the other hand, the counterbore 9 can be manufactured in a single process, so that the price can be reduced.

図4は実施例1の変形例にかかるプリント回路基板を用いた回路モジュールの断面図である。図1に示す実施例と同一または相当する部分には、同一の参照番号を付し、その説明を繰り返さない。ここでは、上面にザグリ穴を設ける代わりに、裏面の、発熱部品1の直下に位置する部分に、図のように中間パターン層3に到るザグリ穴9を設ける。この場合には、たとえトランスファーモールドを行っても発熱回路部品1に応力は発生せず、ザグリ穴9の埋め込みは不要である。発熱部品1で発生した熱は、図中、点線で示すように流れ、回路下面パターン層4へと伝達される。その後の放熱の様子は実施例1と同様である。   FIG. 4 is a cross-sectional view of a circuit module using a printed circuit board according to a modification of the first embodiment. Parts that are the same as or equivalent to those in the embodiment shown in FIG. 1 are given the same reference numerals, and the description thereof will not be repeated. Here, instead of providing a countersunk hole on the upper surface, a countersunk hole 9 reaching the intermediate pattern layer 3 is provided on the back surface of the part located immediately below the heat generating component 1 as shown in the figure. In this case, even if transfer molding is performed, no stress is generated in the heat generating circuit component 1, and it is not necessary to fill the counterbore hole 9. The heat generated in the heat generating component 1 flows as shown by the dotted line in the figure and is transmitted to the circuit lower surface pattern layer 4. The subsequent heat radiation is the same as in the first embodiment.

発熱素子から、回路全体を取り囲む外部環境への熱抵抗は、図5に示す様に、発熱素子から中間パターン層へ至る第1の熱抵抗R1と、中間パターン層から外部環境へいたる第2の熱抵抗R2とから構成され、これらは直列抵抗として作用している。したがって、消費電力W、外部環境温度Taのとき、発熱回路素子1の到達温度はTa+(R1+R2)*Wとなり、これらの熱抵抗R1とR2を入れ替えた本実施例2の効果は、実施例1と同じである。このように中間パターン層3へと接続されるザグリ穴9は部品実装面側に設けてもよいし、その裏面に設けてもよい。ただし、回路下面パターン層4内部での温度勾配に配慮すると、実施例1の方が、若干全体の熱抵抗が低い事が期待される。   As shown in FIG. 5, the heat resistance from the heating element to the external environment surrounding the entire circuit is the first thermal resistance R1 from the heating element to the intermediate pattern layer and the second thermal resistance from the intermediate pattern layer to the external environment. It consists of thermal resistance R2 and these act as series resistance. Therefore, when the power consumption W and the external environment temperature Ta, the temperature reached by the heat generating circuit element 1 is Ta + (R1 + R2) * W, and the effect of the second embodiment in which these thermal resistances R1 and R2 are switched is as follows. Same as Example 1. Thus, the counterbore 9 connected to the intermediate pattern layer 3 may be provided on the component mounting surface side or on the back surface thereof. However, in consideration of the temperature gradient inside the circuit lower surface pattern layer 4, it is expected that Example 1 has a slightly lower overall thermal resistance.

図6は、本発明を光通信モジュールに適用した実施例にかかる。図1に示す実施例と同一または相当する部分には、同一の参照番号を付し、その説明を繰り返さない。具体的には、発熱部品1は半導体レーザ素子であり、回路部品8a,8bは受光素子である。実施例1とほぼ同じ工程により図6に示す構造を作製した。ただしこの例では、中間パターン層3の層厚を0.1mmとした。また、部品実装面には、回路形成後にトランスファーモールド工程によりレンズ付きエポキシ樹脂10を形成した。この光通信モジュールは例えば携帯電話、ノート型パーソナルコンピュータのマザーボードへと搭載され、それぞれのマザー基板、筐体を通じて放熱されることになる。   FIG. 6 shows an embodiment in which the present invention is applied to an optical communication module. Parts that are the same as or equivalent to those in the embodiment shown in FIG. 1 are given the same reference numerals, and the description thereof will not be repeated. Specifically, the heat generating component 1 is a semiconductor laser element, and the circuit components 8a and 8b are light receiving elements. A structure shown in FIG. 6 was fabricated through substantially the same steps as in Example 1. However, in this example, the layer thickness of the intermediate pattern layer 3 was set to 0.1 mm. Moreover, the epoxy resin 10 with a lens was formed in the component mounting surface by the transfer mold process after circuit formation. This optical communication module is mounted on, for example, a motherboard of a mobile phone or a notebook personal computer, and heat is radiated through the mother board and the casing.

しかしながら本例のように、エポキシ樹脂10が発熱部品1の表面を厚く(レンズがある分、保護目的だけの樹脂モールドより厚さが必要である。)覆っている場合には、部品実装面からの対流による放熱量が低減する。したがって本例の場合には更なるモジュール熱抵抗の低減が必要である。本例では、中間パターン層3として厚さ0.1mmの銅箔を用いている。この程度の厚さがある場合、ザグリ穴9は、その底面を中間パターン層3の直上又は内部に設定することが可能となる。本例では、ザグリ穴9にメッキされてなる高熱伝導性材料で形成された熱伝導体膜2bの底面部分と中間パターン層3は直接接している。この場合、発熱部品1で発生した熱は、実施例1のようにザグリ穴9の側面から中間パターン層3へ流れるのではなく、図中点線の矢印で示すように、熱伝導体膜2bの、発熱部品1の直下に位置する部分から中間パターン層3へと達する。その後の放熱の様子は、実施例1と同様である。   However, as in this example, when the epoxy resin 10 covers the surface of the heat generating component 1 thickly (the lens is necessary to be thicker than a resin mold for protection purposes only), the component mounting surface is used. The amount of heat released by convection is reduced. Therefore, in the case of this example, it is necessary to further reduce the module thermal resistance. In this example, a copper foil having a thickness of 0.1 mm is used as the intermediate pattern layer 3. When there is such a thickness, the counterbore hole 9 can be set to have a bottom surface directly above or inside the intermediate pattern layer 3. In this example, the intermediate pattern layer 3 is in direct contact with the bottom surface portion of the heat conductive film 2b formed of a high heat conductive material plated in the counterbore 9. In this case, the heat generated in the heat generating component 1 does not flow from the side surface of the counterbore hole 9 to the intermediate pattern layer 3 as in the first embodiment, but instead of the heat conductor film 2b as shown by the dotted arrow in the figure. The intermediate pattern layer 3 is reached from a portion located immediately below the heat generating component 1. The state of the subsequent heat dissipation is the same as in the first embodiment.

このように、中間パターン層3と、熱伝導体膜2bの、ザグリ穴9の底面に位置する部分とが接合し、かつその接合面積が大きい場合、大幅な熱抵抗の低減が図れ、本実施例では熱抵抗135K/Wを得た(図3参照)。特に半導体レーザなどのアナログ部品は、温度によりその出力が直接影響を受けてしまい、光通信可能距離の短小化などがおきてしまう。したがって特に放熱性を向上させた回路基板、モジュールが必須である。   In this way, when the intermediate pattern layer 3 and the portion of the heat conductor film 2b located on the bottom surface of the counterbore 9 are bonded and the bonding area is large, the thermal resistance can be greatly reduced, and this embodiment is performed. In the example, a thermal resistance of 135 K / W was obtained (see FIG. 3). In particular, the output of analog parts such as semiconductor lasers is directly affected by temperature, resulting in a reduction in the distance for optical communication. Therefore, circuit boards and modules with improved heat dissipation are indispensable.

図7はさらに放熱性の向上した基板を用いた光通信モジュールの例である。先の実施例3の構造に、さらにザグリ穴9の裏面側から、同じくザグリ穴11を形成したものである。ザグリ穴11の直径はザグリ穴9の底面の直径と同程度又はそれ以上に形成しておく。もちろん放熱の効果は小さくなるが、レイアウトに応じてザグリ穴9より小さくしてもよい。ザグリ穴11の内部は、銅、ニッケル、金の順にメッキが施されており、発熱部品1で発生した熱は、図中、点線の矢印で示すように、熱伝導体膜2b、中間パターン層3から、ガラスエポキシ基板6を経て、回路下面パターン層4へと伝達し、空気中又は、接続される機器の筐体、マザー基板へと放散される。   FIG. 7 shows an example of an optical communication module using a substrate with further improved heat dissipation. The counterbore hole 11 is also formed in the structure of the third embodiment from the back side of the counterbore hole 9. The diameter of the counterbore 11 is formed to be equal to or larger than the diameter of the bottom surface of the counterbore 9. Of course, the effect of heat dissipation is reduced, but it may be smaller than the counterbore 9 depending on the layout. The inside of the counterbore 11 is plated in the order of copper, nickel, and gold, and the heat generated in the heat generating component 1 is, as shown by the dotted arrows in the figure, the heat conductor film 2b, the intermediate pattern layer 3 is transmitted to the circuit lower surface pattern layer 4 through the glass epoxy substrate 6 and is diffused in the air, or to the casing of the connected device and the mother substrate.

本実施例では、基板下面からザグリ穴11を形成しており、ザグリ穴11の底面と中間パターン層3の距離dを変える事で熱抵抗をコントロールすることが可能である。本実施例ではこの距離を50μmに設定した。図8に、この距離dを変えた時の熱抵抗の様子を示す。距離dを短くするとともに熱抵抗の低減がうかがわれるが、特に100μm以下の領域では、急速に低減する事が確認できた。ザグリ穴形成工程における深さの最大公差は、±50μmであり、上記距離を50μmに設定する事で、実際のdは0μm<d<100μmとなり、熱抵抗を115(K/W)以下にまで低減させることが可能となった。この値は、図3から明らかなように、放熱用ビアの数を増やすことのみでは実現する事が困難な熱抵抗の値である。   In this embodiment, counterbore holes 11 are formed from the bottom surface of the substrate, and the thermal resistance can be controlled by changing the distance d between the bottom surface of the counterbore holes 11 and the intermediate pattern layer 3. In this embodiment, this distance is set to 50 μm. FIG. 8 shows the state of thermal resistance when the distance d is changed. It can be seen that the thermal resistance is reduced as the distance d is shortened, but it is confirmed that the distance d decreases rapidly particularly in the region of 100 μm or less. The maximum depth tolerance in the counterbored hole forming process is ± 50 μm. By setting the above distance to 50 μm, the actual d becomes 0 μm <d <100 μm, and the thermal resistance is 115 (K / W) or less. It became possible to reduce. As is apparent from FIG. 3, this value is a value of thermal resistance that is difficult to achieve only by increasing the number of heat-dissipating vias.

本例では、部品実装パターン(2a)および中間パターン層3と、下面側のザグリ穴11の内壁面に形成されたパターン4とは電気的に直接接続していない構成とし、回路設計の自由度をあげたものとしている。しかしながらこれらパターン2a、3、4が互いに放熱用ビアで接続されている構成であってもよい事は言うまでもない。   In this example, the component mounting pattern (2a) and the intermediate pattern layer 3 are not electrically connected directly to the pattern 4 formed on the inner wall surface of the counterbore hole 11 on the lower surface side, and the degree of freedom in circuit design. It is assumed that However, it goes without saying that the patterns 2a, 3 and 4 may be connected to each other through heat dissipation vias.

ガラスエポキシ層6全体を薄くする事で、本実施例と同様の効果が得られるが、そのような構造では、基板全体が薄くなり、トランスファーモールド後の応力により基板の反り、ワイヤの断線などの問題が生じやすくなる。   By making the entire glass epoxy layer 6 thin, the same effect as in the present embodiment can be obtained. However, in such a structure, the entire substrate becomes thin, and the warping of the substrate due to stress after transfer molding, wire breakage, etc. Problems are likely to occur.

今回開示された実施例はすべての点で例示であって制限的なものではないと考えられるべきである。例えば、ガラスエポキシ層6は他の絶縁性材料であってもよい。本発明の範囲は上記した説明ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。   It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. For example, the glass epoxy layer 6 may be another insulating material. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

本発明は、発熱量の大きな回路部品を実装するプリント基板に関する。特に、部品実装面からの放熱が少ない、樹脂モールドを必要とする回路基板として用いる事ができる。さらに加えるならば、上記モールド樹脂が回路保護以外の機能を有し、その厚さを薄くできない(例えばIrDAに代表される光モジュール部品など)場合には、格段の放熱効果を有するものである。   The present invention relates to a printed circuit board on which circuit components that generate a large amount of heat are mounted. In particular, it can be used as a circuit board that requires less resin heat radiation from the component mounting surface. In addition, when the mold resin has a function other than circuit protection and the thickness cannot be reduced (for example, an optical module component typified by IrDA), it has a significant heat dissipation effect.

実施例1にかかるプリント回路基板を用いた回路モジュールの断面図である。It is sectional drawing of the circuit module using the printed circuit board concerning Example 1. FIG. 比較例にかかるプリント回路基板を用いた回路モジュールの断面図である。It is sectional drawing of the circuit module using the printed circuit board concerning a comparative example. サーマルビアホールの数と熱抵抗の関係を示す図である。It is a figure which shows the relationship between the number of thermal via holes, and thermal resistance. 実施例2にかかるプリント回路基板を用いた回路モジュールの断面図である。It is sectional drawing of the circuit module using the printed circuit board concerning Example 2. FIG. 発熱素子から、回路全体を取り囲む外部環境への熱の流れを熱抵抗を用いて示した図である。It is the figure which showed the flow of the heat | fever from the heat generating element to the external environment surrounding the whole circuit using thermal resistance. 実施例3にかかるプリント回路基板を用いた光通信モジュールの断面図である。FIG. 6 is a cross-sectional view of an optical communication module using a printed circuit board according to Example 3; 実施例4にかかるプリント回路基板を用いた光通信モジュールの断面図である。FIG. 6 is a cross-sectional view of an optical communication module using a printed circuit board according to Example 4; ザグリ穴の底面と中間パターン層の距離dと熱抵抗の関係を示す図である。It is a figure which shows the relationship between the distance d of the bottom face of a counterbore hole, and an intermediate | middle pattern layer, and thermal resistance. 従来のプリント回路基板を用いた回路モジュールの断面図である。It is sectional drawing of the circuit module using the conventional printed circuit board. 他の従来のプリント回路基板を用いた回路モジュールの断面図である。It is sectional drawing of the circuit module using another conventional printed circuit board.

符号の説明Explanation of symbols

1 発熱部品
2a 回路上面パターン層
2b 熱伝導体膜
3 中間パターン層
4 回路下面パターン層
5、6 ガラスエポキシ基板
7 放熱用ビア
8a.8b 回路部品
9,11 ザグリ穴
10 エポキシ樹脂(トランスファーモールド樹脂)
12 放熱体
13 ヒートパイプ
DESCRIPTION OF SYMBOLS 1 Heat-generating component 2a Circuit upper surface pattern layer 2b Thermal conductor film 3 Intermediate pattern layer 4 Circuit lower surface pattern layer 5, 6 Glass epoxy board 7 Heat radiation via 8a. 8b Circuit parts 9, 11 Counterbored holes 10 Epoxy resin (transfer mold resin)
12 radiator 13 heat pipe

Claims (6)

第1の絶縁層を間に介在させて設けられた上面パターン層と中間パターン層と、
第2の絶縁層を介在させて、前記中間パターン層の向かい側に設けられた下面パターン層とを備え、
前記第1の絶縁層又は前記第2の絶縁層の少なくとも一方に、表面から内方に向かって形成された第1のザグリ穴が設けられており、
前記上面パターン層又は前記下面パターン層のいずれか1つと前記中間パターン層が、前記第1のザグリ穴の内壁面に連続して形成された熱伝導率50W/(m・K)以上の熱伝導体膜で接続されている事を特徴とするプリント回路基板。
An upper surface pattern layer and an intermediate pattern layer provided with a first insulating layer interposed therebetween;
A lower surface pattern layer provided on the opposite side of the intermediate pattern layer with a second insulating layer interposed therebetween,
At least one of the first insulating layer or the second insulating layer is provided with a first counterbore hole formed inward from the surface,
Thermal conductivity of 50 W / (m · K) or more in which either one of the upper surface pattern layer or the lower surface pattern layer and the intermediate pattern layer are continuously formed on the inner wall surface of the first counterbore hole A printed circuit board characterized by being connected by a body membrane.
前記上面パターン層又は前記下面パターン層のいずれか1つと前記中間パターン層との接続は、前記第1のザグリ穴の底面部分に形成された前記熱伝導体膜を介して行われることを特徴とする請求項1記載のプリント回路基板。   The connection between any one of the upper surface pattern layer or the lower surface pattern layer and the intermediate pattern layer is performed through the thermal conductor film formed on the bottom surface portion of the first counterbore hole. The printed circuit board according to claim 1. 前記第1のザグリ穴が設けられていない他方の前記第1の絶縁層又は前記第2の絶縁層に、表面から内方に向かって形成され、かつその底面と前記中間パターン層との距離が100μm以下である第2のザグリ穴が設けられている、請求項1または2に記載のプリント回路基板。   The other first insulating layer or the second insulating layer not provided with the first counterbore hole is formed inward from the surface, and the distance between the bottom surface and the intermediate pattern layer is The printed circuit board according to claim 1, wherein a second counterbore hole having a size of 100 μm or less is provided. 前記熱伝導体膜は、ニッケル、銅、金、銀のいずれか1つを含む材料で形成されていることを特徴とする請求項1〜3のいずれかに記載のプリント回路基板。   The printed circuit board according to claim 1, wherein the thermal conductor film is made of a material containing any one of nickel, copper, gold, and silver. 請求項1または3記載のプリント回路基板を用いて、前記第1又は第2のザグリ穴の内部に回路部品を実装した回路モジュール。   A circuit module in which a circuit component is mounted in the first or second counterbore using the printed circuit board according to claim 1. 前記回路部品は半導体レーザ素子であることを特徴とする請求項5記載の回路モジュール。   6. The circuit module according to claim 5, wherein the circuit component is a semiconductor laser element.
JP2005026402A 2005-02-02 2005-02-02 Printed circuit with improved heat dissipation performance and circuit module comprising the same Pending JP2006216674A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101220940B1 (en) * 2010-09-30 2013-01-11 (주) 액트 Printed circuit board for heat dissipation and method for manufacturing the same
WO2017022789A1 (en) * 2015-08-06 2017-02-09 株式会社村田製作所 Circuit module
JP2017508630A (en) * 2013-12-31 2017-03-30 キヤノン ユー.エス. ライフ サイエンシズ, インコーポレイテッドCanon U.S. Life Sciences, Inc. Printed circuit board design for stacked microfluidic devices

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6344745A (en) * 1986-08-11 1988-02-25 Ibiden Co Ltd Circuit board for mounting of electronic component
JPH05327144A (en) * 1992-04-02 1993-12-10 Nec Corp Hybrid integrated circuit device
JPH0690069A (en) * 1990-09-27 1994-03-29 Sun Microsyst Inc Printed-circuit board assembly and method for formation of heat-conductive passage in it
JPH07231147A (en) * 1994-02-15 1995-08-29 Ibiden Co Ltd Board for mounting electronic parts, and its manufacture
JP2003046256A (en) * 2001-05-25 2003-02-14 Ibiden Co Ltd Method for manufacturing substrate for packaging ic chip

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6344745A (en) * 1986-08-11 1988-02-25 Ibiden Co Ltd Circuit board for mounting of electronic component
JPH0690069A (en) * 1990-09-27 1994-03-29 Sun Microsyst Inc Printed-circuit board assembly and method for formation of heat-conductive passage in it
JPH05327144A (en) * 1992-04-02 1993-12-10 Nec Corp Hybrid integrated circuit device
JPH07231147A (en) * 1994-02-15 1995-08-29 Ibiden Co Ltd Board for mounting electronic parts, and its manufacture
JP2003046256A (en) * 2001-05-25 2003-02-14 Ibiden Co Ltd Method for manufacturing substrate for packaging ic chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101220940B1 (en) * 2010-09-30 2013-01-11 (주) 액트 Printed circuit board for heat dissipation and method for manufacturing the same
JP2017508630A (en) * 2013-12-31 2017-03-30 キヤノン ユー.エス. ライフ サイエンシズ, インコーポレイテッドCanon U.S. Life Sciences, Inc. Printed circuit board design for stacked microfluidic devices
WO2017022789A1 (en) * 2015-08-06 2017-02-09 株式会社村田製作所 Circuit module

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