JP2007123453A - Controller - Google Patents

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JP2007123453A
JP2007123453A JP2005312087A JP2005312087A JP2007123453A JP 2007123453 A JP2007123453 A JP 2007123453A JP 2005312087 A JP2005312087 A JP 2005312087A JP 2005312087 A JP2005312087 A JP 2005312087A JP 2007123453 A JP2007123453 A JP 2007123453A
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wiring board
power
board
wiring
control element
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JP4761200B2 (en
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Kunihiro Takenaka
国浩 竹中
Toshio Nagao
敏男 長尾
Shoichiro Shimoike
正一郎 下池
Tetsuya Ito
徹也 伊藤
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Yaskawa Electric Corp
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Yaskawa Electric Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a controller capable of raising wiring density without permitting a current capacity of a board to be influenced by a wiring pattern of a control element, and without permitting a power element and the control element to be influenced thermally by each other. <P>SOLUTION: The controller includes power elements 111 such as a plurality of power semiconductor elements, a plurality of control elements 112, and a wiring board 113 on which electrodes and a wiring pattern are formed for packaging the foregoing elements thereon. In the controller, the foregoing power elements 111 and the foregoing elements 112 are packaged mediating a gap 116. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、電力半導体素子などのパワー素子や制御回路を形成する制御素子が高密度に実装され、パワー素子の大電流用配線パターンと制御素子の微細配線パターンが複雑な配線パターンで混在したコントローラに関する。   The present invention is a controller in which power elements such as power semiconductor elements and control elements forming a control circuit are mounted with a high density, and a large current wiring pattern of the power element and a fine wiring pattern of the control element are mixed in a complicated wiring pattern. About.

従来のパワー素子の大電流用配線パターンと制御素子の微細配線パターンが複雑な配線パターンで混在したコントローラについて、半導体装置や電力変換装置を例にあげて説明する。半導体装置や電力変換装置は、電力半導体素子などのパワー素子の大電流用配線パターンと、制御素子用の微細な配線パターンが必要となる。これらを実現するために、１枚の金属ベース上に、それぞれパワー素子用、制御素子用の配線パターンを形成した２つの実装基板を接合し、それらにそれぞれの素子を実装し、放熱は金属ベースを介して行うもの（例えば、特許文献１参照）や、両面に素子を実装できる１枚の実装基板に、パワー素子と制御素子を実装し、放熱はパワー素子と制御素子の少なくとも一方の反実装面から伝熱部材により放熱器へおこなうものなどがある（例えば、特許文献２参照）。
以下、図に基づいて説明する。
図４は、１枚の金属ベース上に、それぞれパワー素子用、制御素子用の配線パターンを形成した２つの実装基板を接合し、それらにそれぞれの素子を実装し、放熱は金属ベースを介して行う半導体装置の平面図および断面図である（特許文献１）。図において、１１１はパワー素子、１１２は制御素子、１２１は制御部実装基板、１２２は電力部実装基板、１２３は絶縁基板、１２４は金属層、１２５はセラミックス絶縁基板、１２６は配線パターン、１２７は導出部、１２８は金属ベースである。構成について説明する。金属ベース１２８は、Ｃｕを主な構成材料とする厚さ約３ｍｍの板である。この金属ベース上に制御部実装基板１２１と電力部実装基板１２２が図４に示すように取り付けられる。制御部実装基板１２１は、ガラスエポキシ系の両面プリント配線板の片面に配線パターンが形成され、配線パターンが形成された面の反対面の金属層が、はんだ付により金属ベース１２８に接合されている。制御部実装基板１２１はセラミックス系の厚膜回路基板を用いても良い。一方、電力部実装基板１２２は、アルミナ系のセラミック基板の片面に配線パターンが形成され、配線パターンが形成された面の反対面の金属層が、はんだ付により金属ベース１２８に接合されている。制御部実装基板１２１と電力部実装基板１２２の電気的な接続は、電力部実装基板１２２の配線パターン１２６の一部を電力部実装基板外へ延長形成されて導出された導出部１２７により行われる。
図５は、両面に素子を実装できる１枚の実装基板に、パワー素子と制御素子を実装し、放熱はパワー素子と制御素子の少なくとも一方の反実装面から伝熱部材により放熱器へおこなう電力変換装置の断面図である（特許文献２）。図５に示す特許文献２の構成要素が特許文献１と同じものについては、同一符号を付してその説明を省略し、異なる点のみ説明する。図において、１２９は放熱器、１３０は基板、１３１は熱伝導材、１３２はネジである。構成について説明する。配線パターンが形成された基板１３０へ、パワー素子１１１および制御素子１１２が実装され、放熱経路として、パワー素子１１１もしくは制御素子１１２の少なくとも一方の反実装面から熱伝導材１３１を介して、アルミ製の放熱器１２９へ放熱する経路を有している。ここで、基板１３０は、ガラスエポキシ両面基板や金属コア基板が用いられる。基板１３０の固定は、放熱器１２９へネジ１３２で行われる。
このように、従来の半導体装置や電力変換装置は、１枚の金属ベース上に、それぞれパワー素子用、制御素子用の配線パターンを形成した２つの実装基板を接合し、それらにそれぞれの素子を実装し、放熱は金属ベースを介して行うものや、一枚の基板へパワー素子と制御素子を実装し、放熱効率をあげるために、別途放熱経路を確保したものもある。
特許第３１５７３６２号（第１−３頁、図１） 特開２００４−３３６９２９号公報（第１−４頁、図１） A conventional controller in which a large current wiring pattern of a power element and a fine wiring pattern of a control element are mixed in a complicated wiring pattern will be described by taking a semiconductor device and a power conversion device as examples. Semiconductor devices and power conversion devices require a large current wiring pattern for power elements such as power semiconductor elements and a fine wiring pattern for control elements. In order to realize these, two mounting boards on which a wiring pattern for a power element and a control element are formed are bonded to one metal base, and each element is mounted on them. The power element and the control element are mounted on a single mounting board that can be mounted on both sides (for example, see Patent Document 1) or the element can be mounted on both sides, and heat dissipation is the reverse mounting of at least one of the power element and the control element. There is what is performed from the surface to the radiator by a heat transfer member (for example, see Patent Document 2).
Hereinafter, a description will be given based on the drawings.
In FIG. 4, two mounting boards on which wiring patterns for power elements and control elements are formed are bonded on a single metal base, and the respective elements are mounted on them. It is the top view and sectional drawing of a semiconductor device to perform (patent document 1). In the figure, 111 is a power element, 112 is a control element, 121 is a control part mounting board, 122 is a power part mounting board, 123 is an insulating board, 124 is a metal layer, 125 is a ceramic insulating board, 126 is a wiring pattern, 127 is The lead-out part 128 is a metal base. The configuration will be described. The metal base 128 is a plate having a thickness of about 3 mm whose main constituent material is Cu. The control unit mounting board 121 and the power unit mounting board 122 are mounted on the metal base as shown in FIG. The control unit mounting board 121 has a wiring pattern formed on one side of a glass epoxy double-sided printed wiring board, and a metal layer opposite to the surface on which the wiring pattern is formed is joined to a metal base 128 by soldering. . The controller mounting substrate 121 may be a ceramic thick film circuit board. On the other hand, the power unit mounting substrate 122 has a wiring pattern formed on one surface of an alumina-based ceramic substrate, and a metal layer opposite to the surface on which the wiring pattern is formed is joined to a metal base 128 by soldering. The electrical connection between the control unit mounting substrate 121 and the power unit mounting substrate 122 is performed by a lead-out unit 127 derived by extending a part of the wiring pattern 126 of the power unit mounting substrate 122 to the outside of the power unit mounting substrate. .
FIG. 5 shows a power element and a control element mounted on a single mounting board on which elements can be mounted on both sides, and heat is dissipated from at least one of the power element and control element on the opposite mounting surface to the radiator by a heat transfer member. It is sectional drawing of a converter (patent document 2). The components of Patent Document 2 shown in FIG. 5 that are the same as those of Patent Document 1 are denoted by the same reference numerals, description thereof is omitted, and only different points will be described. In the figure, 129 is a heat radiator, 130 is a substrate, 131 is a heat conducting material, and 132 is a screw. The configuration will be described. The power element 111 and the control element 112 are mounted on the substrate 130 on which the wiring pattern is formed, and is made of aluminum as a heat dissipation path from at least one opposite mounting surface of the power element 111 or the control element 112 via the heat conductive material 131. There is a path for radiating heat to the radiator 129. Here, a glass epoxy double-sided board or a metal core board is used as the board 130. The substrate 130 is fixed to the radiator 129 with screws 132.
As described above, in the conventional semiconductor device and power conversion device, two mounting substrates on which a wiring pattern for a power element and a control element are formed are bonded on a single metal base, and each element is attached to them. Some of them are mounted and radiated through a metal base, and some are mounted with a power element and a control element on a single substrate, and a separate heat radiating path is secured in order to increase heat radiating efficiency.
Japanese Patent No. 3157362 (page 1-3, FIG. 1) JP 2004-336929 A (page 1-4, FIG. 1)

従来の半導体装置や電力変換装置で、１枚の金属ベース上に、それぞれパワー素子用、制御素子用の配線パターンを形成した２つの実装基板を接合し、それらにそれぞれの素子を実装し、放熱は金属ベースを介して行うものの場合は、パワー素子を実装する電力部実装基板はセラミックス系の基板を用いるため、配線密度に限界があり、装置の超小形化には対応できないという問題点があった。
また、一枚の基板へパワー素子と制御素子を実装し、放熱効率をあげるために、別途放熱経路を確保したものの場合、基板の電流容量が制御素子の配線パターンに制限され、さらに、パワー素子と制御素子が熱的に影響されあうという問題点があった。
本発明はこのような問題点に鑑みてなされたものであり、配線密度を上げることができ、その結果、装置を小形化することができ、基板の電流容量が制御素子の配線パターンに影響されることがなく、パワー素子と制御素子が熱的に影響されあうこともないコントローラを提供することを目的とする。 In a conventional semiconductor device or power conversion device, two mounting boards on which a wiring pattern for a power element and a control element are formed are bonded to one metal base, and each element is mounted on them to dissipate heat. In the case of using a metal base, the power unit mounting board on which the power element is mounted uses a ceramic substrate, so that there is a limit to the wiring density, and there is a problem that it cannot cope with the miniaturization of the apparatus. It was.
In addition, in the case where a power element and a control element are mounted on a single board and a heat dissipation path is separately secured in order to increase heat dissipation efficiency, the current capacity of the board is limited to the wiring pattern of the control element. There is a problem that the control element is thermally affected.
The present invention has been made in view of such problems, and can increase the wiring density. As a result, the apparatus can be miniaturized, and the current capacity of the substrate is influenced by the wiring pattern of the control element. It is an object of the present invention to provide a controller in which the power element and the control element are not affected by heat.

上記問題を解決するため、本発明は、次のように構成したのである。
請求項１記載の発明は、複数の電力半導体素子などのパワー素子と、複数の制御素子と、それらを実装するための電極や配線パターン形成した配線板とを備えたコントローラにおいて、前記パワー素子と前記制御素子とを空隙を介して実装したものである。
請求項２記載の発明は、複数の電力半導体素子などのパワー素子と、複数の制御素子と、それらを実装するための電極や配線パターン形成した配線板とを備えたコントローラにおいて、前記配線板上に作製された配線パターンと、少なくとも1枚の配線パターンを備えた第２の配線板上のいずれかに配置された各々の前記パワー素子と前記制御素子が、空隙を介して配置されたものである。
請求項３記載の発明は、前記第２の配線板は、前記配線板上に形成された配線パターンと空隙を介して配置される孔を形成されたものである。
請求項４記載の発明は、前記パワー素子が実装される部位に相当する前記配線板の領域と、前記制御素子が実装される部位に相当する前記配線板の領域との間に空隙が形成されたものである。 In order to solve the above problem, the present invention is configured as follows.
The invention according to claim 1 is a controller including a power element such as a plurality of power semiconductor elements, a plurality of control elements, and a wiring board on which electrodes and wiring patterns for mounting them are formed. The control element is mounted via a gap.
According to a second aspect of the present invention, there is provided a controller including a power element such as a plurality of power semiconductor elements, a plurality of control elements, and a wiring board on which electrodes and wiring patterns for mounting them are formed. Each of the power element and the control element arranged on any one of the wiring pattern prepared in the above and on the second wiring board having at least one wiring pattern are arranged via a gap. is there.
According to a third aspect of the present invention, the second wiring board is formed with a wiring pattern formed on the wiring board and a hole arranged through a gap.
According to a fourth aspect of the present invention, a gap is formed between a region of the wiring board corresponding to a portion where the power element is mounted and a region of the wiring board corresponding to a portion where the control element is mounted. It is a thing.

請求項１から３に記載の発明によると、パワー素子を実装する大電流配線領域と制御素子を実装する微細配線領域を一枚の配線板上に形成できるために高密度化が可能である。また、パワー素子と制御素子を分離する構造であるために相方の熱的影響が低減される。
請求項２に記載の発明によると、配線板でもパワー素子と制御素子を分離する構造を有しているため、相方の熱的影響を最小限にできる。 According to the first to third aspects of the present invention, the high current wiring area for mounting the power element and the fine wiring area for mounting the control element can be formed on one wiring board, so that the density can be increased. In addition, since the power element and the control element are separated, the thermal effect of the other side is reduced.
According to the second aspect of the present invention, since the wiring board has a structure for separating the power element and the control element, the thermal influence of the other side can be minimized.

以下、本発明の実施の形態について図を参照して説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図１は、本発明の第１の実施例に係るコントローラの上面図と上面図中のＡ−Ａ’面で切断した側断面図である。本発明の構成要素が従来技術と同じものについては、同一符号を付してその説明を省略し、異なる点のみ説明する。図において、１１３はコア層プリント配線板、１１４はビルドアップ層、１１５は表層プリント配線板、１１６は空隙、１１７は微細配線領域、１１８は大電流配線領域、１１９はプリプレグ、１２０はスルーホールである。本発明が特許文献１と異なる部分は、コア層プリント配線板１１３を備え、前記コア層プリント配線板１１３に、制御素子１１２が実装される微細配線領域１１７をビルドアップ層１１４で形成し、パワー素子１１１が実装される大電流配線領域１１８を、ビルドアップ層が形成された部分に対応する部分がくりぬかれた形の表層プリント配線板１１５を接着することで形成した点と、これらの微細配線領域１１７と大電流配線領域１１８の間には一定の空隙１１６を設けた点と、これらの配線領域は、コア層プリント配線板の両面に形成した点である。これにより、高密度な実装と、微細配線領域１１７と大電流配線領域１１８の直接的な熱の影響低減の両立が可能である。
また、特許文献２と異なる部分も同様で、一つの配線板上に制御素子１１２の実装に適した微細配線領域１１７とパワー素子１１１の実装に適した大電流配線領域１１８を備え、熱的な影響をさけるための空隙１１６を有している部分である。
図１に示すように、コア層プリント配線板１１３の上面および下面には、ビルドアップ層１１４が半導体製造プロセスを用いて形成されており、ビルトアップ層１１４には、制御素子１１２が実装されている。ビルドアップ層１１４とコア層プリント配線板１１３との電気的接続は、スルーホールにより行われる。
また、表層プリント配線板１１５は、プリプレグ１１９などを用いてコア層プリント配線板１１３と接着されており、ビルドアップ層１１４に空隙１１６を介して配置できるように孔が形成されている。また、表層プリント配線板１１５には、パワー素子１１１が実装されている。コア層プリント配線板１１３との電気的接続は、スルーホール１２０、または、ビアホールにより行われる。
このようなコントローラは、パワー素子１１１は大電流配線領域１１８と制御素子１１２は微細配線領域１１７に空隙１１６を介して分離されて構成されている。 FIG. 1 is a top view of a controller according to a first embodiment of the present invention and a side sectional view cut along the AA ′ plane in the top view. Constituent elements of the present invention that are the same as those of the prior art will be denoted by the same reference numerals, description thereof will be omitted, and only differences will be described. In the figure, 113 is a core layer printed wiring board, 114 is a build-up layer, 115 is a surface printed wiring board, 116 is a gap, 117 is a fine wiring area, 118 is a high current wiring area, 119 is a prepreg, and 120 is a through hole. is there. The present invention is different from Patent Document 1 in that a core layer printed wiring board 113 is provided, a fine wiring region 117 on which the control element 112 is mounted is formed on the core layer printed wiring board 113 by a buildup layer 114, and power A large current wiring region 118 on which the element 111 is mounted is formed by adhering a surface layer printed wiring board 115 in which a portion corresponding to a portion where the buildup layer is formed is hollowed, and these fine wirings A certain gap 116 is provided between the region 117 and the large current wiring region 118, and these wiring regions are formed on both surfaces of the core layer printed wiring board. As a result, it is possible to achieve both high-density mounting and direct thermal influence reduction of the fine wiring region 117 and the large current wiring region 118.
Also, the parts different from Patent Document 2 are the same, and a fine wiring region 117 suitable for mounting the control element 112 and a large current wiring region 118 suitable for mounting the power element 111 are provided on one wiring board, and thermal This is a portion having a gap 116 for avoiding the influence.
As shown in FIG. 1, a buildup layer 114 is formed on the upper and lower surfaces of the core layer printed wiring board 113 using a semiconductor manufacturing process, and a control element 112 is mounted on the buildup layer 114. Yes. The electrical connection between the buildup layer 114 and the core layer printed wiring board 113 is made through a through hole.
Further, the surface layer printed wiring board 115 is bonded to the core layer printed wiring board 113 using a prepreg 119 or the like, and a hole is formed so that the surface layer printed wiring board 115 can be disposed through the gap 116 in the buildup layer 114. A power element 111 is mounted on the surface printed wiring board 115. The electrical connection with the core layer printed wiring board 113 is made through the through hole 120 or the via hole.
In such a controller, the power element 111 is separated from the large current wiring region 118 and the control element 112 is separated into the fine wiring region 117 via the gap 116.

ここで用いられるプリント配線板の詳細な製造フローを図２に示す。
（１）コア層プリント配線板１１３について述べる。図では４層プリント配線板の例を示す。コア層プリント配線板１１３は、一般的に用いられるガラスエポキシ系のプリント配線板か、内層に金属層を有する金属コア配線板としてもよい。このコア層プリント配線板は、エッチング等により、配線パターンを形成し、必要な層数を積層する。配線パターンは、表層は１８μｍ程度のものを用い、内層は３５〜２１０μｍの様々な厚さのものを用いることができる。
（２）このコア層プリント配線板１１３に、ビルドアップ層１１４を形成する。ビルドアップ層１１４は、絶縁層と配線層を順次積層して形成する。図では２層のビルドアップ層の例を示す。ビルドアップ層１１４の絶縁層に感光性樹脂を用いた場合は露光、現像によりビアホールを形成し、パターンめっき法により配線パターンを形成する。また、絶縁層に熱硬化性樹脂を用いた場合はレーザによりビアホールを形成し、パターンめっき法により配線パターンを形成する。絶縁層である樹脂が付いた銅箔を用いた場合はエッチングによりパターンを形成する。配線パターンはいずれの方法で作製しても良い。
ビルドアップ層１１４は、コア層プリント配線板１１３の必要な部分に形成されるため、ビルドアップ層１１４を形成する領域以外は、レジストによりコーティングされておく必要がある。上記したいずれかの方法で配線パターンを作製すれば、ビルドアップ層１１４の多層化は容易である。なお、コア層プリント配線板１１３へのビルドアップ層形成時やビルドアップ層積層時は、銅箔との密着力を高めるために、エッチングなどにより粗化する方が良い。
（３）ビルドアップ層１１４が形成されたコア層プリント配線板１１３に、ビルドアップ層に対応した部分がくりぬかれた表層プリント配線板１１５を接着する。接着には、炭素繊維に樹脂を含浸した熱硬化性樹脂であるプリプレグ１１９が用いられ、加熱加圧により積層される。なお、コア層プリント配線板１１３への表層プリント配線板１１５接着時は、銅箔との密着力を高めるために、エッチングなどにより粗化する方が良い。また、配線パターンは、電流の大きさにあわせて、銅箔３５〜２５０μｍの厚さのものから選択して用いる。
（４）表層プリント配線板１１５とコアプリント配線板１１３に、スルーホール１２０またはビアホールが形成され、プリント配線板が完成する。このとき、ビルドアップ層はレジストによりコーティングしておく必要がある。
（５）プリント配線板に、パワー素子１１１を大電流配線領域１１８へ、制御素子１１２を微細配線用領域１１７へ、それぞれ実装し、コントローラが完成する。
必要であれば、コネクタなどを実装しても良い。 A detailed manufacturing flow of the printed wiring board used here is shown in FIG.
(1) The core layer printed wiring board 113 will be described. In the figure, an example of a four-layer printed wiring board is shown. The core layer printed wiring board 113 may be a commonly used glass epoxy printed wiring board or a metal core wiring board having a metal layer as an inner layer. In this core layer printed wiring board, a wiring pattern is formed by etching or the like, and a necessary number of layers are stacked. As the wiring pattern, a surface layer having a thickness of about 18 μm and an inner layer having various thicknesses of 35 to 210 μm can be used.
(2) A build-up layer 114 is formed on the core layer printed wiring board 113. The build-up layer 114 is formed by sequentially stacking an insulating layer and a wiring layer. In the figure, an example of two build-up layers is shown. When a photosensitive resin is used for the insulating layer of the buildup layer 114, a via hole is formed by exposure and development, and a wiring pattern is formed by a pattern plating method. When a thermosetting resin is used for the insulating layer, a via hole is formed by a laser and a wiring pattern is formed by a pattern plating method. When a copper foil with a resin as an insulating layer is used, a pattern is formed by etching. The wiring pattern may be produced by any method.
Since the buildup layer 114 is formed in a necessary portion of the core layer printed wiring board 113, it is necessary to coat the area other than the area where the buildup layer 114 is formed with a resist. If the wiring pattern is produced by any of the methods described above, the build-up layer 114 can be easily multi-layered. In addition, when forming the buildup layer on the core layer printed wiring board 113 or laminating the buildup layer, it is better to roughen by etching or the like in order to increase the adhesion with the copper foil.
(3) The surface layer printed wiring board 115 in which the portion corresponding to the buildup layer is hollowed is bonded to the core layer printed wiring board 113 on which the buildup layer 114 is formed. For bonding, a prepreg 119, which is a thermosetting resin in which carbon fiber is impregnated with a resin, is used and laminated by heating and pressing. When the surface layer printed wiring board 115 is bonded to the core layer printed wiring board 113, it is better to roughen it by etching or the like in order to increase the adhesion with the copper foil. The wiring pattern is selected from those having a thickness of copper foil of 35 to 250 μm according to the magnitude of current.
(4) A through-hole 120 or a via hole is formed in the surface layer printed wiring board 115 and the core printed wiring board 113 to complete the printed wiring board. At this time, the build-up layer needs to be coated with a resist.
(5) The power element 111 and the control element 112 are mounted on the printed wiring board in the large current wiring area 118 and the fine wiring area 117, respectively, thereby completing the controller.
If necessary, a connector or the like may be mounted.

図３は、本発明の第２の実施例に係るコントローラの上面図と上面図中のＡ−Ａ’面で切断した側断面図である。
図において、コア層プリント配線板１１３に、制御素子１１２が実装された微細配線領域１１７と、パワー素子１１１が実装された表層プリント配線板１１５とを接着してプリント配線板で形成した点と製造方法については、実施例１と同様であるので説明を省略する。
本発明が実施例１と異なる点は、大電流領域１１８と微細配線領域１１７の領域がコア層プリント配線板１１３においても空隙１１６を介して分離されたことである。
この場合、コア層プリント配線板にもパワー素子と制御素子を分離する構造を有しているため、相方の熱的影響を最小限にできる。 FIG. 3 is a top view of a controller according to the second embodiment of the present invention and a side sectional view cut along the AA ′ plane in the top view.
In the figure, the core layer printed wiring board 113 is bonded to a fine wiring region 117 on which the control element 112 is mounted and a surface printed wiring board 115 on which the power element 111 is mounted, and is formed from a printed wiring board. Since the method is the same as that of the first embodiment, the description thereof is omitted.
The present invention is different from the first embodiment in that the large current region 118 and the fine wiring region 117 are separated from each other in the core layer printed wiring board 113 through the gap 116.
In this case, since the core layer printed wiring board has a structure for separating the power element and the control element, the thermal influence of the other side can be minimized.

本発明の実施例１を示すコントローラの側断面図と上面図Side sectional view and top view of a controller showing Embodiment 1 of the present invention 本発明の概略製造フローを示すフローチャート図The flowchart figure which shows the outline manufacturing flow of this invention 本発明の実施例２を示すコントローラの側断面図と上面図Side sectional view and top view of a controller showing Embodiment 2 of the present invention 従来の半導体装置の側断面図と上面図Side sectional view and top view of conventional semiconductor device 従来の電力変換装置の側断面図Side sectional view of a conventional power converter

符号の説明Explanation of symbols

１１１ パワー素子
１１２ 制御素子
１１３ コア層プリント配線板
１１４ ビルドアップ層
１１５ 表層プリント配線板
１１６ 空隙
１１７ 微細配線領域
１１８ 大電流配線領域
１１９ プリプレグ
１２０ スルーホール
１２１ 制御部実装基板
１２２ 電力部実装基板
１２３ 絶縁基板
１２４ 金属層
１２５ セラミックス絶縁基板
１２６ 配線パターン
１２７ 導出部
１２８ 金属ベース
１２９ 放熱器
１３０ 基板
１３１ 熱伝導材
１３２ ねじ 111 Power element 112 Control element 113 Core layer printed wiring board 114 Build-up layer 115 Surface layer printed wiring board 116 Void 117 Fine wiring area 118 High current wiring area 119 Pre-preg 120 Through hole 121 Control part mounting board 122 Power part mounting board 123 Insulating board 124 metal layer 125 ceramic insulating substrate 126 wiring pattern 127 lead-out part 128 metal base 129 radiator 130 substrate 131 heat conduction material 132 screw

Claims (4)

複数の電力半導体素子などのパワー素子と、複数の制御素子と、それらを実装するための電極や配線パターン形成した配線板とを備えたコントローラにおいて、
前記パワー素子と前記制御素子とを空隙を介して実装したことを特徴とするコントローラ。 In a controller comprising a power element such as a plurality of power semiconductor elements, a plurality of control elements, and a wiring board on which electrodes and wiring patterns for mounting them are formed,
A controller characterized in that the power element and the control element are mounted via a gap. 複数の電力半導体素子などのパワー素子と、複数の制御素子と、それらを実装するための電極や配線パターン形成した配線板とを備えたコントローラにおいて、
前記配線板上に作製された配線パターンと、少なくとも1枚の配線パターンを備えた第２の配線板上のいずれかに配置された各々の前記パワー素子と前記制御素子が、空隙を介して配置されたことを特徴とするコントローラ。 In a controller comprising a power element such as a plurality of power semiconductor elements, a plurality of control elements, and a wiring board on which electrodes and wiring patterns for mounting them are formed,
Each of the power element and the control element arranged on any one of the wiring pattern produced on the wiring board and the second wiring board provided with at least one wiring pattern is arranged via a gap. A controller characterized by that. 前記第２の配線板は、前記配線板上に形成された配線パターンと空隙を介して配置される孔を形成されたことを特徴とする請求項２に記載のコントローラ。   The controller according to claim 2, wherein the second wiring board is formed with a wiring pattern formed on the wiring board and a hole arranged through a gap. 前記パワー素子が実装される部位に相当する前記配線板の領域と、前記制御素子が実装される部位に相当する前記配線板の領域との間に空隙が形成されたことを特徴とする請求項２記載のコントローラ。 The air gap is formed between a region of the wiring board corresponding to a part where the power element is mounted and a region of the wiring board corresponding to a part where the control element is mounted. 2. The controller according to 2.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010115045A (en) * 2008-11-07 2010-05-20 Toshiba Corp Inverter device in power converter
DE102011088292B4 (en) 2010-12-14 2019-01-31 Denso Corporation ELECTRONIC DEVICE

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58147271U (en) * 1982-03-27 1983-10-03 株式会社フジクラ Enamel substrate with insulation
JPH03157362A (en) * 1989-11-16 1991-07-05 Nissan Chem Ind Ltd Benzyl halides
JPH0513894A (en) * 1991-04-30 1993-01-22 Mitsubishi Electric Corp Board
JPH05167006A (en) * 1991-12-16 1993-07-02 Mitsubishi Electric Corp Semiconductor device and manufacturing method thereof; composite substrate used for semiconductor device and manufacturing method thereof
JPH10335866A (en) * 1997-05-27 1998-12-18 Fujitsu Ten Ltd Heat radiation structure for circuit board
JPH1140901A (en) * 1997-07-23 1999-02-12 Sharp Corp Circuit board
JPH11163490A (en) * 1997-11-27 1999-06-18 Mitsubishi Electric Corp Electronic device
JPH11317582A (en) * 1998-02-16 1999-11-16 Matsushita Electric Ind Co Ltd Multilayer wiring board and manufacture thereof
JP2001095131A (en) * 1999-09-27 2001-04-06 Furukawa Electric Co Ltd:The Electrical junction box
JP2002141637A (en) * 2000-11-02 2002-05-17 Multi:Kk Printed-wiring board and its manufacturing method
JP2002299785A (en) * 2001-03-29 2002-10-11 Tdk Corp High-frequency module
JP2004342325A (en) * 2003-05-12 2004-12-02 Matsushita Electric Works Ltd Discharge lamp lighting device
JP2005223078A (en) * 2004-02-04 2005-08-18 Murata Mfg Co Ltd Circuit module
JP2006019441A (en) * 2004-06-30 2006-01-19 Shinko Electric Ind Co Ltd Method of manufacturing substrate with built-in electronic substrate

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58147271U (en) * 1982-03-27 1983-10-03 株式会社フジクラ Enamel substrate with insulation
JPH03157362A (en) * 1989-11-16 1991-07-05 Nissan Chem Ind Ltd Benzyl halides
JPH0513894A (en) * 1991-04-30 1993-01-22 Mitsubishi Electric Corp Board
JPH05167006A (en) * 1991-12-16 1993-07-02 Mitsubishi Electric Corp Semiconductor device and manufacturing method thereof; composite substrate used for semiconductor device and manufacturing method thereof
JPH10335866A (en) * 1997-05-27 1998-12-18 Fujitsu Ten Ltd Heat radiation structure for circuit board
JPH1140901A (en) * 1997-07-23 1999-02-12 Sharp Corp Circuit board
JPH11163490A (en) * 1997-11-27 1999-06-18 Mitsubishi Electric Corp Electronic device
JPH11317582A (en) * 1998-02-16 1999-11-16 Matsushita Electric Ind Co Ltd Multilayer wiring board and manufacture thereof
JP2001095131A (en) * 1999-09-27 2001-04-06 Furukawa Electric Co Ltd:The Electrical junction box
JP2002141637A (en) * 2000-11-02 2002-05-17 Multi:Kk Printed-wiring board and its manufacturing method
JP2002299785A (en) * 2001-03-29 2002-10-11 Tdk Corp High-frequency module
JP2004342325A (en) * 2003-05-12 2004-12-02 Matsushita Electric Works Ltd Discharge lamp lighting device
JP2005223078A (en) * 2004-02-04 2005-08-18 Murata Mfg Co Ltd Circuit module
JP2006019441A (en) * 2004-06-30 2006-01-19 Shinko Electric Ind Co Ltd Method of manufacturing substrate with built-in electronic substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010115045A (en) * 2008-11-07 2010-05-20 Toshiba Corp Inverter device in power converter
DE102011088292B4 (en) 2010-12-14 2019-01-31 Denso Corporation ELECTRONIC DEVICE

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