JPH0529989B2 - - Google Patents

Info

Publication number
JPH0529989B2
JPH0529989B2 JP61184389A JP18438986A JPH0529989B2 JP H0529989 B2 JPH0529989 B2 JP H0529989B2 JP 61184389 A JP61184389 A JP 61184389A JP 18438986 A JP18438986 A JP 18438986A JP H0529989 B2 JPH0529989 B2 JP H0529989B2
Authority
JP
Japan
Prior art keywords
column
mode
address
row
column address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP61184389A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62103895A (ja
Inventor
Uangu Chuupingu
Etsuchi Shaa Atsushuin
Hiramu Uomatsuku Richaado
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPS62103895A publication Critical patent/JPS62103895A/ja
Publication of JPH0529989B2 publication Critical patent/JPH0529989B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1027—Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
JP61184389A 1985-08-07 1986-08-07 半導体メモリおよびその動作方法 Granted JPS62103895A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/763,483 US4750839A (en) 1985-08-07 1985-08-07 Semiconductor memory with static column decode and page mode addressing capability
US763483 1985-08-07

Publications (2)

Publication Number Publication Date
JPS62103895A JPS62103895A (ja) 1987-05-14
JPH0529989B2 true JPH0529989B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-05-06

Family

ID=25067950

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61184389A Granted JPS62103895A (ja) 1985-08-07 1986-08-07 半導体メモリおよびその動作方法

Country Status (4)

Country Link
US (1) US4750839A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0213395B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS62103895A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3677672D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960003526B1 (ko) 1992-10-02 1996-03-14 삼성전자주식회사 반도체 메모리장치
JPS63237296A (ja) * 1987-03-25 1988-10-03 Toshiba Corp 半導体記憶装置
US5528551A (en) * 1987-05-21 1996-06-18 Texas Instruments Inc Read/write memory with plural memory cell write capability at a selected row address
US5173878A (en) * 1987-11-25 1992-12-22 Kabushiki Kaisha Toshiba Semiconductor memory including address multiplexing circuitry for changing the order of supplying row and column addresses between read and write cycles
EP0333231B1 (en) * 1988-03-18 1995-06-14 Nec Corporation Microcomputer system capable of accessing to memory at high speed
JPH01258294A (ja) * 1988-04-07 1989-10-16 Nec Corp ダイナミック・ランダム・アクセス・メモリ
US4933910A (en) * 1988-07-06 1990-06-12 Zenith Data Systems Corporation Method for improving the page hit ratio of a page mode main memory system
US5159676A (en) * 1988-12-05 1992-10-27 Micron Technology, Inc. Semi-smart DRAM controller IC to provide a pseudo-cache mode of operation using standard page mode draws
USRE38379E1 (en) * 1989-08-28 2004-01-06 Hitachi, Ltd. Semiconductor memory with alternately multiplexed row and column addressing
US5107465A (en) * 1989-09-13 1992-04-21 Advanced Micro Devices, Inc. Asynchronous/synchronous pipeline dual mode memory access circuit and method
US6324120B2 (en) 1990-04-18 2001-11-27 Rambus Inc. Memory device having a variable data output length
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
JPH0682339B2 (ja) * 1990-08-31 1994-10-19 インターナショナル・ビジネス・マシーンズ・コーポレイション メモリ・アクセス・システムおよび方法
US5305277A (en) * 1991-04-24 1994-04-19 International Business Machines Corporation Data processing apparatus having address decoder supporting wide range of operational frequencies
US5260909A (en) * 1991-11-18 1993-11-09 Nec Electronics Incorporated Memory with phase locked serial input port
US5485589A (en) * 1991-12-31 1996-01-16 Dell Usa, L.P. Predictive addressing architecture
US6279116B1 (en) 1992-10-02 2001-08-21 Samsung Electronics Co., Ltd. Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation
JP3344494B2 (ja) * 1993-03-23 2002-11-11 インターナショナル・ビジネス・マシーンズ・コーポレーション ページモードを有するシングルクロックメモリ
US5379261A (en) * 1993-03-26 1995-01-03 United Memories, Inc. Method and circuit for improved timing and noise margin in a DRAM
RU2156506C2 (ru) * 1993-04-27 2000-09-20 Самсунг Электроникс Ко., Лтд. Полупроводниковая память
US5640527A (en) * 1993-07-14 1997-06-17 Dell Usa, L.P. Apparatus and method for address pipelining of dynamic random access memory utilizing transparent page address latches to reduce wait states
US6185629B1 (en) * 1994-03-08 2001-02-06 Texas Instruments Incorporated Data transfer controller employing differing memory interface protocols dependent upon external input at predetermined time
US5526320A (en) 1994-12-23 1996-06-11 Micron Technology Inc. Burst EDO memory device
US5682354A (en) * 1995-11-06 1997-10-28 Micron Technology, Inc. CAS recognition in burst extended data out DRAM
US5610864A (en) 1994-12-23 1997-03-11 Micron Technology, Inc. Burst EDO memory device with maximized write cycle timing
US5640364A (en) * 1994-12-23 1997-06-17 Micron Technology, Inc. Self-enabling pulse trapping circuit
US6525971B2 (en) 1995-06-30 2003-02-25 Micron Technology, Inc. Distributed write data drivers for burst access memories
US5729504A (en) * 1995-12-14 1998-03-17 Micron Technology, Inc. Continuous burst edo memory device
US7681005B1 (en) * 1996-01-11 2010-03-16 Micron Technology, Inc. Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation
US6401186B1 (en) 1996-07-03 2002-06-04 Micron Technology, Inc. Continuous burst memory which anticipates a next requested start address
US6981126B1 (en) 1996-07-03 2005-12-27 Micron Technology, Inc. Continuous interleave burst access
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4079462A (en) * 1976-05-07 1978-03-14 Intel Corporation Refreshing apparatus for MOS dynamic RAMs
US4303993A (en) * 1979-10-10 1981-12-01 Honeywell Information Systems Inc. Memory present apparatus
JPS5798174A (en) * 1980-12-09 1982-06-18 Hitachi Ltd Semiconductor storage device
JPS58196671A (ja) * 1982-05-10 1983-11-16 Hitachi Ltd 半導体記憶素子
JPS5975494A (ja) * 1982-10-25 1984-04-28 Hitachi Ltd 半導体記憶装置
JPS59139195A (ja) * 1983-01-26 1984-08-09 Mitsubishi Electric Corp 半導体記憶装置

Also Published As

Publication number Publication date
EP0213395A2 (en) 1987-03-11
EP0213395A3 (en) 1988-08-24
DE3677672D1 (de) 1991-04-04
US4750839A (en) 1988-06-14
EP0213395B1 (en) 1991-02-27
JPS62103895A (ja) 1987-05-14

Similar Documents

Publication Publication Date Title
JPH0529989B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
US5349566A (en) Memory device with pulse circuit for timing data output, and method for outputting data
US7275200B2 (en) Transparent error correcting memory that supports partial-word write
US6351427B1 (en) Stored write scheme for high speed/wide bandwidth memory devices
US5155705A (en) Semiconductor memory device having flash write function
US6023434A (en) Method and apparatus for multiple row activation in memory devices
US6633504B1 (en) Synchronous DRAM having test mode in which automatic refresh is performed according to external address and automatic refresh method
JP4065687B2 (ja) 半導体メモリ装置
US5544101A (en) Memory device having a latching multiplexer and a multiplexer block therefor
US5848015A (en) Bitline precharge halt access mode for low power operation of a memory device
JPH09147551A (ja) メモリデバイス回路及びマルチバンクメモリアレイのマルチバンク列の同時アドレス方法
US7466623B2 (en) Pseudo SRAM capable of operating in continuous burst mode and method of controlling burst mode operation thereof
JPH03147152A (ja) メモリ・システム
US6067273A (en) Semiconductor memory burst length count determination detector
US5801996A (en) Data path for high speed high bandwidth DRAM
US6219283B1 (en) Memory device with local write data latches
JPH07211077A (ja) 半導体記憶装置
US5381363A (en) Method and circuitry for performing a hidden read-modify-write
JP3344926B2 (ja) ワード線多重選択可能な半導体記憶装置
US5701273A (en) Memory device
US6044433A (en) DRAM cache
USRE41013E1 (en) Method of and apparatus for providing look ahead column redundancy access within a memory
US7505358B2 (en) Synchronous semiconductor memory device
US6678193B2 (en) Apparatus and method for tracking between data and echo clock
JPH1021687A (ja) 半導体記憶装置

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees