JPH05291241A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05291241A JPH05291241A JP13553892A JP13553892A JPH05291241A JP H05291241 A JPH05291241 A JP H05291241A JP 13553892 A JP13553892 A JP 13553892A JP 13553892 A JP13553892 A JP 13553892A JP H05291241 A JPH05291241 A JP H05291241A
- Authority
- JP
- Japan
- Prior art keywords
- base body
- semiconductor substrate
- semiconductor device
- electrode
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、高耐圧化を図った半導
体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a high breakdown voltage.
【0002】[0002]
【従来の技術】従来、半導体装置を高耐圧化する手段と
して、フィールドプレート構造やガードリング構造をと
ることによって、半導体基体中における電界集中を緩和
する方法がとられてきた。2. Description of the Related Art Heretofore, as a means for increasing the breakdown voltage of a semiconductor device, a method of relaxing an electric field concentration in a semiconductor substrate by taking a field plate structure or a guard ring structure has been taken.
【0003】[0003]
【発明が解決しようとする課題】解決しようとする問題
点は、半導体基体に化合物半導体、特にガリウム砒素G
aAsを用いた半導体基体の表面側に第1の電極を、そ
の裏面側に第2の電極を設けた半導体装置では、その半
導体基体の表面準位が高く、表面に電界が集中しやすく
て、フィールドプレート構造やガードリング構造によっ
ては充分な高耐圧化を図ることができないことである。The problem to be solved is that the semiconductor substrate is a compound semiconductor, especially gallium arsenide G.
In the semiconductor device in which the first electrode is provided on the front surface side of the semiconductor substrate using aAs and the second electrode is provided on the back surface side thereof, the surface level of the semiconductor substrate is high, and the electric field is easily concentrated on the surface. Depending on the field plate structure and the guard ring structure, it is impossible to achieve a sufficiently high breakdown voltage.
【0004】[0004]
【課題を解決するための手段】本発明は、半導体基体の
表面における電界集中を抑制して高耐圧化を充分に図る
べく、半導体基体の表面に接して半導体基体表面との界
面準位が低い誘電体層を設けて、半導体基体の表面電位
を低下させるようにしている。According to the present invention, in order to suppress the electric field concentration on the surface of the semiconductor substrate and to sufficiently increase the breakdown voltage, the interface state with the surface of the semiconductor substrate is low in contact with the surface of the semiconductor substrate. A dielectric layer is provided to lower the surface potential of the semiconductor substrate.
【0005】[0005]
【実施例】本発明による半導体装置にあっては、図1に
示すように、ガリウム砒素GaAsのn(+)層11お
よびn層12からなる高抵抗半導体基体1の表面側に拡
散によって形成されたp型領域2の部分に対向してフィ
ールドプレート構造をもった金属電極3が、またその半
導体基体1の裏面側には裏面電極4がそれぞれ設けられ
ており、半導体基体1の表面側において、金属電極3の
当接部分以外で、半導体基体1の表面に接して、その表
面準位を抑制する物質、例えばアルミガリウム砒素から
なる半導体基体1の表面との界面準位が低い誘電体層5
が形成され、さらにその上にSiO2,SiON,Si
Nなどからなる保護膜6が形成されており、その保護膜
6上に金属電極3のフィールドプレート部分が接するよ
うに構成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, a semiconductor device according to the present invention is formed by diffusion on the surface side of a high resistance semiconductor substrate 1 consisting of n (+) layer 11 and n layer 12 of gallium arsenide GaAs. Further, a metal electrode 3 having a field plate structure is provided facing the portion of the p-type region 2, and a back surface electrode 4 is provided on the back surface side of the semiconductor substrate 1, and on the front surface side of the semiconductor substrate 1, A dielectric layer 5 which is in contact with the surface of the semiconductor substrate 1 except the contact portion of the metal electrode 3 and which has a low interface state with the surface of the semiconductor substrate 1 made of, for example, aluminum gallium arsenide.
Is formed, and further SiO 2 , SiON, Si
A protective film 6 made of N or the like is formed, and the field plate portion of the metal electrode 3 is in contact with the protective film 6.
【0006】しかして、このように構成された本発明に
よる半導体装置によれば、誘電体層5によって半導体基
体1の表面での準位形成が緩和され、電界集中が起きに
くくなり、フィールドプレート手段を用いた高耐圧化に
有効となる。According to the semiconductor device of the present invention having such a structure, however, the level formation on the surface of the semiconductor substrate 1 is relaxed by the dielectric layer 5, and the electric field concentration is less likely to occur. Is effective for high withstand voltage.
【0007】図中、7は空乏層を示している。In the figure, 7 indicates a depletion layer.
【0008】それに対して、図3に示す従来構造の半導
体装置では、フィールドプレート構造をもった金属電極
3の当接部分以外で、半導体基体1の表面に接して、そ
の表面安定化のために保護膜6しか設けられていないの
で、特にガリウム砒素GaAsでは半導体基体1の表面
に形成される準位により生ずる電界集中が顕著となり、
フィールドプレー卜手段を導入しても充分な高耐圧化を
図ることが困難となっている。On the other hand, in the conventional semiconductor device shown in FIG. 3, the surface of the semiconductor substrate 1 is in contact with the surface of the semiconductor substrate 1 except for the contact portion of the metal electrode 3 having the field plate structure to stabilize the surface. Since only the protective film 6 is provided, especially in gallium arsenide GaAs, the electric field concentration caused by the level formed on the surface of the semiconductor substrate 1 becomes remarkable,
It is difficult to achieve a sufficiently high breakdown voltage even if field play means is introduced.
【0009】図2は本発明の他の実施例を示すもので、
この場合は、ガリウム砒素GaAsのn(+)層11お
よびn層12からなる半導体基体1の表面側に拡散によ
って形成されたp型領域2の部分に対向して金属電極8
が、またその半導体基体1の裏面側には裏面電極4がそ
れぞれ設けられ、その半導体基体1にp型のガードリン
グ9が形成されたものにあって、半導体基体1の表面側
において、金属電極8の当接部分以外で、半導体基体1
の表面に接して、その表面準位を抑制する物質、例えば
アルミガリウム砒素からなる半導体基体1の表面との界
面準位が低い誘電体層5が形成され、さらにその上にS
iO2,SiON,SiNなどからなる保護膜6が形成
されている。FIG. 2 shows another embodiment of the present invention.
In this case, the metal electrode 8 is opposed to the portion of the p-type region 2 formed by diffusion on the surface side of the semiconductor substrate 1 composed of the n (+) layer 11 and the n layer 12 of gallium arsenide GaAs.
However, a back electrode 4 is provided on the back surface side of the semiconductor substrate 1, and a p-type guard ring 9 is formed on the semiconductor substrate 1, and the metal electrode is provided on the front surface side of the semiconductor substrate 1. 8 except the abutting portion of the semiconductor substrate 1
A dielectric layer 5 having a low interface level with the surface of the semiconductor substrate 1 made of a substance that suppresses the surface level, for example, aluminum gallium arsenide, is formed in contact with the surface of S, and S is further formed thereon.
A protective film 6 made of iO 2 , SiON, SiN or the like is formed.
【0010】このように構成されたものにあっても、前
記実施例の場合と同様に、誘電体層5によって半導体基
体1の表面での準位形成が緩和され、電界集中が起きに
くくなり、ガードリング9を用いた高耐圧化に有効とな
る。Even in the structure as described above, the level formation on the surface of the semiconductor substrate 1 is alleviated by the dielectric layer 5 as in the case of the above-mentioned embodiment, and the electric field concentration hardly occurs. This is effective for increasing the withstand voltage using the guard ring 9.
【0011】本発明は、以上説明した半導体基体1とし
てガリウム砒素GaAsを用いたものに限らず、他の半
導体基体を用いた場合にも同様に実施することにより高
耐圧化を有効に図ることができることはいうまでもな
い。The present invention is not limited to the one using gallium arsenide GaAs as the semiconductor substrate 1 described above, but it can be effectively carried out in the same manner when another semiconductor substrate is used to effectively increase the breakdown voltage. It goes without saying that you can do it.
【0012】[0012]
【発明の効果】以上、本発明による半導体装置によれ
ば、半導体基体の表面に接して半導体基体表面との界面
準位が低い誘電体層を設けることにより、半導体基体1
の表面での準位形成を緩和して電界集中が起きにくくな
るようにすることができ、簡単な手段により高耐圧化を
有効に図ることができるという利点を有している。As described above, according to the semiconductor device of the present invention, the semiconductor substrate 1 is provided by providing the dielectric layer in contact with the surface of the semiconductor substrate and having a low interface state with the surface of the semiconductor substrate.
There is an advantage that the level formation on the surface of the can be relaxed so that electric field concentration is less likely to occur, and the high breakdown voltage can be effectively achieved by a simple means.
【図1】本発明の一実施例による半導体装置を示す正断
面図である。FIG. 1 is a front sectional view showing a semiconductor device according to an embodiment of the present invention.
【図2】本発明の他の実施例による半導体装置を示す正
断面図である。FIG. 2 is a front sectional view showing a semiconductor device according to another embodiment of the present invention.
【図3】従来の半導体装置を示す正断面図である。FIG. 3 is a front cross-sectional view showing a conventional semiconductor device.
1 半導体基体 2 p型領域 3 フィールドプレート構造をもった金属電極 4 裏面電極 5 誘電体層 6 保護膜 7 空乏層 8 金属電極 9 ガードリング 1 semiconductor substrate 2 p-type region 3 metal electrode having a field plate structure 4 back electrode 5 dielectric layer 6 protective film 7 depletion layer 8 metal electrode 9 guard ring
Claims (3)
の裏面側に第2の電極を設けた半導体装置において、半
導体基体の表面に接して、半導体基体表面との界面準位
が低い誘電体層を設けたことを特徴とする半導体装置。1. A semiconductor device having a first electrode on the front surface side of a semiconductor substrate and a second electrode on the back surface side thereof, in contact with the surface of the semiconductor substrate, and having a low interface state with the surface of the semiconductor substrate. A semiconductor device having a dielectric layer.
に、第1の電極をフィールドプレート構造とし、そのフ
ィールドプレート部分が保護膜上に当接するようにした
ことを特徴とする前記第1項の記載による半導体装置。2. The protective film is formed on the dielectric layer, the first electrode has a field plate structure, and the field plate portion is in contact with the protective film. The semiconductor device according to the description.
に、半導体基体中にガードリングを形成したことを特徴
とする前記1項の記載による半導体装置。3. The semiconductor device according to claim 1, wherein a protective film is formed on the dielectric layer and a guard ring is formed in the semiconductor substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13553892A JPH05291241A (en) | 1992-04-10 | 1992-04-10 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13553892A JPH05291241A (en) | 1992-04-10 | 1992-04-10 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05291241A true JPH05291241A (en) | 1993-11-05 |
Family
ID=15154125
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13553892A Pending JPH05291241A (en) | 1992-04-10 | 1992-04-10 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05291241A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6316794B1 (en) | 1998-04-22 | 2001-11-13 | Fuji Electric Co., Ltd. | Lateral high voltage semiconductor device with protective silicon nitride film in voltage withstanding region |
JP2005203658A (en) * | 2004-01-19 | 2005-07-28 | Sanken Electric Co Ltd | Semiconductor device |
-
1992
- 1992-04-10 JP JP13553892A patent/JPH05291241A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6316794B1 (en) | 1998-04-22 | 2001-11-13 | Fuji Electric Co., Ltd. | Lateral high voltage semiconductor device with protective silicon nitride film in voltage withstanding region |
US6558983B2 (en) | 1998-04-22 | 2003-05-06 | Fuji Electric Co., Ltd. | Semiconductor apparatus and method for manufacturing the same |
JP2005203658A (en) * | 2004-01-19 | 2005-07-28 | Sanken Electric Co Ltd | Semiconductor device |
JP4697384B2 (en) * | 2004-01-19 | 2011-06-08 | サンケン電気株式会社 | Semiconductor device |
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