JPH01125870A - Gallium arsenide schottky barrier semiconductor device - Google Patents

Gallium arsenide schottky barrier semiconductor device

Info

Publication number
JPH01125870A
JPH01125870A JP28355687A JP28355687A JPH01125870A JP H01125870 A JPH01125870 A JP H01125870A JP 28355687 A JP28355687 A JP 28355687A JP 28355687 A JP28355687 A JP 28355687A JP H01125870 A JPH01125870 A JP H01125870A
Authority
JP
Japan
Prior art keywords
schottky barrier
gaas
type semiconductor
electrode
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28355687A
Other languages
Japanese (ja)
Inventor
Takeshi Konuma
小沼 毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP28355687A priority Critical patent/JPH01125870A/en
Publication of JPH01125870A publication Critical patent/JPH01125870A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To protect a GaAs-FET from reduction in noise index by a method wherein a Ti-Al-Ti layer is formed to serve as a Schottky electrode on an N-GaAs substrate. CONSTITUTION:As the material for a Schottky barrier on an N-GaAs substrate, a metal layer Ti-Al-Ti is used. That is, on a semi-insulating GaAs substrate 1, a high resistance buffer layer 2, an N-type semiconductor layer 3, and an M<+>-type semiconductor layer 4 are formed. Formation further follows of a mesa section 5, a recess section 6, and ohmic electrodes that are a source electrode 7 and a drain electrode 8. A gate electrode 9 is formed by vacuum evaporation wherein Ti, Al, and again Ti, are deposited in succession. After deposition of silicon nitride as a surface protecting film, heat treatment is accomplished for stabilization. The result is an N-GaAs Schottky barrier type semiconductor device free of changes from the passage of time and excellent in FET characteristics.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はn型砒化ガリウム(以下n−GaムSと略す)
を用いたショットキ障壁型半導体装置、特に電界効果ト
ランジスタ(以下FITと略す)に関する。
[Detailed Description of the Invention] Industrial Field of Application The present invention relates to n-type gallium arsenide (hereinafter abbreviated as n-GaM S).
The present invention relates to a Schottky barrier type semiconductor device using a Schottky barrier type semiconductor device, particularly a field effect transistor (hereinafter abbreviated as FIT).

従来の技術 GaAgシヲットキ障壁型電界効果トランジスタ(以下
GaAs −F g Tと略す)は、n−GaASが材
料的に飽和速度が大きいので、高速、高周波半導体装置
として広く用いられている。GaAs −FETのショ
ットキ障壁となるゲートa極材料としては、種々の材料
が用いられている。例えばアルミニウム(以下hlと略
す) 、 Ad−チタン(以下Tiと略す)、T1−白
金(以下ptと略す)−金(以下ムUと略す)、タング
ステン(以下Wと略す)等多くの材料がある。単体のG
a As−FICTのゲート電極としてはA、5−Ti
  が多く用いられている。
2. Description of the Related Art GaAg Schottky barrier field effect transistors (hereinafter abbreviated as GaAs-F g T) are widely used as high-speed, high-frequency semiconductor devices because n-GaAS has a high saturation speed as a material. Various materials are used as gate a-electrode materials that serve as Schottky barriers in GaAs-FETs. For example, there are many materials such as aluminum (hereinafter abbreviated as HL), Ad-titanium (hereinafter abbreviated as Ti), T1-platinum (hereinafter abbreviated as PT)-gold (hereinafter abbreviated as U), tungsten (hereinafter abbreviated as W), etc. be. Single G
a As the gate electrode of As-FICT, A, 5-Ti
is often used.

発明が解決しようとする問題点 このゲート成極材料はA4でショットキ障壁をn−Ga
ASと形成し、Tiでムeのエレクトロマイグレーショ
ンを防止している。ke−Ti  からなるゲート電極
はゲート抵抗が低い、電画の加工が容易である等の多く
の長所を有しているが、ショットキ界面にトラップ準位
を形成しゃすぐ、GaAs −F E Tの特性が経時
変化するという問題がある。
Problems to be Solved by the Invention This gate polarization material is A4 with a Schottky barrier of n-Ga.
It is formed with AS, and Ti prevents electromigration of mu. Although the gate electrode made of ke-Ti has many advantages such as low gate resistance and easy processing of electrolytic images, it is difficult to form trap levels at the Schottky interface, making it difficult to use in GaAs-FET. There is a problem that the characteristics change over time.

本発明は上記の問題に鑑み、GaAs −F E Tの
ゲート電極としてAβ−Tiのゲー[極を改良し、経時
変化のないショットキ障壁用材料を提供することを目的
とする。
In view of the above problems, an object of the present invention is to improve a gate electrode of Aβ-Ti as a gate electrode of a GaAs-FET, and to provide a material for a Schottky barrier that does not change over time.

問題点を解決するための手段 本発明はI’m−GILAsに用いるショットキ障壁用
材料として、T1−ム1−Tiからなる金属を用いる。
Means for Solving the Problems The present invention uses a metal consisting of T1-Ti as the Schottky barrier material used in I'm-GILAs.

作用 本発明により、経時変化がなく、良好なFET特性を有
するn−GaAsショア)キ障壁型半導体装置を提供す
る。
Effect of the Invention The present invention provides an n-GaAs shore barrier type semiconductor device which does not change over time and has good FET characteristics.

実施例 本発明の一実施例としてGaAs −F E Tについ
て図を用いて説明する。図は本発明の一実施例のショッ
トキ障壁型GLA5− FgTの構造を示す断面図であ
る。
EXAMPLE As an example of the present invention, a GaAs-FET will be explained with reference to the drawings. The figure is a sectional view showing the structure of a Schottky barrier type GLA5-FgT according to an embodiment of the present invention.

半絶縁Ga As基板1にエピタキシャル法を用いて、
高抵抗バッファ層2、キャJ ヤl11度4 X 10
”1、厚み0.1μmのn型半導体層3、キャリヤ濃度
2 X 1018d 、厚み0.1511mのn+型半
導体4を形成する。欠いて化学エツチングを用いて、メ
サ部6、リセス部6を形成する。通常の写真食刻法とリ
フトオフ法を用いて、オーミックtiを形成し、ソース
電極7、ドレイン電極8を形成する。次にゲート電極9
として、Ti500人、h13000人、Ti500人
を連続真空蒸着法を用いて形成する。表面保護膜として
窒化シリコンを3000人堆積する。(図示せず)しか
る後、360°Cで30分間水素雰囲気中で安定化のた
めの熱処理をして、FETの製作が終る。製作したFE
Tのゲート長は0.311m 、ゲート巾は200μm
である。
Using an epitaxial method on a semi-insulating GaAs substrate 1,
High resistance buffer layer 2, layer 11 degrees 4 x 10
1. Form an n-type semiconductor layer 3 with a thickness of 0.1 μm, a carrier concentration of 2×1018d, and an n+-type semiconductor 4 with a thickness of 0.1511 m. Mesa portion 6 and recess portion 6 are formed using chemical etching. An ohmic Ti is formed using a normal photolithography method and a lift-off method, and a source electrode 7 and a drain electrode 8 are formed.Next, a gate electrode 9 is formed.
As a result, 500 Ti, 13000 H, and 500 Ti are formed using a continuous vacuum deposition method. 3,000 silicon nitride layers are deposited as a surface protection film. (Not shown) Thereafter, a heat treatment is performed for stabilization at 360° C. for 30 minutes in a hydrogen atmosphere, and the fabrication of the FET is completed. The manufactured FE
T gate length is 0.311m, gate width is 200μm
It is.

上記と同一方法でゲート電極として、A43o00人、
Ti5oo入のFETを製作し、本発明と信頼性の比較
をした。信頼性の条件としては120″Cでドレイン電
流25mA条件に試料を500時間、1000時間放置
した後、試作の雑音指数を測定した。雑音指数の測定条
件としては、12 GHz  で、ドレイン電流10m
ムで測定した。
A43o00 person as a gate electrode in the same method as above,
A FET containing Ti5oo was manufactured and its reliability was compared with that of the present invention. The reliability conditions were 120"C and a drain current of 25mA, after which the sample was left for 500 and 1000 hours, and then the noise figure of the prototype was measured.The noise figure measurement conditions were 12 GHz and a drain current of 10mA.
Measured using

試料は本発明、従来例とも50ット試作し、各ロフトか
ら任意に100ケ選別し、6o○ケずつ信頼性試験を行
った。本発明、従来例とも初期値の雑音指数は1.2±
o、2dBの試料を用いた。信頼性試験に於ける良否の
判定は雑音指数が1.6dB以北を不良とした。次表に
信頼性試験に於ける累積不良の個数を示す。
50 samples were produced for both the present invention and the conventional example, 100 samples were arbitrarily selected from each loft, and a reliability test was conducted on 60 samples each. The initial noise figure for both the present invention and the conventional example is 1.2±
A sample of 2 dB was used. In the reliability test, a product with a noise figure of 1.6 dB or higher was judged to be defective. The following table shows the cumulative number of defects in reliability tests.

この表から本発明の劣化が極端に少ないことは明白であ
る。不良の原因を検討した結果、本発明の不良の1ケは
オーミック電極の劣化に伴う、ソース抵抗の増大であっ
た。一方従来例の1000時間での不良の23ケの内2
ヶがオーミ、、り電極の劣化に伴う、ソース抵抗の増大
であり、他の21ケはSパラメータの測定から相互コン
ダクタンスの減少、ゲート抵抗の増大が見られた。
From this table, it is clear that the deterioration of the present invention is extremely small. As a result of examining the causes of defects, one defect in the present invention was found to be an increase in source resistance due to deterioration of the ohmic electrode. On the other hand, 2 out of 23 defects in the conventional example after 1000 hours
In one case, the source resistance increased due to deterioration of the ohmic and diode electrodes, and in the other 21 cases, S-parameter measurements showed a decrease in mutual conductance and an increase in gate resistance.

本発明のゲート電極を用いることで、雑音指数の劣化の
少ない原因は明らかではないが、本発明のゲート電極の
方がショットキ界面及びゲート電極材の変化が少ないの
ではないかと推測している。
The reason why the noise figure deteriorates less when using the gate electrode of the present invention is not clear, but it is speculated that the gate electrode of the present invention causes fewer changes in the Schottky interface and gate electrode material.

実施例nはGaAs −F E Tで説明したが、Ga
Asショットキダイオードにも適用できることは勿論で
ある。又2次元電子ガスを用いたデバイスにも適用でき
ることは勿論である。
Example n was explained using GaAs-FET, but GaAs-FET
Of course, it can also be applied to As Schottky diodes. It goes without saying that the present invention can also be applied to devices using two-dimensional electron gas.

発明の詳細 な説明したように、本発明はn−GaAsにTi−A 
l −T iからなる金属層をショットキ電極と17で
用いることで、GaAs −F RTの雑音指数の劣化
を抑制することが出来、その工業的価匝は大なるものが
ある。
As described in detail, the present invention provides Ti-A to n-GaAs.
By using a metal layer made of l-Ti as the Schottky electrode 17, it is possible to suppress the deterioration of the noise figure of the GaAs-F RT, and its industrial value is great.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の一実施例であるシヨ・ントキ障壁型GaA
S −F K Tの構造を示す断面図である。 1・・・・・・半絶縁性Ga As基板、2・・・・・
・高抵抗バッファ層、3・・・・・・n型半導体層、4
・・・・・・n+半導体層、5・・・・・・メサ部、6
・・・・・・リセス部、7・・・・・・ソース成嘆、8
・・・・・・ドレイン電極、9・・・・・・Ti−Al
 −T1 からなるゲート4極。
The figure shows a typical barrier type GaA that is an embodiment of the present invention.
It is a sectional view showing the structure of S-FKT. 1... Semi-insulating Ga As substrate, 2...
・High resistance buffer layer, 3...n-type semiconductor layer, 4
......n+ semiconductor layer, 5...Mesa part, 6
・・・Recess part, 7... Sauce admiration, 8
...Drain electrode, 9...Ti-Al
- Gate quadrupole consisting of T1.

Claims (1)

【特許請求の範囲】[Claims]  n型砒化ガリウム結晶表面にチタン(Ti)−アルミ
ニウム(Al)−チタン(Ti)からなる金属層を設け
、この金属層と前記n型砒化ガリウム結晶との界面にシ
ョットキ障壁を形成せしめてなる砒化ガリウムショット
キ障壁型半導体装置。
Arsenide formed by providing a metal layer made of titanium (Ti)-aluminum (Al)-titanium (Ti) on the surface of an n-type gallium arsenide crystal and forming a Schottky barrier at the interface between this metal layer and the n-type gallium arsenide crystal. Gallium Schottky barrier type semiconductor device.
JP28355687A 1987-11-10 1987-11-10 Gallium arsenide schottky barrier semiconductor device Pending JPH01125870A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28355687A JPH01125870A (en) 1987-11-10 1987-11-10 Gallium arsenide schottky barrier semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28355687A JPH01125870A (en) 1987-11-10 1987-11-10 Gallium arsenide schottky barrier semiconductor device

Publications (1)

Publication Number Publication Date
JPH01125870A true JPH01125870A (en) 1989-05-18

Family

ID=17667055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28355687A Pending JPH01125870A (en) 1987-11-10 1987-11-10 Gallium arsenide schottky barrier semiconductor device

Country Status (1)

Country Link
JP (1) JPH01125870A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010157601A (en) * 2008-12-26 2010-07-15 Sanken Electric Co Ltd Semiconductor device, and method of manufacturing the same
US9605671B2 (en) 2013-04-26 2017-03-28 Kobe Steel, Ltd. Reciprocating compressor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56100480A (en) * 1980-01-11 1981-08-12 Nec Corp Electric field effect transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56100480A (en) * 1980-01-11 1981-08-12 Nec Corp Electric field effect transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010157601A (en) * 2008-12-26 2010-07-15 Sanken Electric Co Ltd Semiconductor device, and method of manufacturing the same
US9605671B2 (en) 2013-04-26 2017-03-28 Kobe Steel, Ltd. Reciprocating compressor

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