JPH0271563A - Semiconductor device, insulated gate type field effect transistor and schottky gate type field effect transistor - Google Patents

Abstract

PURPOSE:To control the occupation factor of carriers at an interface level by a method wherein a Dirac delta doped layer is formed on a compound semiconductor layer making its base reach the depth equal to a debye length or less from the surface of the semiconductor layer. CONSTITUTION:An n-type GaAs layer 12 is epitaxially grown on a semi- insulating GaAs substrate 11 through an MBE method so as to have a specified thickness, and then Si is epitaxially grown thereon in a single atomic layer to form a delta doped layer 13. Then, an n-type GaAs layer is epitaxially grown again on the delta doped layer 13 to make the n-type GaAs layer 12 as thick as specified. And, an AuGe/Ni film is formed on the whole face, which is patterned through etching and then subjected to a heat treatment to make the AuGe/Ni film and the n-type GaAs layer 12 alloyed for the formation of a source 16 and a drain 17. Then, an insulating film is formed on the whole face, which is patterned through etching to form a gate insulating film 14. Next, a metal film of Al or Au is formed on the whole face, which is patterned through etching for the formation of a gate electrode 15. By this set-up, the occupation factor of carriers at an interface level can be controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, an insulated gate field effect transistor, and a Schottky gate field effect transistor using a Dirac-delta doped layer.

[Summary of the invention]

In the semiconductor device according to the present invention, a Dirac-delta doped layer is formed at a depth below the Debye length from the surface of the compound semiconductor layer. Thereby, when a gate insulating film is formed on a compound semiconductor layer, it is possible to control the occupation rate of carriers in the interface states existing at the interface thereof.

Further, the insulated gate field effect transistor according to the present invention includes a Dirac-Derk dove layer and a channel layer, which are formed at a depth equal to or less than the Debye length from the surface of the compound semiconductor layer. As a result, a high-performance insulated gate field effect transistor using a compound semiconductor can be realized.

Furthermore, the Schottky gate field effect transistor according to the present invention further includes a first Dirac-delta doped layer formed at a depth d1 below the Debye length from the surface of the compound semiconductor layer, and a first Dirac-delta doped layer formed at a depth d1 from the surface of the compound semiconductor layer. d!
(where d,>d), and a second Dirac-delta doped layer. This makes it possible to realize a Schottky gate field effect transistor with extremely large transconductance.

(Conventional technology) M OS (Metal Oxide Sem1con
MIS represented by F.E.T.
(Metal In5lator Sem1cond
FET has achieved high performance using silicon (St), but on the other hand, MISF has been developed using compound semiconductors such as gallium arsenide (GaAs)
Attempts have been made to realize ET.

In addition, as a prior art document regarding a semiconductor device using a Dirac-delta doped layer, for example, JP-A-61-1
Publication No. 66081 is mentioned.

[Problem to be solved by the invention]

However, when using a compound semiconductor such as GaAs,
MISF has desired characteristics due to the presence of many interface states at the interface between the compound semiconductor and the gate insulating film.
It was difficult to realize ET.

Therefore, an object of the present invention is to provide a semiconductor device in which when a gate insulating film is formed on a compound semiconductor layer, the occupancy rate of carriers in the interface state existing at the interface between the gate insulating films can be controlled.

Another object of the present invention is to provide a high-performance insulated gate field effect transistor using a compound semiconductor.

Another object of the present invention is to provide a Schottky gate field effect transistor with extremely large transconductance.

[Means to solve the problem]

In the semiconductor device according to the present invention, a compound semiconductor layer (
A Dirac-delta doped I'1i (13) is formed at a depth equal to or less than the Debye length from the surface of 12, 18).

The insulated gate field effect transistor according to the present invention has a Dirac-delta doped layer (12, 18) formed at a depth equal to or less than the Debye length from the surface of the compound semiconductor layer (12, 18).
3) and a channel layer (12, 19).

The Schottky gate field effect transistor according to the present invention includes a first Dirac-delta doped 1i (13) formed at a depth dl below the Debye length from the surface of the compound semiconductor layer (18); The second layer is formed at a depth dt (d,>dI) from the surface.
Dirac-delta doped layer (19).

Here, the Dirac-delta doped layer refers to a monoatomic layer impurity-doped layer doped with a two-dimensional spread at a certain depth from the surface of the compound semiconductor layer. When two axes are taken in the depth direction from the surface of the compound semiconductor layer, the impurity doping profile when the monoatomic impurity doped layer is formed at a depth d from the surface can be mathematically expressed as Dirac ( Since the layer can be expressed as No (Z)=Nzoδ(z−d) using the delta function of Dirac (Dirac), it is called a Dirac-delta doped layer (hereinafter referred to as δ-doped layer) as described above.

Here, No(z) is the three-dimensional doping concentration, and No is the 2-dimensional doping concentration.
is the dimensional doping concentration.

If the Debye length mentioned above is expressed as D, then D-r-Y
It is 7Ty. Here, ε is the dielectric constant of the compound semiconductor, k is the Boltzmann constant, T is the absolute temperature, q is the unit charge (absolute value of electronic charge), and N is the impurity concentration of the δ-doped layer. This Debye length indicates the thickness of the two-dimensional electron gas (2DEC) that is formed around the position of this δ-doped layer, for example, assuming that the impurity in the δ Be 1 layer is a donor impurity. Its typical value in the present invention is several tens of people.

Therefore, in the present invention, the δ-doped layer is formed near the surface of the compound semiconductor layer.

The channel layer in the insulated gate field effect transistor according to the present invention may be composed of a δ-doped layer, or may be composed of a compound semiconductor uniformly doped with impurities.

[Effect]

Now, as shown in FIG. 1, consider the case where a δ-doped layer 2 is formed at a depth d from the surface of a compound semiconductor N1 such as GaAs, for example. Here, d≦D. A gate insulating film 3 and a gate electrode 4 are formed on the compound semiconductor layer 1. Reference numerals 5 and 6 indicate the source and drain, respectively.

As already mentioned, the compound semiconductor N1 and the gate insulating film 3
At the interface with
There exists an interface state (of the order of l3c1), which has been a factor that has hindered the realization of MISFETs using compound semiconductors.

However, this problem can be solved by forming the δ-doped layer 2 from the surface of the compound semiconductor N1 to a depth d equal to or less than the Debye length, as described above. That is, considering the case where the impurity of the δ-doped layer 2 is, for example, a donor impurity, the concentration n3 of 20EG formed by electrons from the donor impurity can be set to about 10''C11-''. Therefore, when the gate voltage v6=0, this 2DE
By supplying G electrons to the interface between the compound semiconductor layer 1 and the gate insulating film 3, the interface level existing at the interface between the compound semiconductor layer 1 and the gate insulating film 3 can be almost completely filled. . At this time, the δ-doped layer 2 becomes depleted (
(deplete).

Now, next is the gate voltage ■. When >0 is applied to the gate electrode 4, electrons begin to accumulate in the depleted δ-doped N2. In this case, since the interface level is almost completely filled with electrons as described above, the accumulation of electrons is performed effectively. Once electrons are accumulated in this way and 2DEC is formed in the δ-doped layer 2, this 2DEG
is confined in a V-shaped deep two-dimensional quantum potential well formed by the positive charge of the δ-doped N2 donor ion and the negative charge of the electron. The concentration n of 2DEC in this two-dimensional quantum potential well can be controlled by the gate voltage V. The maximum value of this electron concentration n is proportional to the capacitance between the gate electrode 4 and the δ-doped layer 2,
Since the depth of this δ-doped layer 2 is extremely shallow, for example, about 10 to 30 layers, this capacitance is large, and therefore the maximum value of this concentration n3 is large.

From the above, it is possible to realize a MISFET using a compound semiconductor and also have a large transconductance g.
, and current drive capability.

Next, consider a Schottky gate field effect transistor in which two δ-doped layers are formed in a compound semiconductor layer.

FIG. 2 shows the relationship between the depth d of the δ-doped layer and the 2DEC concentration n8 in the case where one δ-doped layer is formed in the compound semiconductor layer and the case where two δ-doped layers are formed.

However, when there are two δ-doped layers, the depth d of the upper δ-doped layer is fixed to 10, and the depth d2 of the lower δ-doped layer is set to d.

As can be seen from Fig. 2, when there is only one δ-doped layer, the depth d of the δ-doped layer must be adjusted to about 100 to 200 layers in order to obtain a high concentration n of about 10 cm- or more. It is necessary to On the other hand, when there are two δ-doped layers, the interface level is almost completely filled with electrons supplied from the upper δ-doped layer, as mentioned above.
It can be seen that even if the lower δ-doped layer is formed at a shallow depth of about 30 to 40 layers from the surface, a relatively high concentration n of 10I3c11- can be obtained. This 10"C11l-
The concentration nl corresponds to a volume concentration of about 10 cm-', which is an electron concentration similar to that of a metal.

Therefore, the 2D
By using EC as a channel, the distance between the gate electrode and the channel can be extremely shortened, and thereby a large transconductance g1 can be obtained. When the depth d2 of the δ-doped layer is 30, considering that the dielectric constant of GaAs is approximately three times that of SiO□, MOS FET using Si
The thickness of the gate insulating film, that is, the SiO□ film is approximately 30 mm.
This corresponds to the case where people/3=10 people. Since the capacitance between the gate electrode and the channel is inversely proportional to log d, in this case the transconductance g, is ~log10
= It is possible to improve by ~3 times.

As can be seen from the above description, according to the semiconductor device according to the present invention, when a gate insulating film is formed on a compound semiconductor layer, the interface states existing at the interface thereof are replaced by carriers supplied from the δ-doped layer. This makes it possible to almost completely fill the interface state, thereby controlling the occupation rate of carriers in the interface state.

Further, according to the insulated gate field effect transistor according to the present invention, the interface level existing at the interface between the compound semiconductor layer and the gate insulating film can be almost completely filled with carriers supplied from the δ-doped layer. Carriers can be effectively induced into the channel layer. As a result, using a compound semiconductor, transconductance gl
A high-performance insulated gate field effect transistor with a large I and high current drive capability can be realized.

Furthermore, according to the Schottky gate field effect transistor according to the present invention, the second δ-doped layer can be formed at a shallow depth from the surface of the compound semiconductor layer, so that the distance between the Schottky gate electrode and the channel can be reduced. can be short (by which the transconductance g,
can be made larger.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. In addition, in all the figures of the embodiment, parts having the same function are given the same reference numerals.

Figure 3 above shows GaAs M I according to Example ① of the present invention.
5FET is shown.

As shown in FIG. 3, GaAsMI according to this Example I
In the SFET, an n-type GaAsJti 12 forming a channel layer is formed on a semi-insulating GaAs substrate 11. To give an example of the thickness and impurity concentration of this n-type GaAs layer 12, the impurity concentration is 3×1017C1n-
3, thickness 1000mm, impurity concentration 10180I1
1-3, the thickness is 200-300 people. In this n-type GaAs layer 12, a δBe-1 layer 13 is formed at a depth of, for example, about 20 layers from the surface thereof. This δ
The impurity of the B1 layer 13 is, for example, a donor impurity such as St. Further, on this n-type GaAs layer 12, a gate insulating film 14 such as a Stow film, Ta, O, etc.
Further, on this gate insulating film 14, a gate electrode 15 made of a metal such as aluminum (Al) or gold (Au) is formed. Codes 16 and 17
indicate the source and drain, respectively. These source 16 and drain 17 are made of an ohmic metal for GaAs, such as an AuGe/Ni film, on the n-type GaAs layer 12.
This AuG is formed by heat treatment after being formed on top of the
It is formed by alloying e/Ni with the n-type GaAs layer 12.

Next, the GaAs according to Example I configured as described above is
An example of a method for manufacturing MISFET will be described.

As shown in FIG. 3, first, n-type G
After epitaxially growing the aAs layer 12 to a predetermined thickness, this n-type GaAs layer 12 is grown using the same <MBE method.
A monoatomic layer of a donor impurity, such as St, is epitaxially grown on the δBe1 layer 13. After this, n-type GaA
The s-layer is epitaxially grown again to a thickness of, for example, about 20 layers, thereby making the n-type GaAs layer 12 to a predetermined thickness.

Next, an AuGe/Ni film is formed on the entire surface by, for example, a vapor deposition method, this AuGe/Ni film is patterned into a predetermined shape by etching, and then heat treatment is performed to form a bond between the AuGe/Ni film and the n-type GaAs layer 12. are alloyed, thereby forming a source 16 and a drain 17. Next, an insulating film such as a SiO□ film or a Tag's film is formed on the entire surface by, for example, the CVD method, and then this insulating film is patterned into a predetermined shape by etching to form the gate insulating film 14. Next, after forming a metal film such as AI or Au on the entire surface by, for example, sputtering or vapor deposition, this metal film is patterned into a predetermined shape by etching to form the gate electrode 15. Complete the GaAs MISFET.

According to this embodiment I, the δBe 1 layer 13 is formed at a shallow depth of about 20 degrees from the surface of the n-type GaAs layer 12, so that it is formed at the interface between the n-type GaAs layer 12 and the gate insulating film 14. The existing interface levels can be almost completely filled with electrons supplied from the δBe-1 layer 13. As a result, by applying a gate voltage ■, >0 to the gate electrode 15, electrons supplied from the n-type GaAs layer 12 can be effectively accumulated in the depleted δ-doped Jii 13, and 2DEC (channel) can be formed. Since this 2DEG is formed extremely shallowly from the surface of the n-type GaAs layer 120, the gate electrode 15
The capacity between this and this 2DEC is extremely large.

For this reason, high-performance GaAs MISF with extremely large transconductance g and current drive ability
ET can be realized.

Figure 4 shows a GaAs MISFET according to the embodiment of the present invention.
shows.

As shown in FIG. 4, GaAsMI according to this embodiment
In the SFET, a 2N δ beam 1 is formed in a semi-insulating GaAs layer 18 formed on a semi-insulating GaAs substrate 11.
Layer 13.19 is formed. Here, the depth dl of the upper δBee 1 layer 13 is, for example, about 10 people, and the depth d2 of the lower δBee 1 layer 19 is, for example, about 30 people.

In the method for manufacturing a GaAs MISFET according to this embodiment (2), δ
This method is the same as the method for manufacturing the GaAs MISFET according to Example (2) except for forming the dope N13.19, so the explanation will be omitted.

According to this embodiment (2), the interface level existing at the interface between the semi-insulating GaAs layer 18 and the gate insulating film 14 can be almost completely filled with electrons supplied from the upper δBe1 layer 13. , the 2DEG formed in the underlying δBe-1 layer 19 can be used as a channel. This channel is located extremely shallow from the surface of the semi-insulating GaAs layer 18, and the 2D
The concentration n8 of EG can be as high as about 10"cm-".

For this reason, high-performance GaAs MISF with extremely large transconductance g and current drive capability
ET can be realized.

Disaster relief facility 1 Figures 5A and 5B are GaA according to embodiment ① of the present invention.
s Schottky gate type FET is shown.

As shown in FIGS. 5A and 5B, in the GaAs Schottky gate FET according to this embodiment 18 are formed. Two δ Be 1 layers 13 and 19 are formed in this semi-insulating GaAs layer in one day. The depth d of the upper δBee 1 layer 13 is, for example, about 10 people, and the depth d of the lower δBee 1 layer 19
For example, number 8 is about 30 people. Moreover, this semi-insulating Ga
A Schottky gate electrode 20 having a very fine width of, for example, about 500 nanometers is formed on the As layer.

This Schottky gate electrode 20 is made by forming a film of a metal such as tungsten (W) on a semi-insulating GaAs layer, and then transferring atoms of this metal to a semi-insulating GaAs layer.
It is formed by diffusing and alloying into i18. In this case, the lower end of this Schottky gate electrode 20 is present between the δBe1 layers 13 and 19.

That is, if the depth of the lower end of this Schottky gate electrode 20 is represented by X, then dl<x<d+ +dz. Therefore, in the region below this Schottky gate electrode 20, one layer of δBe1 layer 19 exists, while in the region other than the region below this Schottky gate electrode 20, two layers of δBe1 layer 19 exist. 13.19 will exist.

In this case, the concentration n of 2DEG formed in the δBe 1 layer 19 below the Schottky gate electrode 2o is a value determined from the solid curve in FIG. δ doping 1i on both sides of
The concentration n of 2DEG formed at point 19 is a value determined from the broken line curve in FIG.

In this embodiment (2), the Schottky gate electrode 20
2DE formed at δ-doped N19 in the lower part of
The concentration n of C can be controlled in the range of 0 to 10"Cl11-" by selecting the depth d2 of the δBe-1 layer 19. As can be seen from Fig. 2, the lower limit of d2 is about 20 people, but for example, if d2 is 20 people, the concentration nfi = o of 2 DEC at gate voltage vG-〇
Therefore, a normally-off, ie, enhancement-type Schottky gate FET can be realized.

On the other hand, if d2 is made larger, a normally-on, depletion-type Schottky gate FET
can be realized.

Further, the concentration n1 of 2DEG formed in the δBe 1 layer 19 on both sides of the Schottky gate electrode 20 is 10
As mentioned above, this corresponds to the volume concentration of IQ of about "cm-". Therefore, this part is considered to be in a state similar to that of a heavy metal.

Next, an example of a method for manufacturing the GaAs Schottky gate FET configured as described above will be described.

As shown in FIG. 6A, first, a semi-insulating GaAs substrate 11
For example, by MBE method, semi-insulating GaAs1i! f
After epitaxially growing the layer 18 to a thickness of, for example, several thousand layers, the IN-th δBee 1 layer 19 is formed thereon.

Next, semi-insulating GaAs is again deposited on top of the δBee 1 layer 19.
After growing, for example, about 20 layers, the 2Nth δ-doped N13 layer is formed thereon.

After this, semi-insulating GaA is again placed on this δ-doped layer 13.
The S layer is grown to a thickness of, for example, about 10 layers to obtain a semi-insulating GaAs layer 18 of a desired thickness. Next, for example, an AuGe/Ni film is formed on the entire surface by, for example, a vapor deposition method,
After patterning this into a predetermined shape by etching, heat treatment is performed to alloy the AuGe/Ni film and the semi-insulating GaAs layer 18 to form a source 16 and a drain 17. Next, this semi-insulating GaAsJ
A metal film 21 made of, for example, tungsten (W) is formed on i I B by, for example, sputtering or vapor deposition.

Thereafter, a raw material gas such as alkylnaphthalene is introduced into a high vacuum evacuated sample chamber of an electron beam irradiation device (not shown), and the beam diameter is set on the metal film 21 in the raw material gas atmosphere in this sample chamber. A narrowly focused electron beam 22 is irradiated in a predetermined pattern. The acceleration voltage of this electron beam 22 is, for example, about 6 kV, and the beam current is, for example, about 20 μA.

Further, the pressure of the raw material gas atmosphere is, for example, 10-S to 1
0-@Torr, typically 10-'Torr. By irradiation with the electron beam 22, the source gas is decomposed and a hydrocarbon-based substance is generated on the metal film 2I, thereby forming a resist 23 having an extremely fine width and made of this generated substance. This resist 23 has excellent dry etching resistance.

Next, using this resist 23 as a mask, the metal film 21 is
is anisotropically etched in a direction perpendicular to the substrate surface by, for example, reactive ion etching (RIE) to form a Schottky gate electrode 20 with a very fine width, as shown in FIG. 6B. Thereafter, the resist 23 is removed by etching to obtain the state shown in FIG. 6C.

Next, by performing heat treatment, the metal constituting the Schottky gate electrode 20, such as W, is removed from the semi-insulating GaAs layer 1.
8 so that the lower end of the Schottky gate electrode 20 is between the δ-doped N13.19. - Through this, the target GaAs Schottky gate FET is completed as shown in FIGS. 5A and 5B.

According to this embodiment (2), since the distance between the Schottky gate electrode 20 and the channel made of 2DEG is extremely short, an extremely large transconductance g can be obtained. Further, a channel is formed below the Schottky gate electrode 20 in a self-aligned manner with respect to the Schottky gate electrode 20, and since the Schottky gate electrode 20 has an extremely small width, the channel length is extremely short.

For this reason, bal is tic
) It is possible to perform ultra-high-speed operation close to that of Furthermore, depending on how the depth d2 of the lower δ Be 1 layer 19 is selected, an enhancement type or a debreasisine type Schottky gate type F
Since an ET can be obtained, it is possible to construct a complementary FET.

FIG. 7A shows the current (I)-voltage (()) between the source and gate of the Schottky gate FET in the state shown in FIG. V) Show characteristics. As is clear from FIG. 7A, before this heat treatment, the IV characteristic between the source and the gate is a straight line, indicating ohmic characteristics. Naturally, in this situation,
Schottky gate type FETs do not work. Next, the seventh
Figure B shows the state after the Schottky gate electrode 20 is formed and then subjected to heat treatment, that is, Figure 5A and Figure 5B.
2 shows the I-V characteristics between the source and gate of the Schottky gate FET in the state shown in FIG. As is clear from FIG. 7B, Schottky characteristics are obtained in this state,
Performs FET operation.

FIG. 8 shows an example of measurement of drain current (4)-voltage (4) characteristics of this Schottky gate type FET. 8th
In the figure, the step of the gate voltage Vc is 0.2■. Note that the FET characteristics shown in FIG. 8 are measurement results for a Schottky gate type FET whose element structure and manufacturing process have not been optimized. By optimizing the element structure and manufacturing process of the Schottky gate FET, gl is approximately one order of magnitude higher than g calculated from Figure 8.
It is thought that it is possible to obtain

The dimensions of each part of the Schottky gate FET used to measure the above characteristics (see FIG. 5A) are W9 = 7.
8amSL*a=3.7Hm, Lg=1500 people, L
,,=5000 people.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-mentioned embodiments (various modifications based on the technical idea of the present invention are possible).

For example, in Example 2, the Schottky gate electrode 2
As the material for 0, it is also possible to use a material other than W, such as tungsten silicide (WSiz) or platinum (Pt). In addition, in Example ①, semi-insulating Ga
If, for example, an AIXGaI-XAs (0≦X≦1) layer is formed as a barrier layer between the As substrate 11 and the semi-insulating GaAs layer, when the Schottky gate electrode 20 has an extremely fine width, It is possible to prevent the phenomenon that the channel does not close when it should close, that is, the short channel effect.

〔Effect of the invention〕

As described above, according to the semiconductor device according to the present invention,
When a gate insulating film is formed on a compound semiconductor layer, it is possible to control the occupation rate of carriers in the interface states existing at the interface between the gate insulating film and the compound semiconductor layer.

Further, according to the insulated gate field effect transistor according to the present invention, a high performance insulated gate field effect transistor using a compound semiconductor can be realized.

Further, according to the Schottky gate field effect transistor according to the present invention, it is possible to realize a Schottky gate field effect transistor with extremely large transconductance.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view for explaining the present invention in detail, and Fig. 2 shows the depth of the δ-doped layer from the surface of the GaAs layer and the 2DEC.
Figure 3 is a graph showing the relationship between . A sectional view showing a GaAs MISFET according to Example I of the present invention, FIG.
A cross-sectional view showing an ISFET, FIG. 5A is an embodiment of the present invention.
FIG. 5B is a cross-sectional view taken along line BB in FIG. 5A,
FIGS. 6A to 6C are Ga shown in FIGS. 5A and 5B.
7A is a cross-sectional view showing a method for manufacturing an As'/a Schottky gate FET in the order of steps.
I- between the source and gate of Schottky gate type FET
FIG. 7B is a graph showing an example of the V characteristic, and shows an example of the I-V characteristic between the source and gate of a GaAs Schottky gate FET after forming the Schottky gate electrode and performing heat treatment. The graph shown in FIG. 8 is the GaAs Schottky gate type F shown in FIGS. 5A and 5B.
It is a graph which shows an example of the characteristic of ET. Explanation of main symbols in the drawings 11: Semi-insulating GaAs substrate, 12: N-type GaAs
layer, 13.19: δ-doped layer, 14: gate insulating film, 15: gate electrode, 16: source, 17: drain, 18: semi-insulating GaAs layer, 20: Schottky gate electrode, 22: electron beam, 23 Ni resist. Agent Patent Attorney Tadashi Sugiura Governor Dago June's Riyari Figure 1 d (A) Σ Doa Fake J Plan 2 DEG's A'l with Atsushi I in Figure 2 N31. Fig. 6 B'/a, n'h'c-/y-JiFETt) 裳p jr
5 Figure 8 C + (pA) Source-gate voltage P1 Vo (V) IO-Vo characteristics Figure 8 Figure 7 B

Claims (1)

[Scope of Claims] 1. A semiconductor device characterized in that a Dirac-delta doped layer is formed at a depth below the Debye length from the surface of a compound semiconductor layer. 2. An insulated gate field effect transistor comprising a Dirac-delta doped layer and a channel layer formed at a depth below the Debye length from the surface of a compound semiconductor layer. 3. Depth d below the Debye length from the surface of the compound semiconductor layer
1, and a second Dirac-delta doped layer formed at a depth d_2 (however, d_2>d_1) from the surface of the compound semiconductor layer. Schottky gate field effect transistor.