JPS63175471A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63175471A
JPS63175471A JP607887A JP607887A JPS63175471A JP S63175471 A JPS63175471 A JP S63175471A JP 607887 A JP607887 A JP 607887A JP 607887 A JP607887 A JP 607887A JP S63175471 A JPS63175471 A JP S63175471A
Authority
JP
Japan
Prior art keywords
layer
impurity
doped
semiconductor
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP607887A
Other languages
Japanese (ja)
Other versions
JPH0728025B2 (en
Inventor
Toshiki Makimoto
俊樹 牧本
Yoshiharu Horikoshi
佳治 堀越
Naoki Kobayashi
直樹 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP62006078A priority Critical patent/JPH0728025B2/en
Publication of JPS63175471A publication Critical patent/JPS63175471A/en
Publication of JPH0728025B2 publication Critical patent/JPH0728025B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To make non-alloy ohmic contact by supplying sufficient tunnel current by a method wherein a single atomic doped layer is formed close to an interface between a metal and a semiconductor to augment the rate of activation of impurity atom. CONSTITUTION:The first impurity doped single atomic layer 3A is formed on the part near the surface of a semiconductor layer 2 while the second impurity doped single atomic layer 3B is formed in parallel with and inside the first impurity doped layer 3A. Resultantly, the energy level of impurity atom in a single atomic doped layer existing in the part near an interface between a metal and a semiconductor exceeds the Fermi level so that the impurity atom may be sufficiently activated even in high concentration doping process to lower the potential existing close to the interface for supplying a sufficient tunnel current. Through these procedures, non-alloy ohmic contact can be made.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体装置に関し、特に合金化プロセスを経ず
に、半導体上へオーミック電極の形成を可能とする不純
物ドーピング層を有する半導体装置に関するものである
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a semiconductor device having an impurity doped layer that enables the formation of an ohmic electrode on a semiconductor without going through an alloying process. It is.

[従来の技術] 原子層ドーピングを用いて、トンネル電流を流すことに
より、低抵抗のオーミックコンタクトを形成する方法と
して、金属と半導体の界面近傍の半導体中に一層の原子
層ドーピングを行う方法がある。この方法におけるエネ
ルギバンド図を第3図に示す。この方法においては以下
に示すような2つの欠点がある。
[Prior art] As a method of forming a low-resistance ohmic contact by flowing a tunnel current using atomic layer doping, there is a method of doping a single atomic layer in a semiconductor near the interface between a metal and a semiconductor. . An energy band diagram in this method is shown in FIG. This method has two drawbacks as shown below.

■ まず、原子層ドープ層とショットキバリアにより形
成される三角ポテンシャル(第3図参照)を通過するト
ンネル電流を増やさねばならない。このためには原子層
ドープ層中の不純物が高濃度であり、かつ活性化してい
なければならない。しかし、高濃度に原子層ドーピング
を行うと、不純物準位が深くなり、不純物が十分活性化
されず。ショットキバリアの高さに相当する電圧よりも
大ぎな電圧降下は得ることができず、ノンアロイオーミ
ックコンタクトの実現は困難であった。
(2) First, it is necessary to increase the tunneling current passing through the triangular potential (see Figure 3) formed by the atomically doped layer and the Schottky barrier. For this purpose, the impurity in the atomically doped layer must be highly concentrated and activated. However, when atomic layer doping is performed at a high concentration, the impurity level becomes deep and the impurity is not activated sufficiently. It was not possible to obtain a voltage drop greater than the voltage corresponding to the height of the Schottky barrier, making it difficult to realize a non-alloy ohmic contact.

■ 次に、一層の原子層ドーピングによって、ショット
キバリアの高さに相当する電圧よりも大きな電圧降下を
引き起こすためには、ドーピング層をある程度、金属と
半導体の界面から離さねばならない。(Appl、 P
hys、 Lett、 ; 49(5)、1986.2
92)、  L、かじ、この時には三角ポテンシャルは
厚くなり電子のトンネル確率は低いものとなるため、ノ
ンアロイオーミンクコンタクトの実現は困難なものとな
る。
(2) Next, in order for a single atomic layer doping to cause a voltage drop greater than the voltage corresponding to the height of the Schottky barrier, the doped layer must be separated from the metal-semiconductor interface to some extent. (Appl, P
hys, Lett, ; 49(5), 1986.2
92), L, Kaji: At this time, the triangular potential becomes thick and the electron tunneling probability becomes low, making it difficult to realize a non-alloy ohmic contact.

金属と半導体との界面から距踵dの位置に、シートキャ
リア濃度がNcの原子層ドーピングを行フた場合の電圧
降下ΔVは ΔV=qxdxNc/ 6       (1)(qは
電子電荷、εは読電率) で与えられる。
The voltage drop ΔV when atomic layer doping with a sheet carrier concentration of Nc is performed at a distance d from the interface between the metal and the semiconductor is ΔV=qxdxNc/6 (1) (q is the electron charge, ε is the readout). Electricity) is given by

ここでは、GaAs中にStを原子層ドープした例につ
いて述べる。
Here, an example will be described in which GaAs is doped with an atomic layer of St.

原子層ドープ層にSi不純物を面密度で5 X 10”
個/cm”だけ入れた場合には、そのうちの20%だけ
がドナとなり活性化することが報告されている(Jpn
、 J、 Appl、 Phys、 ;  25゜(1
986) 、L748)、これはSi不純物の準位が深
くなっているため、不純物が十分に活性化されていない
ためである。
Si impurity is added to the atomic layer doped layer at an areal density of 5 x 10”
It has been reported that when only 20% of the cells/cm are added, only 20% of them become donors and are activated (Jpn
, J. Appl, Phys; 25° (1
986), L748), this is because the level of the Si impurity is deep and the impurity is not activated sufficiently.

第4図に従来の方法で作成した一層のドープ層を有する
半導体装置の例を示す。この従来例はn−type G
aAs基板1上にノンドープGaAs層2を200[人
]形成した後、Si不純物を面密度で5 X 10”個
/cm2入れた単原子層ドーピング層3を形成した後、
再びノンドープGaAs層2をd [人]形成し、裏面
にAuGeNiオーミックコンタクト4を蒸着し、表面
には、Au電極5を蒸着した構造となっている。
FIG. 4 shows an example of a semiconductor device having one doped layer made by a conventional method. This conventional example is n-type G
After forming 200 non-doped GaAs layers 2 on an aAs substrate 1, and forming a monoatomic layer doping layer 3 containing Si impurities at an areal density of 5 x 10'' pieces/cm2,
A non-doped GaAs layer 2 is formed again, an AuGeNi ohmic contact 4 is deposited on the back surface, and an Au electrode 5 is deposited on the front surface.

接触抵抗ρ。は第4図に示すように、膜厚方向に電圧を
かけ、電流を測定することによって測定するができる。
Contact resistance ρ. As shown in FIG. 4, this can be measured by applying a voltage in the direction of the film thickness and measuring the current.

dによる接触抵抗ρCの変化を第5図に示す。dの小さ
いときには、一層の原子層ドープ層による電圧降下がシ
ョットキバリアに相当する電圧よりも小さなためpcは
高い。また、dを大きくすると、三角ポテンシャルが厚
いためpcは高い。接触抵抗pcが最小となるのは式(
1)においてΔ■がショットキバリアの高さに相当する
d=60[入]である。しかし、この場合にも、三角ポ
テンシャルが厚いために十分なトンネル電流が流れない
ため、ρ0は高い。
FIG. 5 shows the change in contact resistance ρC depending on d. When d is small, pc is high because the voltage drop due to one atomic layer doped layer is smaller than the voltage corresponding to the Schottky barrier. Furthermore, when d is increased, the triangular potential is thicker, so pc becomes higher. The formula (
In 1), d=60 [in], which corresponds to the height of the Schottky barrier. However, even in this case, ρ0 is high because the triangular potential is thick and sufficient tunnel current does not flow.

[発明が解決しようとする問題点] 本発明は、上述した従来の欠点、すなわちドーピング層
の活性化率が低下し、トンネル電流が少なかった点を解
決し、良好なノンアロイオーミック電極層を有する半導
体装置を提供することを目的とする。
[Problems to be Solved by the Invention] The present invention solves the above-mentioned conventional drawbacks, namely, that the activation rate of the doped layer is low and the tunnel current is small, and has a good non-alloy ohmic electrode layer. The purpose is to provide semiconductor devices.

[問題点を解決するための手段] このような目的を達成するために、本発明の半導体装置
は、半導体層の表面近傍に表面と平行に第1の不純物ド
ープ単原子層が形成されており、第1の不純物ドープ単
原子層により内部に第1の層と平行に第2の不純物ドー
プ単原子層が形成されていることを特徴とする。
[Means for Solving the Problems] In order to achieve such an object, the semiconductor device of the present invention includes a first impurity-doped monoatomic layer formed near the surface of the semiconductor layer and parallel to the surface. , a second impurity-doped monoatomic layer is formed inside the first impurity-doped monoatomic layer in parallel to the first layer.

[作 用] 本発明においては単原子層ドープ層によって形成される
ポテンシャルを薄くすることによって、十分なトンネル
電流を流すために、単原子層ドープ層を金属と半導体界
面に十分に近くして不純物原子の活性化率を極めて高く
し、さらに次の単原子層ドーピング層と供にショットキ
バリアの高さに相当する電圧よりも大きな電圧降下を引
き起こさせる。金属と半導体との界面に近い高濃度のド
ーピング層の不純物準位は深いのにもかかわらず、フェ
ルミレベルよりも上にあるために、すべて活性化される
ことになる。
[Function] In the present invention, in order to flow a sufficient tunnel current by thinning the potential formed by the monoatomic layer doped layer, the monoatomic layer doped layer is placed sufficiently close to the metal-semiconductor interface to prevent impurities from forming the monoatomic layer doped layer. The activation rate of atoms is made extremely high, and together with the next monoatomic layer doping layer, a voltage drop larger than the voltage corresponding to the height of the Schottky barrier is caused. Even though the impurity levels in the highly doped layer near the interface between the metal and the semiconductor are deep, they are all activated because they are above the Fermi level.

このために十分なトンネル電流を流すことができるので
、ノンアロイオーミンクコンタクトの実現が可能である
For this purpose, a sufficient tunneling current can be passed, making it possible to realize a non-alloy ohmic contact.

[実施例] 以下に図面を参照して本発明の詳細な説明する。[Example] The present invention will be described in detail below with reference to the drawings.

第1図C本発明の実施例を示す。FIG. 1C shows an embodiment of the present invention.

第1の不純物ドープ層としてd=10[人]の位置に5
 X 10”個/crn2だけStを単原子層ドープし
た第1の層3Aを形成し、ざらにd=60CAlの位置
に、第2の不純物ドープ層3Bとして活性化率が100
%である5 X 10”個/cI112のSi単原子層
ドーピングを行った構造を作製した。他の構造は第4図
に示した従来例と同じである。
5 at the position of d=10 [people] as the first impurity doped layer.
A first layer 3A doped with a monoatomic layer of St by X 10'' pieces/crn2 is formed, and a second impurity doped layer 3B with an activation rate of 100 is formed at a position roughly at d=60CAl.
A structure was fabricated in which Si monoatomic layer doping was performed at a concentration of 5 x 10'' atoms/cI112.

第1および第2の不純物ドープ層はそれぞれ複数の原子
層からなると、原子層間での不純物の相互作用によって
電子の放出が抑制される。従って、両不純物ドープ層は
それぞれ単原子層であることが必要である。高濃度の不
純物をドープした単原子層を形成するには、MOCVD
法を改良した流量変調MOGVD法が有効である。
When each of the first and second impurity-doped layers is composed of a plurality of atomic layers, electron emission is suppressed by interaction of impurities between the atomic layers. Therefore, both impurity-doped layers must each be a monoatomic layer. To form a monoatomic layer doped with a high concentration of impurities, MOCVD
The flow modulation MOGVD method, which is an improved method, is effective.

このとき、第1の不純物ドープ層の活性化率を従来例と
同様に20%とすると、第1層による電圧降下はΔV、
 =O,14[V] となり、第2の不純物ドープ層に
よる電圧降下は、ΔV2=0,42[V] であるから
、Δv、−1−AV2<φB(0,9V)となり、低い
接触抵抗ρ。は得られない。しかし、実際に測定を行な
うとρ。= I X 10−’[Ω・cm2]程度の極
めて低い接触抵抗が得られた。
At this time, if the activation rate of the first impurity doped layer is 20% as in the conventional example, the voltage drop due to the first layer is ΔV,
=O, 14[V], and the voltage drop due to the second impurity doped layer is ΔV2=0,42[V], so Δv,-1-AV2<φB(0,9V), resulting in low contact resistance. ρ. cannot be obtained. However, when actually performing measurements, ρ. An extremely low contact resistance of the order of = I x 10-' [Ω·cm2] was obtained.

第2図に本発明における2層の単原子層ドープを行った
構造のエネルギーバンドを示す。
FIG. 2 shows the energy band of a structure in which two monoatomic layers are doped according to the present invention.

本発明においてはフェルミレベルよりも上の不純物準位
から電子が放出されることにより、第1層の活性化率が
実質1高(なったために低い接触抵抗が得られる。この
ように第1層の位置における伝導帯とフェルミレベルと
の差を比較的大きくとることにより、不純物の活性化率
を上げることができる。第2図と第3図とを比較すれば
明らかなように金属と半導体との界面付近の電子に対す
るポテンシャルは、従来の三角ポテンシャルに比べ薄く
なり、十分なトンネル電流を流すことができるために、
ノンアロイオーミックコンタクトの実現が可能である。
In the present invention, since electrons are emitted from the impurity level above the Fermi level, the activation rate of the first layer is substantially increased by 1, resulting in a low contact resistance. The activation rate of impurities can be increased by making the difference between the conduction band and the Fermi level relatively large at the position of The potential for electrons near the interface is thinner than the conventional triangular potential, and a sufficient tunneling current can flow.
It is possible to realize a non-alloy ohmic contact.

六久ムー 笛1聞枳)γに第7層のド−ピング層をそれ
ぞれ5 X 1G”個/ cod” 、  5 x 1
0′2個/ c m 2とし、第1層および第2層の半
導体表面からの位置を変え、抵抗率の変化を調べた。そ
の結果を第1表に示す。第1層の位置が界面から 10
0人をこえて離れている場合および第2層の位置が50
0人をこえて離れている場合には10−6Ω・cm2台
の低い抵抗率を得ることはできなかった。従って10−
8Ω・cm2台の低い抵抗率を得るためには、第1層お
よび第2層の位置は、半導体の表面から、それぞれ10
0人、500人以内が望ましい。
Rokukyu Mu Fue 1) Add the 7th doping layer to γ, 5 x 1 G"/cod", 5 x 1
0'2 pieces/cm2, and the positions of the first layer and the second layer from the semiconductor surface were changed to examine changes in resistivity. The results are shown in Table 1. The position of the first layer is from the interface 10
If there are more than 0 people apart and the second layer position is 50
If there were more than 0 people apart, it was not possible to obtain a resistivity as low as 10-6 Ω·cm2. Therefore 10-
In order to obtain a low resistivity on the order of 8 Ω cm2, the positions of the first and second layers should be 100 cm from the surface of the semiconductor.
0 people, preferably 500 or less.

表   1 [効 果] 以上説明したように、本発明によれば金属と半導体との
界面付近に存在する単原子層ドーピング層内の不純物原
子のエネルギ準位が、フェルミレベルよりも上であり、
高濃度にドーピングを行なっても不純物原子は十分活性
化できる。このため、界面付近に存在するポテンシャル
は、非常に薄くなり、十分なトンネル電流を流すことが
できるため、ノンアロイオーミックコンタクトの実現が
可能となった。
Table 1 [Effects] As explained above, according to the present invention, the energy level of the impurity atoms in the monoatomic layer doped layer existing near the interface between the metal and the semiconductor is higher than the Fermi level,
Even if doping is performed at a high concentration, impurity atoms can be sufficiently activated. For this reason, the potential existing near the interface becomes extremely thin and a sufficient tunneling current can flow, making it possible to realize a non-alloy ohmic contact.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例を示す断面図、第2図は本発明
におけるエネルギーバンド図、 第3図は従来の単一のドープ層を有する半導体装置にお
けるエネルギーバンド図、 第4図は従来の半導体装置の一例の断面図、第5図は従
来の装置における接触抵抗を示す図である。 1−−・n −GaAs基板、 2・・・ノンドープGaAs層、 3A・・・第1の不純物ドープ単原子層、3B・・・第
2の不純物ドープ単原子層。
FIG. 1 is a cross-sectional view showing an embodiment of the present invention, FIG. 2 is an energy band diagram in the present invention, FIG. 3 is an energy band diagram in a conventional semiconductor device having a single doped layer, and FIG. 4 is a conventional FIG. 5 is a cross-sectional view of an example of a semiconductor device, and FIG. 5 is a diagram showing contact resistance in a conventional device. 1--.n-GaAs substrate, 2... Non-doped GaAs layer, 3A... First impurity-doped monoatomic layer, 3B... Second impurity-doped monoatomic layer.

Claims (1)

【特許請求の範囲】 1)半導体層の表面近傍に該表面と平行に第1の不純物
ドープ単原子層が形成されており、該第1の不純物ドー
プ単原子層により内部に該第1の層と平行に第2の不純
物ドープ単原子層が形成されていることを特徴とする半
導体装置。 2)前記第1の不純物ドープ単原子層の前記表面からの
距離が100Å以内であり、かつ前記第2の不純物ドー
プ単原子層の前記表面からの距離が500Å以内である
ことを特徴とする特許請求の範囲第1項記載の半導体装
置。 3)前記第1の不純物層のドーピング量は、金属と前記
半導体を接触させた際に形成されるショットキバリアの
高さに相当する電圧よりも小さな電圧降下を引き起こす
量であることを特徴とする特許請求の範囲第1項または
第2項に記載の半導体装置。 4)前記第1および第2の不純物層によって引き起こさ
れる電圧降下の量が前記ショットキバリアの高さに相当
する電圧より大きいことを特徴とする特許請求の範囲第
1項記載の半導体装置。
[Scope of Claims] 1) A first impurity-doped monoatomic layer is formed near the surface of the semiconductor layer in parallel with the surface, and the first impurity-doped monoatomic layer causes the first layer to be formed inside the semiconductor layer. A semiconductor device characterized in that a second impurity-doped monoatomic layer is formed in parallel with the . 2) A patent characterized in that the distance from the surface of the first impurity-doped monoatomic layer is within 100 Å, and the distance from the surface of the second impurity-doped monoatomic layer is within 500 Å. A semiconductor device according to claim 1. 3) The doping amount of the first impurity layer is an amount that causes a voltage drop smaller than a voltage corresponding to the height of a Schottky barrier formed when a metal and the semiconductor are brought into contact. A semiconductor device according to claim 1 or 2. 4) The semiconductor device according to claim 1, wherein the amount of voltage drop caused by the first and second impurity layers is larger than the voltage corresponding to the height of the Schottky barrier.
JP62006078A 1987-01-16 1987-01-16 Semiconductor device Expired - Fee Related JPH0728025B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62006078A JPH0728025B2 (en) 1987-01-16 1987-01-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62006078A JPH0728025B2 (en) 1987-01-16 1987-01-16 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS63175471A true JPS63175471A (en) 1988-07-19
JPH0728025B2 JPH0728025B2 (en) 1995-03-29

Family

ID=11628530

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62006078A Expired - Fee Related JPH0728025B2 (en) 1987-01-16 1987-01-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0728025B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0271563A (en) * 1988-09-06 1990-03-12 Sony Corp Semiconductor device, insulated gate type field effect transistor and schottky gate type field effect transistor
JP2008098674A (en) * 2003-06-10 2008-04-24 Matsushita Electric Ind Co Ltd Semiconductor device
US10833199B2 (en) 2016-11-18 2020-11-10 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height
US10872964B2 (en) 2016-06-17 2020-12-22 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US10879366B2 (en) 2011-11-23 2020-12-29 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US10937880B2 (en) 2002-08-12 2021-03-02 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11043571B2 (en) 2002-08-12 2021-06-22 Acorn Semi, Llc Insulated gate field effect transistor having passivated schottky barriers to the channel

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59175774A (en) * 1984-02-01 1984-10-04 Hitachi Ltd Semiconductor device
JPS63173A (en) * 1986-06-19 1988-01-05 Fujitsu Ltd High-speed semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59175774A (en) * 1984-02-01 1984-10-04 Hitachi Ltd Semiconductor device
JPS63173A (en) * 1986-06-19 1988-01-05 Fujitsu Ltd High-speed semiconductor device

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0271563A (en) * 1988-09-06 1990-03-12 Sony Corp Semiconductor device, insulated gate type field effect transistor and schottky gate type field effect transistor
US11056569B2 (en) 2002-08-12 2021-07-06 Acorn Semi, Llc Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11043571B2 (en) 2002-08-12 2021-06-22 Acorn Semi, Llc Insulated gate field effect transistor having passivated schottky barriers to the channel
US11355613B2 (en) 2002-08-12 2022-06-07 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11018237B2 (en) 2002-08-12 2021-05-25 Acorn Semi, Llc Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US10937880B2 (en) 2002-08-12 2021-03-02 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US10950707B2 (en) 2002-08-12 2021-03-16 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
JP2008098674A (en) * 2003-06-10 2008-04-24 Matsushita Electric Ind Co Ltd Semiconductor device
US10879366B2 (en) 2011-11-23 2020-12-29 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US11610974B2 (en) 2011-11-23 2023-03-21 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US11804533B2 (en) 2011-11-23 2023-10-31 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US10872964B2 (en) 2016-06-17 2020-12-22 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US11843040B2 (en) 2016-06-17 2023-12-12 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US10833199B2 (en) 2016-11-18 2020-11-10 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height
US11462643B2 (en) 2016-11-18 2022-10-04 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height

Also Published As

Publication number Publication date
JPH0728025B2 (en) 1995-03-29

Similar Documents

Publication Publication Date Title
Hensel et al. Transistor action in Si/CoSi2/Si heterostructures
Mönch Barrier heights of real Schottky contacts explained by metal-induced gap states and lateral inhomogeneities
Crowell et al. Surface‐state and interface effects in Schottky barriers at n‐type silicon surfaces
US20200136024A1 (en) Apparatus for spin injection enhancement and method of making the same
JPS631064A (en) Field effect transistor and manufacture of the same
CN103426922A (en) Semiconductor device and manufacturing method of the same
Stall et al. A study of Ge/GaAs interfaces grown by molecular beam epitaxy
CN108028285A (en) Tunnel barrier schottky
CN104170058A (en) Improving metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
JPS63175471A (en) Semiconductor device
US10985311B2 (en) Semiconductor element, magnetoresistance effect element, magnetic sensor and spin transistor
Hasegawa Inteface-controlled Schottky barriers on InP and related materials
US20080157062A1 (en) Spin transistor
Dickie et al. Metal-organic-silicon nanoscale contacts
Ikeda et al. Tunneling emission from valence band of Si-metal–oxide–semiconductor electron tunneling cathode
JPH0687509B2 (en) Heterojunction magnetic sensor
JPH03222376A (en) Diamond semiconductor light emitting element
TW200905874A (en) Heterojunction bipolar transistor
JPS623591B2 (en)
JP4162888B2 (en) Spin valve transistor
JPH01125985A (en) Semiconductor device
JP2009200351A (en) Semiconductor spin device and spin fet
Furlan et al. Modeling tunneling-assisted generation-recombination rate in space-charge region of PN A-SI: H junction
JPS62245681A (en) Negative differential resistance field-effect tran-sistor
JP2722849B2 (en) Resonant tunnel field effect transistor

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees