JP2009200351A - Semiconductor spin device and spin fet - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor spin device capable of improving an MR ratio and a spin FET capable of improving an MR ratio especially between a source and a drain. <P>SOLUTION: Although a value of source-side interface resistance of a spin MOSFET is essentially different from a value of drain-side interface resistance, these values are made to approximately coincide with each other by adjusting the thickness of a tunnel barrier layer in the interface. Consequently, electrical symmetry in the spin MOSFET can be secured, and when a condition for the case is analyzed, an improved MR ratio is found out. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor spin device and a spin FET using the same.

  Semiconductor spin electronics using spin technology and semiconductor technology is attracting attention as a key technology for next-generation electronic devices. In a semiconductor spin device, carriers having a specific spin are injected into a semiconductor and the carriers are conducted in the semiconductor.

  For example, in a spin MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a spin is injected into a semiconductor from a source electrode, and this spin is taken out from a drain electrode. Spin MOSFETs are described in, for example, Patent Document 1 and Non-Patent Document 1 by Mr. Sugawara and Mr. Tanaka.

  The structure of the spin MOSFET described in Patent Document 1 and Non-Patent Document 1 is based on a conventional Schottky MOSFET, uses a magnetic material for the source electrode and the drain electrode, and spin-polarized current from the magnetic material to the Si channel. Is injected. A normal MOSFET controls a current by a gate voltage, but a spin MOSFET newly adds a control method such as an external magnetic field in addition to a gate voltage. That is, the output current due to the magnetoresistive effect varies depending on the relative angle of the magnetization directions of the source electrode and the drain electrode. Usually, the direction of magnetization of the source electrode is fixed, and the magnetization is switched between parallel / antiparallel with the drain electrode as a free layer.

  When a constant spin current is supplied from the source electrode into the semiconductor, the control width increases as the spin polarizability of the electrode increases. When a half metal having a polarizability of 100% is used for the source electrode and the drain electrode, when these magnetization directions are antiparallel, the resistance becomes infinite and no current flows at a small voltage. In addition, the current flows only when the source-drain voltage is equal to or greater than the half-metal band gap. As described above, the current is switched depending on the magnetization direction, which is a feature of the spin MOSFET.

  If the magnetization direction of the drain electrode made of a ferromagnetic material is associated with a digital value, the amount of carriers extracted from the drain electrode changes depending on the magnetization direction, so this can be controlled by controlling the magnetization direction from the outside. Can also be used for MRAM (Magnetoretic Random Access Memory).

  Here, as one of the most important issues in semiconductor spintronics, there is a problem of improving the efficiency of spin injection into the semiconductor. Generally, metal and semiconductor differ in electrical resistivity by 4 to 6 digits. It is known that the spin current is reflected at the junction interface of materials having different electrical resistivity. In other words, considering the application of spin-polarized current from the metal magnetic material to the semiconductor, there is a problem that many spins are difficult to be injected into the semiconductor due to the difference in electrical resistivity in the vicinity of the interface.

  The polarizability of the spin-polarized current flowing in the ferromagnetic body attenuates as soon as it passes through the junction interface with a substance having a large resistance. This is a problem referred to as “conductivity mismatch”. Non-patent document 2 by Schmidt et al. Discloses a spin injection model to a semiconductor based on electrochemical potential calculation.

  In order to avoid such a conductivity mismatch, a method of inserting a tunnel insulating film at the interface between the ferromagnetic material and the semiconductor has been proposed. For example, Non-Patent Document 5 discloses a semiconductor spin device that achieves high spin injection efficiency by using such a technique. In the evaluation of spin injection, the ellipticity of light emission emitted by combining electrons and holes during carrier injection is measured. For the measurement of luminescence, GaAs which is a direct transition type semiconductor material is mainly used. This is because indirect transition type single crystal Si does not emit light.

  In the optical measurement, the operation of actually taking out the spin-polarized current from the semiconductor is unnecessary. Non-Patent Document 4 by Fert et al. Pointed out that an optimum tunneling resistance exists for the magnetoresistive effect when the detection (= extraction) of the spin current is considered in addition to the injection of the spin-polarized current. ing. Non-Patent Document 4 shows that a large MR ratio can be obtained when the interface resistance of the tunnel film coincides with the resistance per semiconductor spin diffusion length (spin resistance). According to Non-Patent Document 4, when the magnitude of the interface resistance is deviated from the matched value, in detail, when the interface resistance value is increased by two orders of magnitude or two orders of magnitude compared to the matched value, the MR ratio is It is shown to be about an order of magnitude smaller.

  Non-Patent Document 3 was disclosed by Min et al.'S team at Twente University in the Netherlands. According to the same document, the key technology for realizing a semiconductor spin device is in the matching condition disclosed in Non-Patent Document 4. From the point of view, we are examining whether it is actually consistent. According to Non-Patent Document 3, a gadolinium (Gd) film having a small work function is inserted between the insulating film and the magnetic electrode film, thereby reducing the height of the Schottky barrier and realizing conductivity matching. Is disclosed.

  When a metal and a semiconductor are bonded, the interface forms a Schottky contact. In the field of semiconductors, silicide and the like that can provide a stable Schottky surface have been put into practical use. Unfortunately, these silicides are non-magnetic materials, and the practical application of spin MOSFETs depends on finding magnetic materials that can change them. The ability to create a Schottky junction is welcome for the operation of the spin MOSFET because it eliminates the conductive mismatch.

  The basic idea of a spin MOSFET is to solve a conductivity mismatch by using a Schottky barrier as a tunnel barrier. However, as in Non-Patent Document 3 described above, an insulating film (tunnel film) is used together. There is also. As described above, in the conventional spin MOSFET, the source electrode and the semiconductor are electrically connected by the tunnel current flowing through the Schottky barrier.

International Publication WO2004 / 0779827 Pamphlet Satoshi Sugahara et al. "A Spin metal-oxide-semiconductor field-effect transistor using half-metallic-ferromagnetic contacts for the source and drain.", Appl. Phys. Letters, March 29, 2000, Vol. 84, no. 13, p. 2307 to 2309 G. Schmidt et al. , "Fundamental obstral for electrical spin injection from a ferromagnetic metal into a diffuse semiconductor, Phys. Rev. B, Aug. 15 p. B. C. Min et al. , “Tunable Spin-tunnel contacts to silicon using low-work-function ferromagnets”, Nature materials, October 2006, Vol. 5, p. 817-822 A. Fert et al. , "Conditions for effective spin injection from a ferromagnetic metal into a semiconductor", Phys. Rev. B, October 19, 2001, Vol. 64, p. 184420-1 to 184420-9 X. Jiang et al. "Highly efficient room-temperature tunnel spin injector using CoFe / MgO (001)", IBM J. MoI. Res. and Dev. , January, 2006, Vol. 50, no. 1, p. 111-120

  However, in a semiconductor spin device, particularly in a spin MOSFET, how to increase the MR ratio has been technically unknown.

  The present invention has been made in view of such a problem, and a semiconductor spin device capable of increasing the MR ratio, and in particular, a spin capable of improving the MR ratio between the source and the drain. An object is to provide an FET.

In order to solve the above problems, a semiconductor spin device according to the present invention includes a first electrode made of a fixed layer, a second electrode made of a free layer, and a semiconductor region provided with the first and second electrodes. And the thickness d _S of the first tunnel barrier layer interposed between the first electrode and the semiconductor region and the thickness d _D of the second tunnel barrier layer interposed between the second electrode and the semiconductor region are as follows: The relational expression: d _S <d _D is satisfied.

  Although the interface resistance of the first electrode (source side) and the interface resistance of the second electrode (drain side) in the semiconductor spin device are inherently different, the thickness of the tunnel barrier layer at these interfaces should be set as described above. Thus, these can be substantially matched. As a result, electrical symmetry in the semiconductor spin device is ensured, and it was found that the MR ratio becomes high when the conditions in this case are analyzed.

More preferably, the first tunnel barrier layer has a first insulating layer, the second tunnel barrier layer has a second insulating layer, the thickness d ₁ of the first insulating layer, and the second insulating layer The layer thickness d ₂ preferably satisfies the following relational expression: d ₁ <d ₂ . In this case, the thickness is determined by the thicknesses d ₁ and d ₂ of the first and second insulating layers, and the thickness d _D on the drain side is relatively larger than the thickness d _S on the source side. The electrical symmetry is ensured, and the MR ratio is increased.

The first tunnel barrier layer has a first semiconductor layer having an energy band gap wider than that of the semiconductor region, and the second tunnel barrier layer has a second semiconductor layer having an energy band gap wider than that of the semiconductor region. May be. In this case, the thickness is determined by the thicknesses d ₁ and d ₂ of the first and second semiconductor layers, and the thickness d _D on the drain side is relatively thicker than the thickness d _S on the source side. The electrical symmetry is ensured, and the MR ratio is increased.

  As the semiconductor spin device, a magnetic head element such as a TMR element, a spin MOSFET, and a spin junction FET can be considered as long as spin conduction is performed.

  The spin FET according to the present invention is a spin FET having the semiconductor spin device described above, wherein the first electrode is a source electrode, the second electrode is a drain electrode, and the potential of the semiconductor region between the source electrode and the drain electrode is controlled. The gate electrode is provided.

  The spin FET in this case can increase the MR ratio between the source and the drain, and when used in an MRAM or the like, it can improve the data read accuracy.

  The semiconductor spin device according to the present invention, particularly the spin FET, can increase the MR ratio.

  Hereinafter, a spin MOSFET as a semiconductor spin device according to an embodiment will be described. Note that the same reference numerals are used for the same elements, and redundant description is omitted. Prior to the description of the embodiment, the basic configuration of the spin MOSFET will be described.

  FIG. 1 is a plan view of a basic spin MOSFET, and FIG. 2 is a cross-sectional view taken along the line II-II of the spin MOSFET shown in FIG.

  The spin MOSFET includes a semiconductor substrate (semiconductor region) 1A, a source electrode (first electrode) 2S provided on the semiconductor substrate 1A, a drain electrode (second electrode) 2D, and a source electrode 2S of the semiconductor substrate 1A. An insulating film 3 provided on a region between the drain electrode 2D and a gate electrode 4 provided on the insulating film 3 are provided. The surface of the semiconductor substrate 1A is etched at portions where the source electrode 2S and the drain electrode 2D are provided, and a channel formed in the semiconductor substrate 1A is positioned between the side surfaces of the source electrode 2S and the drain electrode 2D.

  The source electrode 2S and the semiconductor substrate 1A are in contact with each other, and a depletion layer spreads in the semiconductor substrate 1A from these contact interfaces. The source electrode 2S made of a ferromagnetic metal and the semiconductor substrate 1A are in Schottky contact, and the region 1S in the semiconductor substrate 1A that forms this Schottky barrier extends from the interface between the source electrode 2S and the semiconductor substrate 1A into the substrate. ing.

  Similarly, the drain electrode 2D and the semiconductor substrate 1A are in contact with each other, and a depletion layer spreads in the semiconductor substrate 1A from these contact interfaces. The drain electrode 2D made of a ferromagnetic metal and the semiconductor substrate 1A are in Schottky contact, and the region 1D in the semiconductor substrate 1A that forms this Schottky barrier extends from the interface between the drain electrode 2D and the semiconductor substrate 1A into the substrate. ing.

  Impurities serving as carriers are added to the contact interface regions 1S and 1D, respectively. The impurity to be added is shallow, and so-called delta doping is performed. As an impurity addition method, an ion implantation method is preferable, but a diffusion method may be used. Impurities may be added by forming an insulating film 3 on the semiconductor substrate 1A and then ion-implanting impurities from the substrate surface using this as a mask or by thermal diffusion.

  The source electrode 2S is composed of a fixed layer in which the magnetization direction DMS is fixed, and the drain electrode 2D is a free layer in which the magnetization direction DMD is reversed by an external magnetic field or spin injection exceeding a threshold value. When the condition for the polarization spin to flow between the source electrode 2S and the drain electrode 2D is satisfied, when the magnetization direction DMS of the source electrode 2S matches the magnetization direction DMD of the drain electrode 2D, the source The current flowing between the electrode 2S and the drain electrode 2D is large, and the magnetoresistance between the source electrode / drain electrode is small. In addition, when the condition where the polarized spin flows between the source electrode 2S and the drain electrode 2D is satisfied, the magnetization direction DMS of the source electrode 2S and the inverted magnetization direction DMD ′ of the drain electrode 2D are opposite to each other. In this case, the current flowing between the source electrode 2S and the drain electrode 2D is small, and the magnetoresistance between the source electrode and the drain electrode is large.

  Now consider the structure between each electrode and the semiconductor. First, consider the case where no delta doping of impurities is performed.

  The vicinity of the interface of the source electrode 2S of the spin MOSFET and the vicinity of the interface of the drain electrode 2D constitute a Schottky diode. If electrons are used as carriers, a reverse voltage is applied to the diode near the source electrode. A forward voltage is applied to the diode near the drain electrode. When the source / drain voltage Vds is small, a Schottky barrier with a thickness sufficient to cause a tunnel effect remains on the drain electrode side. However, when the source / drain voltage Vds is higher than the height of the Schottky barrier, the barrier on the drain side In the vicinity of the drain electrode interface, carrier conduction due to diffusion becomes dominant near the drain electrode interface.

  That is, when no impurity is added, the electrical configuration near the source electrode interface and the drain electrode interface is asymmetric. More specifically, the interface resistance on the source electrode 2S side is high, and the interface resistance on the drain side is low. Thus, in the spin MOSFET, the resistances on the carrier injection side and the carrier extraction side are essentially different.

Here, if a tunnel resistance is added at least to the drain side, the symmetry of the electrical structure in the vicinity of the source electrode and the vicinity of the drain electrode can be enhanced. The present invention has found that the MR ratio can be remarkably improved by increasing the originally different electrical symmetry by adding a tunnel resistance. That is, the spin injection efficiency in the semiconductor spin device can be improved, the spin extraction efficiency can be improved, and the MR ratio can be increased. This is because the conductivity matching (resistance matching) condition at both interfaces is satisfied, and a large magnetoresistance can be obtained at this time.

  FIG. 3A is a diagram of an FET in which each element is schematically shown, and FIG. 3B is an energy band diagram showing energy at each position of the element shown in FIG. Ec is the lower end of the conduction band, and Ev is the upper end of the valence band.

  Carriers injected from the source electrode 2S through the semiconductor region 1S constituting the Schottky barrier (potential barrier) travel in the semiconductor substrate 1A according to the internal electric field while maintaining the spin state at the time of injection, It flows into the drain electrode 2D through the semiconductor region 1D constituting the Schottky barrier (potential barrier). The potential in the semiconductor substrate 1A depends on the potential applied to the gate electrode, and in the state where the source / drain voltage Vds is applied, the magnetization directions of the source electrode 2S and the drain electrode 2D are matched, and When a gate potential having a high potential is applied to the gate electrode 4 to such a thickness that the spin can pass through the semiconductor regions 1S and 1D, carriers flow from the source electrode 2S to the drain electrode 2D. When the magnetization directions of the source electrode 2S and the drain electrode 2D do not match, carriers do not flow from the source electrode 2S to the drain electrode 2D. Further, when a high potential gate potential is not applied to the gate electrode 4, carriers do not flow.

  When the magnetization direction of the drain electrode 2D is associated with “0” and “1”, a digital value is stored according to the presence or absence of carriers output from the drain electrode 2D, and functions as an MRAM. The direction of magnetization of the drain electrode 2D is larger than a prescribed amount in the drain electrode 2D by applying a magnetic field from the outside or using a specific ferromagnetic electrode (not shown) provided at an appropriate position of the semiconductor substrate 1A as a spin valve. If an amount of spins is injected, the magnetization direction of the drain electrode 2D changes so as to be aligned with the injected spin direction. That is, the direction of magnetization of the drain electrode 2D can be switched by switching the direction of spin injection for external magnetic field or magnetization reversal control.

  Next, an embodiment in which a relatively large tunnel resistance is added to the drain side as described above will be described. In the above, in order to increase the MR ratio by increasing the spin injection efficiency from the source electrode 2S and efficiently extracting the spin from the drain electrode 2D, the thickness of the tunnel barrier is adjusted to satisfy the conductivity matching condition. It was mentioned that it was preferable. Theoretically, it is preferable that perfect conductivity matching is performed, but a certain effect can be obtained even if there is a slight deviation.

  FIG. 4 is a plan view of the spin MOSFET according to the first embodiment. FIG. 5 is a cross-sectional view taken along the line VV of the spin MOSFET shown in FIG. In this spin MOSFET, a potential barrier layer (tunnel barrier layer) 1S ′ is interposed between the semiconductor substrate 1A and the source electrode 2S, and a potential barrier layer (tunnel barrier layer) 1D is interposed between the semiconductor substrate 1A and the drain electrode 2D. 1-3 is different from FIGS. 1 to 3 in that the other configuration is the same.

  FIG. 6A is a diagram of an FET schematically showing each element of the FET of the first embodiment, and FIG. 6B is an energy showing energy at each position of the element shown in FIG. It is a band diagram.

The polarized spin injected from the source electrode 2S tunnels through the potential barrier layer 1S including the potential barrier layer 1S ′ and flows into the semiconductor substrate 1A. The polarized spin is taken out from the drain electrode 2D through the potential barrier 1D including the potential barrier layer 1D ′. The thickness d ₂ of the drain-side potential barrier layer 1D ′ is set larger than the thickness of the source-side potential barrier layer 1S ′ (d ₁ <d ₂ ).

  The potential barrier layer 1S ′ is made of a semiconductor layer or an insulating layer having an energy band gap wider than that of the semiconductor substrate 1A, and the potential barrier layer 1D ′ is also made of a semiconductor layer or insulating layer having an energy band gap wider than that of the semiconductor substrate 1A. Become.

Further, the electron tunneling is regulated by the thickness of the potential barrier layers 1S ′ and 1D ′, and the thickness d _D of the potential barrier layer 1D is set larger than the thickness d _S of the potential barrier layer 1S ( d _S <d _D ). These potential barrier layers are all tunnel barrier layers having a thickness that causes a tunnel effect. In this example, the potential barrier layers 1S ′ and 1D ′ are made of the same material.

  When the potential barrier layers 1S ′ and 1D ′ are made of an insulator, the channel length (d) is obtained by removing the thickness of the potential barrier layers 1S ′ and 1D ′ from the shortest distance between the source electrode 2S and the drain electrode 2D. The distance is specified. The channel length (d) is defined by the shortest distance between the source electrode 2S and the drain electrode 2D when the potential barrier layers 1S 'and 1D' are made of a semiconductor material different from that of the semiconductor substrate 1A.

  In the description of FIG. 3, the potential barrier through which spin passes is a Schottky barrier due to metal / semiconductor contact. . Except for this point, the operation of the FET of the first embodiment is the same as that shown in FIG. 3, and impurities are added as described above, but even if these impurities are not added, If the potential barrier layer is thicker on the drain side, the MR ratio can be increased as described above.

  Next, the conductivity matching condition will be described in detail.

7, MR ratio obtained by the normalized interface resistance Q _C3 between the normalized interface resistance Q _C1, the drain electrode 2D and the semiconductor substrate 1A between the source electrode 2S and the semiconductor substrate 1A It is a graph which shows distribution of. The conductivity matching condition is Q _C1 = Q _C3 , and when both values are 1, the MR ratio is maximized. The spin MOSFET of this embodiment always operates near the matching condition that allows the maximum value of the MR ratio to be obtained. The source / drain voltage is assumed to be 1V.

As described above, when no impurities are added, the electrical configuration of the source electrode interface and the drain electrode interface is asymmetric. Therefore, in order to improve this symmetry and achieve conductivity matching, the tunnel on the drain side is used. The thickness d _D (d ₂ ) of the barrier layer 1D is made larger than the thickness d _S (d ₁ ) of the source side 1S.

N _S (/ cm ³ ) represents the impurity concentration of the surface of the semiconductor substrate 1A at the position where the source electrode 2S is provided, D _S (nm) represents the diffusion depth of this impurity, and N _D ( / Cm ³ ) indicates the impurity concentration on the surface of the semiconductor substrate 1A at the position where the drain electrode 2D is provided, and D _D (nm) indicates the diffusion depth of this impurity.

A data group (circle) in the region RG1 in FIG. 7 shows a combination of interface resistances Q _C1 and Q _C3 that can obtain an MR ratio of 10% or more of the maximum value of the MR ratio. The data in the region RG1 is when the added impurity concentration and depth are as follows.
1 × 10 ¹⁶ (/ cm ³ ) ≦ N _S (/ cm ³ ) ≦ 1 × 10 ²⁰ (/ cm ³ )
^{1 × 10 16 (/ cm 3} ) ≦ N D (/ cm 3) ≦ 1 × 10 20 (/ cm 3)
1 (nm) ≦ D _S (nm) ≦ 100 (nm)
1 (nm) ≦ D _D (nm) ≦ 100 (nm)
3 (nm) ≦ d _S (nm) ≦ 10 (nm)
3 (nm) ≦ d _D (nm) ≦ 10 (nm)
0.5 (nm) ≦ d ₁ (nm) ≦ 3 (nm)
0.5 (nm) ≦ d ₂ (nm) ≦ 5 (nm)
The resistance R _C1 when passing through the above-described region 1S and the resistance R _C3 when passing through the region 1D are: resistance R _C1 <resistance R _C3 , and each suitable range is 1 kΩ to 30 kΩ.

Each impurity concentration more preferably satisfies the following relationship in order to increase the MR ratio.
1 × 10 ¹⁷ (/ cm ³ ) ≦ N _S (/ cm ³ ) ≦ 1 × 10 ²⁰ (/ cm ³ )
^{1 × 10 17 (/ cm 3} ) ≦ N D (/ cm 3) ≦ 1 × 10 20 (/ cm 3)

A data group (triangle mark) in the region RG2 of FIG. 7 shows a combination of interface resistances Q _C1 and Q _C3 that can obtain an MR ratio of 1% or more of the maximum value of the MR ratio. Data in the region RG2 is obtained when the added impurity concentration and depth are as follows.
1 × 10 ¹⁵ (/ cm ³ ) ≦ N _S (/ cm ³ ) ≦ 1 × 10 ²¹ (/ cm ³ )
^{1 × 10 15 (/ cm 3} ) ≦ N D (/ cm 3) ≦ 1 × 10 21 (/ cm 3)
1 (nm) ≦ D _S (nm) ≦ 1000 (nm)
1 (nm) ≦ D _D (nm) ≦ 1000 (nm)
1 (nm) ≦ d _S (nm) ≦ 100 (nm)
1 (nm) ≦ d _D (nm) ≦ 100 (nm)
0.3 (nm) ≦ d ₁ (nm) ≦ 10 (nm)
0.3 (nm) ≦ d ₂ (nm) ≦ 20 (nm)
In this case as well, the resistance R _C1 when passing through the above-described region 1S and the resistance R _C3 when passing through the region 1D are resistance R _C1 <resistance R _C3 , and each suitable range is 100 to 100 100 kΩ.

_{Incidentally,} a straight line of Q C3 _{= Q C1,} the straight line of the MR ratio of logQ C3 = -logQ _C1 becomes relatively higher than ambient.

Here, the source electrode 2S and the drain electrode 2D are made of a ferromagnetic metal such as CoFe, the channel length (d) is 3 μm, and the resistivity of the semiconductor substrate 1A is 1 Ω · cm. Impurity is added by δ-doped ion implantation and activated. By changing the ion implantation amount from 1 × 10 ¹⁶ / cm ³ to 1 × 10 ²⁰ / cm ³ , the interface resistances Q _C1 and Q _C3 can be arbitrarily changed from 10 MΩ to 1Ω.

If Q _C3 = β × Q _C1 , the size of β indicates the asymmetry of the interface resistance. According to the ion implantation, the asymmetry coefficient β varies from 10 ⁻⁶ to 10 ⁶ . This is because the height of the Schottky barrier, which is the interface resistance, and the thickness of the depletion layer vary greatly with the amount of ion implantation. Similarly to the case of ion implantation, β can be adjusted by the thickness of the tunnel barrier layer.

  The impurity-added region includes (a) an internal region when the potential barrier layers 1S ′ and 1D ′ are semiconductors, and (b) a semiconductor from the interface between the potential barrier layers 1S ′ and 1D ′ and the semiconductor substrate 1A. It is a shallow region toward the deep part of the substrate 1A, or (c) both regions (a) and (b).

  From the interface between the semiconductor substrate and the potential barrier layers 1S 'and 1D', regions 1S and 1D forming a potential barrier between the semiconductor substrate interface and the semiconductor substrate 1A extend.

In this example, it is assumed that (b) an impurity is added immediately below the potential barrier layer. In the case of (a) and (c), N _S, N _D is assumed to be given by the average value of the concentration of each of the impurity doped region. Further, ZnO was adopted as the potential barrier layers 1S ′ and 1D ′, and Heusler alloy (Co ₂ MnSi: thickness 20 nm) was adopted as the source electrode 2S and the drain electrode 2D.

The thickness of the potential barrier layers 1S ′ and 1D ′ can be varied from 0.2 nm to 20 nm, but in this example, the film quality is stable from 0.6 nm to 10 nm. In the embodiment of FIG. 7, both the ZnO film thickness and the impurity doping amount are changed independently. By adjusting the thicknesses d ₁ and d ₂ of the potential barrier layers 1S ′ and 1D ′ independently on the source side and the drain side, the asymmetry is almost unlimited in the region of Q _C1 ≧ 0.0001 and Q _C3 ≧ 0.0001. The coefficient β and the interface resistance can be changed.

The crosses in the figure indicate combinations of the interface resistances Q _C1 and Q _C3 when only MR ratios less than 1% of the maximum value of the MR ratio can be obtained.

  As materials and dimensions of each element, the following can be adopted.

  (Semiconductor substrate 1A)

  As a material of the semiconductor substrate 1A, a semiconductor such as Si or Ge, or a compound semiconductor such as GaAs or InGaAs can be used. In the semiconductor substrate 1A, the shortest distance between the source electrode 2S and the drain electrode 2D, that is, the channel length (d) is preferably 0.1 μm or more and 100 μm or less. This channel length (d) is set shorter than the spin diffusion length in the semiconductor substrate 1A. The material of the semiconductor substrate 1A of this example is Si, the channel length (d) is 3 μm, and the resistivity of the substrate is 1 Ω · cm. The conductivity type of the semiconductor substrate 1A is N-type, but can also be P-type.

(Source electrode 2S)
As the material of the source electrode 2S, transition metals such as Co and Fe, transition metal alloys such as CoFe, Heusler alloys such as Co ₂ MnSi, Co ₂ MnGe, Co ₂ FeAl and Co ₂ FeSi, and ferromagnetic such as Fe ₃ Si Silicides or half metals such as CrO ₂ , Fe ₃ O ₄ , and (LaSr) MnO ₃ can be used. The material of the source electrode 2S in this example is Co ₂ MnSi, and the planar dimensions of the electrode are 10 μm × 0.5 μm.

(Drain electrode 2D)
The material of the drain electrode 2D includes transition metals such as Co and Fe, transition metal alloys such as CoFe, Heusler alloys such as Co ₂ MnSi, Co ₂ MnGe, Co ₂ FeAl and Co ₂ FeSi, and ferromagnetic such as Fe ₃ Si. Silicides or half metals such as CrO ₂ , Fe ₃ O ₄ , and (LaSr) MnO ₃ can be used. The material of the drain electrode 2D in this example is Co ₂ MnSi, and the planar dimension of the electrode is 10 μm × 0.5 μm. That is, the drain electrode 2D can be made of the same material and dimensions as the source electrode 2S.

  (Gate insulation film 3)

As the gate insulating film 3, SiO ₂ can be used. As the gate insulating film 3, SiN or the like can be used in addition to the oxide insulator.

  (Gate electrode 4)

  The material of the gate electrode 4 is not particularly limited as long as it is a conductor. As a material of the gate electrode 4, for example, Au, Ag, Cu, Al, Ni, silicide, an alloy containing these elements, AuGeNi, or the like can be used.

  (Additive impurities)

  When the semiconductor substrate 1A is made of Si, P (phosphorus) can be used as an N-type impurity. In the case of other semiconductors, known impurities corresponding thereto can be used. The carrier concentration at room temperature in the semiconductor is assumed to be equal to the impurity concentration.

  (Potential barrier film 1S ', 1D')

For the potential barrier films 1S ′ and 1D ′, insulating films such as MgO, SiN, Al ₂ O ₃ , HfO ₂ , and ZnO can be used. ZnO is also a semiconductor, and an N-type carrier concentration of 1 × 10 ¹⁴ / cm ³ to 1 × 10 ²¹ / cm ³ can be used and does not necessarily have to be tunnel conduction. A semiconductor such as TiO ₂ or GaN can also be used.

  Next, the conductivity matching conditions used for obtaining the above simulation graph will be described in detail.

First, the definition of parameters used for the explanation is as follows. If there is a parameter variation in the area, the average value is used as the parameter value.
· Lambda _N: spin diffusion length in the semiconductor substrate 1A · λ _F: spin diffusion length of the source electrode 2S and a drain electrode in the 2D · d: channel length of the semiconductor substrate 1A · _{R N:} Spin-resistance of the semiconductor substrate 1A · [rho _N : Channel resistivity of semiconductor substrate 1A, ρ _F : channel resistivity in source electrode 2S and drain electrode 2D, S: channel cross-sectional area between source and drain, α _C : polarization in a region generally providing a potential barrier Ratio · α _C1 : Spin polarizability in the region 1S that provides the potential barrier between the source electrode 2S and the semiconductor substrate 1A • α _C3 : In the region 1D that provides the potential barrier between the drain electrode 2D and the semiconductor substrate 1A spin polarization · σ (up): conductivity of the magnetic body of up-spin electrons · σ (down): the magnetic body down-spin electrons conductivity · sigma _C Stay up-): tunnel conductivity of up-spin electrons · σ _{C (down):} tunnel conductivity of down-spin electrons · alpha _F: spin polarization of a typical magnetic · alpha _F1: spin polarization of the source electrode 2S · alpha _F3: drain electrodes 2D of the spin polarization _· Q C: _{R N} interfacial _resistance, normalized by Q C1: interfacial resistance · _Q between the standardized semiconductor substrate 1A and the source electrode 2S in _{R N C3:} interface resistance · _{R F} between the standardized semiconductor substrate 1A and the drain electrode 2D with R _N: spin resistance of the magnetic material · _{R F1:} source electrode 2S of the spin resistance · _{R F3:} spin resistance of the drain electrode 2D · Q _{F: R N-spin} resistance of standardized magnetic body Q F1: _{R N} spin _{resistance-of} the source electrode 2S standardized by Q F3: spin resistance, the _{R N} with standardized drain electrode 2D R: magnetoresistance ratio (MR ratio)
R _C : Resistance when passing through the region 1S or 1D that provides the barrier (tunnel resistance)
R _C1 : Resistance when passing through the region 1S R _C3 : Resistance when passing through the region 1D

Note that the spin resistance is a resistance per spin diffusion length divided by 1-α _F ² .

In the following description, the following mathematical expressions are referred to.

The spin diffusion theoretical model given by the equations (2) to (12) is applied when the resistances at the two interfaces are different. Note that the resistivity ρ _N in the equation (4) is given by the differential resistance between the source and drain of the semiconductor substrate 1A after the device is formed. ΔR obtained from these equations (13) and (14) represents the magnitude of resistance change due to magnetization reversal of the drain electrode. In this equation, the parameters related to spin injection and the parameters on the spin take-out side appear symmetrically. Since the resistance on the spin injection side guides the spin current to the channel, a higher ΔR can be obtained. On the spin extraction side, the spin direction is interrupted when the magnetization direction is antiparallel, so that a higher ΔR can be obtained with a higher resistance.

  Considering that the change in resistance is due to the difference in spin accumulation between parallel and antiparallel magnetization directions, the spin injection side should not be accumulated by flowing a spin current as much as possible, and the extraction side should be spin-free. It plays a role of blocking and accumulating the flow, and this is thought to have produced a large resistance change as a result.

  Equation (1) is obtained by dividing the resistance change ΔR given by Equations (13) and (14) by the reference resistance indicated by the denominator of Equation (15) to obtain the resistance change rate (MR ratio). is there. In the tunnel magnetoresistive element, the MR ratio is generally normalized by the resistance between the electrodes, but here, the channel resistance is ignored and the interface resistance is normalized. This is because of the merit of improving the symmetry of the formula and making the essence easy to read, but the actual device channel length is less than a fraction of the spin diffusion length. Even if standardized by resistance, the matching condition is almost the same. When the maximum value of MR ratio is obtained, the above-described conductivity matching condition is satisfied.

That is, when Q _C1 and Q _C3 satisfying the formula (1) MR ratio are Q _C1 = Q _C3 , the MR ratio is maximum (= 100%). However, as shown in FIG. The ratio satisfies 1% or more of the maximum value, preferably 10% or more. The interfacial resistance Q _C1 of the source electrode 2S and the semiconductor substrate 1A in the spin MOSFET, but the interface resistance Q _C3 of the drain electrode 2D and the semiconductor substrate 1A are different nature, thicker at the drain side the thickness of the tunnel barrier layer, as described above By doing so, the interface resistance in a drain can be enlarged and these interface resistances can be made equal. That is, when Q _C1 = Q _C3 , the electrical symmetry of the spin device is ensured and the MR ratio is increased. Since Q _C1 improvement effect of the MR ratio when they do not coincide in _{Q C3 is, Q} C1 ₌ Q 1% or more of the MR ratio in the case of _C3, the _{Q C1} and _{Q C3} to preferably satisfy 10% or more If the relationship is set, the MR ratio can be improved.

In other words, when the interface resistance on the source side (= R _N / 2) = spin resistance in the semiconductor substrate (= 2λ _N ρ _N / S) = the interface resistance on the drain side (= R _N / 2) The rate is consistent. When Q _C3 = β × Q _C1 , the MR ratio takes a maximum value when the function of this straight line satisfies the value of the hyperbola Q _C1 × Q _C3 = 1. On this hyperbola, the MR ratio is maximized when Q _C1 = Q _C3 .

FIG. 8 is a graph of the MR ratio when the interface resistance Q _C1 is changed when the asymmetry coefficient β is 0.01 to 100. FIG. 9 is a graph obtained by logarithmically displaying the graph shown in FIG. Here, MR ^* = MR / (4 × α _C1 × α _C3 ). d / λ _N = 0.3. That is, the channel length is 30% of the spin diffusion length. When β is 10 and 100 and the asymmetry is high, the maximum value of the MR ratio is small. When Q _C1 = β ^−0.5 , the MR ratio is maximized. In this case, Q _C3 = β ^0.5 , and the maximum value of the MR ratio is obtained when β = 1.

10, when d / lambda _N is 0.1 to 10, a graph of the MR ratio when changing the asymmetry factor beta.

  It can be seen that the maximum value of the MR ratio is obtained when β = 1, and that the larger the MR ratio is, the shorter the channel length d is. From the graph of MR ratio, it can be seen that the range in which the asymmetry coefficient β can be practically used is limited to 0.01 ≦ β ≦ 100, and preferably 0.1 ≦ β ≦ 10.

FIG. 11 is a graph showing a specific example of the source / drain resistance R (Ω) and the MR ratio, which are ρ _N = 1 Ωcm, S = 10 μm × 0.5 μm = 5 μm ² , λ _N = 10 μm. , R _N = 40 kΩ, d = 3 μm, α _C1 = α _C3 = 0.4 (material: CoFe). The MR ratio is normalized by the interface resistance _RC . In the structure of FIG. 5, the semiconductor substrate 1A is N-type, P (phosphorus) as an impurity is ion-implanted into the semiconductor substrate immediately below the source electrode 2S by δ doping, and P is also injected into the semiconductor substrate immediately below the drain electrode 2D. In this example, (phosphorus) is ion-implanted with δ-doping and activated. Impurity concentration _{N D} of the source-side impurity concentration _{N S,} the drain side of this embodiment are both 1 × ¹⁰ 20 / cm ^3.

The interface resistance between each electrode 2S, 2D and the semiconductor substrate 1A is governed by the tunnel resistance of the potential barrier layer. The potential barrier layers 1S ′ and 1D ′ are made of SiN and can have thicknesses of 0.1 nm to 2 nm, respectively. Note that the thicknesses d _S and d _D of the tunnel barrier layer are 5 nm and 6 nm, respectively, and the thicknesses d ₁ and d ₂ of the insulating layer are 0.3 nm and 1.5 nm, respectively. In this case, β is approximately 1. The figure also shows the case where the value of β is changed.

  FIG. 12 is a graph showing the asymmetry coefficient β and the MR ratio under the conditions of FIG.

This is a graph of ρ _N = 1 Ωcm, S = 10 μm × 0.5 μm = 5 μm ² , R _N = 40 kΩ, α _C1 = α _C3 = 0.4 (material: CoFe). The MR ratio is normalized by the interface resistance _RC . Rc is the sum of the interface resistances of the source and drain, and consists of the tunnel resistance of the insulating film and the Schottky barrier. In the case of λ _N = 10 μm and d = 3 μm, d / λ _N = 0.3, but this figure also shows the case where the value of d / λ _N is changed. Other conditions are the same as in FIG.

  Next, the FET of the second embodiment will be described.

  FIG. 13A is a diagram schematically illustrating each element of the FET according to the second embodiment, and FIG. 13B illustrates energy at each position of the element illustrated in FIG. It is an energy band figure.

FIG. 13 shows a configuration in which the source-side insulating layer shown in FIG. 6 is omitted, and the other structure is the same as that shown in FIG. Of course, also in the FET of this embodiment, the above-described relationship of d _S <d _D is satisfied. In the case of this example, if the above-mentioned thickness d ₁ = 0 is considered, the relationship d ₁ <d ₂ is also satisfied.

  The polarized spin injected from the source electrode 2S tunnels through the potential barrier 1S not including the insulating layer and flows into the semiconductor substrate 1A. The polarized spin is taken out from the drain electrode 2D through the potential barrier 1D including the potential barrier layer 1D '. Except for this point, the operation of the FET of the second embodiment is the same as that of the first embodiment. That is, when the source-side Schottky interface resistance is already close to the value of the channel spin resistance, insertion of the source-side tunnel film can be omitted.

  In the above description, the spin MOSFET using the gate insulating film is shown, but the present invention can also be applied to a junction FET (JFET) or the like excluding the gate insulating film. That is, as the semiconductor spin device of the present invention, a magnetic head element such as a TMR element, a spin MOSFET, or a spin junction FET can be considered as long as spin conduction is performed. Since the above-described spin FET can increase the MR ratio between the source and the drain, when used in an MRAM or the like, the data read accuracy can be improved. It is also possible to provide an insulating layer only on the source side in the FET.

1 is a plan view of a spin MOSFET according to a first embodiment. It is the II-II arrow sectional view taken on the line of the spin MOSFET shown in FIG. (A) It is the figure of FET which each element was modeled, (b) is an energy band figure which shows the energy in each position of the element shown to (a). It is a top view of spin MOSFET concerning a 2nd embodiment. FIG. 6 is a cross-sectional view taken along the line VI-VI of the spin MOSFET shown in FIG. 5. (A) It is the figure of FET which each element was modeled, (b) is an energy band figure which shows the energy in each position of the element shown to (a). Shows the normalized interface resistance Q _C1 between the source electrode 2S and the semiconductor substrate 1A, the distribution of the MR ratio obtained by the normalized interface resistance Q _C3 between the drain electrode 2D and the semiconductor substrate 1A It is a graph. Asymmetry factor β is a graph of the MR ratio when changing the interfacial resistance _{Q C1} in the case of 0.01. 10 is a logarithmic display of the graph shown in FIG. If d / lambda _N is 0.1 to 10, a graph of the MR ratio when changing the asymmetry factor beta. It is a graph which shows a specific example of resistance R (ohm) between source / drain, and MR ratio. 13 is a graph showing the asymmetry coefficient β and the MR ratio under the conditions of FIG. (A) It is the figure of FET which each element was modeled, (b) is an energy band figure which shows the energy in each position of the element shown to (a).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1A ... Semiconductor substrate, 2S ... Source electrode, 4 ... Drain electrode, 2D ... Drain electrode.

Claims (4)

A first electrode comprising a fixed layer;
A second electrode comprising a free layer;
A semiconductor region provided with the first and second electrodes;
With
The thickness d _S of the first tunnel barrier layer interposed between the first electrode and the semiconductor region, and the thickness d _D of the second tunnel barrier layer interposed between the second electrode and the semiconductor region are: The following relation:
d _S <d _D
A semiconductor spin device characterized by satisfying The first tunnel barrier layer has a first insulating layer;
The second tunnel barrier layer has a second insulating layer;
The thickness d ₁ of the first insulating layer and the thickness d ₂ of the second insulating layer are expressed by the following relational expression:
d ₁ <d ₂
The semiconductor spin device according to claim 1, wherein: The first tunnel barrier layer includes a first semiconductor layer having an energy band gap wider than that of the semiconductor region;
The second tunnel barrier layer includes a second semiconductor layer having an energy band gap wider than that of the semiconductor region;
Wherein the thickness d ₁ of the first semiconductor layer, the thickness d ₂ of the second semiconductor layer, the following relationship:
d ₁ <d ₂
The semiconductor spin device according to claim 1, wherein: In the spin FET having the semiconductor spin device according to any one of claims 1 to 3,
The first electrode as a source electrode;
The second electrode is a drain electrode,
A spin FET comprising a gate electrode for controlling a potential of the semiconductor region between the source electrode and the drain electrode.