JPS59175774A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the FET having a substantially high mobility by a method wherein when a layer not-including an impurity and a layer including it are laminated on a semiconductor substrate to be subjected to an epitaxial growth, these layers are selected to be a single-atom layer or a thin layer according to that and the layer including impurities is doped with the specified impurity. CONSTITUTION:On an N type Si substrate 11, a single crystal layer 12 not- including an impurity and an Si layer 13 to which As of 10<16>/cm<3> is added, which are about 1,000Angstrom thick, are alternately grown by a molecular beam epitaxial method. The base for FET is thus formed and the upmost layer is covered with a Shottky electrode 14. Consequently, the characteristics of voltage- electrostatic capacitance of the FET shows a steps form as is shown in the drawing. In this constitution, the thickness of the epitaxial layer is not limitted to the present one. The thickness of 100-1,000Angstrom is also efficient and as for the concentration for adding impurities, 10<15>-5X10<16>/cm<3> may be preferable.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device based on a conventional construction principle.

Conventionally, p-n junctions, which are the main component of semiconductor devices, have been made by diffusion methods, alloy methods, ion implantation methods, and growth junction formation methods. However, p-n created using this method
In both junctions, the concentration of fine particles is statistically distributed and continuously changes spatially. For this reason, when attempting to miniaturize semiconductor devices, for example, there are physical limits due to the statistical distribution of this impurity concentration.

When doping impurities into a semiconductor layer, the present invention controls impurity atoms in units of monoatomic layers and localizes the impurities in predetermined regions within the semiconductor layer, thereby achieving characteristics that cannot be achieved with conventional methods. An object of the present invention is to provide a semiconductor device having the following features.

The present invention relates to a semiconductor device constructed using semiconductor materials as base materials, wherein the impurity region introduced into the base material is an impurity region in which impurities are limited within a monoatomic layer or a thin layer similar thereto. It is characterized by having the following.

This structure was only realized after the development of the molecular beam epitaxial method.

Since the semiconductor device of the present invention has the characteristic semiconductor multilayer structure as described above, it is possible to realize a semiconductor device having distinctive characteristics that could not be realized with conventional semiconductor devices. .

In general, in a semiconductor device including a depletion layer, impurities are introduced in a concentrated manner into a monoatomic layer or a single or multiple layers having the same number or thickness as the depletion layer, or in particular at least It is designed to include one or more layers containing impurities. In this example below, the layer to which impurities are added is only one monoatomic layer, but it may be a polyatomic layer or may be composed of a plurality of these layers.

Examples of a semiconductor device having stepped voltage-capacitance characteristics and a short channel high speed field effect transistor (FET) will be specifically described.

First, an example of step-like voltage-capacitance characteristics will be explained.

Using a Si molecular beam source and an arsenic molecular beam source, a multilayer structure as shown in FIG. 1 is created by alternately growing 81 molecular beam epitaxy layers and arsenic-doped layers on a substrate crystal. 11 is a P-type silicon (Si) substrate, 12 is a silicon semiconductor layer, 13 is a silicon layer in which arsenic impurities are localized, and 14 is an electrode. At this time, when adding arsenic, a shutter is placed in front of the Si molecular source to suppress the addition of arsenic to less than a monomolecular layer. FIG. 2 shows the distribution of impurity atoms in the multilayer structure thus created.

Next, the characteristics when an electric field is applied to a semiconductor device having an impurity concentration distribution as shown in FIG. 2 will be described.

The difference .DELTA.E1 in electric field strength on both sides of the .delta.-function type impurity concentration distribution as shown in FIG. 2 can be determined by integrating the one-dimensional Boissono equation.

However, ψ is the potential energy, and ρ(x) is the charge distribution due to impurities, which is ρ(X) - ρ. δ(x-ai)
It is expressed as Here, ε8 indicates the electrostatic dielectric constant a1 of the semiconductor and the position of the impurity layer. By integrating equation (1) in the vicinity of al, the difference ΔEi in electric field strength on both sides of ai is as follows. Here, ρ0 is the impurity concentration per unit area Ni
When replaced with [m-2), ΔE1 in equation (2) becomes ΔE;
= 1.56X10-9N, [V/m, l (3
).

In this case, the thickness d [m] 0. ) The capacitance C of the semiconductor layer is (4) per m2.

Therefore, the voltage-capacitance characteristic of the semiconductor device shown in FIG. 1 becomes step-like as shown in FIG. Further, as is clear from equation (3), the size of the capacitance and voltage step can be arbitrarily changed by appropriate impurity concentration and interval between impurity-doped layers.

An example will be described in which an impurity region in which impurities are limited in a monoatomic layer or a thin layer similar thereto, which is a feature of the present invention, is applied to a field effect transistor.

The impurity is provided locally and is present in a region away from the channel. The carrier concentration is determined by the voltage applied to the gate electrode and the impurity distribution depending on the semiconductor layer containing impurities.

Because of these structural features, it has the following advantages.

(1) Since the channel region does not contain impurities, carriers are not subject to impurity scattering. Therefore, higher mobility can be achieved.

In the case of a normal MOSFET, the channel length (,l) is designed to maintain a relationship of lαNi −2 with respect to the impurity concentration (Ni) of the substrate. However, in this case, no matter what manufacturing method is used, it is impossible to achieve a carrier mobility exceeding the level shown in Table 1 depending on the impurity concentration of the substrate.

In contrast, in the semiconductor device of the present invention, as shown in Table 1, an FET with much higher mobility than the conventional example can be realized. In order to facilitate comparison, the added impurity concentration in the case of the present invention is shown in the table as the depletion region in the channel region.
n ) as the average effective impurity concentration.

(2) Shorter channels, that is, miniaturization of semiconductor devices (Table 1)
Allows for comparison of mobilities. Conventionally, it has been thought that the limit of miniaturization of MOS transistors is determined by the impurity concentration in the Si substrate.

In other words, in order to reduce the channel length l of a transistor (MOS), it is necessary to sieve the impurity concentration Ni of the substrate, and the minimum channel length l(!: impurity concentration N
As described above, i is in the relationship lαN1-2. However, if the impurity concentration Ni is increased, the spatial f and IK movement of the potential within the channel/channel of the MOS transistor increases, so the upper limit of N1 is approximately IQ''[m'').

In this case, it was theoretically impossible to reduce the channel length to less than 10 times R* (10-7 m (1000 people)) when the average distance between impurity atoms was R''=10'm.

However, in the semiconductor device of the present invention, there are few impurities near the channel, so that spatial fluctuations in the potential well can be made extremely small, and therefore a short channel can be realized.

For example, the same number of impurity atoms as the number of impurity atoms in the range of D from the interface between 5in2 and Si of a Δ/i0S transistor are added concentratedly to a single atomic layer separated by a distance from the interface between SiO□ and Si. Let's consider the case. When impurities are uniformly added to a conventional substrate, the spatial variation of the channel potential of a MOS transistor is ~e2
/ε5ε. When added to a monoatomic layer, the fluctuation of the moss potential becomes smaller by three times (R'/D). Here, R/
” is the average distance between impurity atoms in a monoatomic layer.

If this is the upper limit of impurity concentration Nl ``1024m'', then R*=10'm, R'''=0.5X10 a
m, and when D=500 people, the variation in potential in the channel will be 1/100 or less compared to the conventional case.

Since there is little variation in potential within the channel, noise at frequencies is also low.

(3) Variations in threshold values of a large number of semiconductor elements are reduced. Therefore, the yield is improved.

This is because, as described above, there are no impurities near the channel, and spatial fluctuations in the potential well ζ are extremely small. If the spatial variation of the potential well is large, the gate voltage ■. By measuring how the drain current ■9 rises, the threshold voltage value of the gate voltage (
V, h) becomes unclear. Moreover, the threshold voltage values of a large number of semiconductor devices will vary statistically.

In the configuration of the present invention, these problems can be greatly reduced.

That is, the rise of the current between the source and the drain becomes sharp near the threshold voltage.

Example Using a molecular beam source of Si and arsenic, a Si single-crystal layer 12 with a thickness of 10' m (1000 m) was deposited on a Si n-type substrate crystal 1, and As was deposited within the monoatomic layer of 10 m (101 m).
2cm-2) doped Si layers 13 are grown alternately by molecular beam epitaxial method to create the laminated structure shown in FIG. AI is on the surface of this laminated structure! The Schottky electrode 14 is formed by electron beam evaporation. Note that the area of the device is lQXIOm. The voltage of this semiconductor device -
The static capacitance characteristics became step-like as shown in Figure 3. S
Thickness of one layer of molecular beam epitaxy of lXl0 ”m (10
0 people) to 1'0-6m (10,000 people) impurity doped layer 1! A similar step-like voltage-capacitance characteristic can be obtained from #1015 m'-2 (10" cm-2) to 5 x 1016 m-2 (5 x 1012 cm'-2).

Embodiment 2 FIGS. 4 and 5 are cross-sectional views of a semiconductor device of the present invention showing each step of the manufacturing process.

A silicon (Si) substrate 41 is mounted in a molecular beam eviction device, and molecular beam sources of Si and boron (B) are prepared. The vacuum inside the molecular beam epitaxial equipment is 1O-9To
rr or less, Si substrate 41ff, thickness 10'm 5
iN42 was grown by molecular beam epitaxial growth, and then 8
Boron concentration 5x1016m in monoatomic layer on 4th layer 42
A Si layer 43 with a thickness of 10'-7 m (100'l) is grown on this S1 layer 43 by molecular beam epitaxial growth. FIG. 4 is a cross-sectional view showing this state. In this example, the impurity is localized within a single atomic layer, but the impurity may be introduced into multiple layers.

In this case, unlike conventional impurity introduction methods, it is important to localize the impurity concentration so that it does not substantially have a vertical needle distribution.

The gate oxide film 56 is made of SiO2 with a thickness of 500 nm by a well-known thermal oxidation method on the upper part of the multilayer structure shown in Figure G4.
This was used as a membrane. The source and drain electrode regions 55 and 55' were formed by thermally diffusing arsenic into the first semiconductor layer using a CVD SiO2 film as a diffusion mask.

The gate electrode 57 is made of metal AI! on the gate oxide film 56.
was formed by vapor deposition. FIG. 5 is a sectional view showing this state.

In this way, an FET (field effect transistor) could be manufactured. Its channel length is 10-7 m (100
0 large), which would have been inoperable with F'ET manufactured using conventional silicon process technology.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a cross-sectional view of a semiconductor device having stepped voltage-capacitance characteristics, FIG. 2 is a diagram showing the impurity concentration distribution of the semiconductor device, and FIG. 3 is a diagram of the semiconductor device. Figures 4 and 5 showing the voltage-capacitance characteristics are cross-sectional views of the device for explaining the manufacturing process of the semiconductor device of the present invention. 11.41: Semiconductor substrate, 13, 43: Second semiconductor layer containing impurities, 12.44: First semiconductor layer containing no impurities, 14.57: Electrode A 3 Figure LpF 4°C rL V tv of

Claims (1)

[Claims] (1) A semiconductor device constructed using a semiconductor material as a base material, wherein the impurity is limited to a monoatomic layer or a thin layer equivalent thereto as an impurity region introduced into the base material. A semiconductor device characterized by having an impurity region.