JPS62271475A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62271475A JPS62271475A JP8091487A JP8091487A JPS62271475A JP S62271475 A JPS62271475 A JP S62271475A JP 8091487 A JP8091487 A JP 8091487A JP 8091487 A JP8091487 A JP 8091487A JP S62271475 A JPS62271475 A JP S62271475A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- impurity
- semiconductor layer
- semiconductor
- molecular
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
- 239000012535 impurity Substances 0.000 claims abstract description 50
- 230000005684 electric field Effects 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- 239000000758 substrate Substances 0.000 abstract description 11
- 238000009826 distribution Methods 0.000 abstract description 7
- 229910052796 boron Inorganic materials 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 238000001704 evaporation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 47
- 238000000034 method Methods 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 239000000969 carrier Substances 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- -1 but in general Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 102220082323 rs35269563 Human genes 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は新規な原理に基づく半導体装置ｆこ関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device based on a novel principle.
従来半導体装置の主要部分であるｐ−ｎ接合は、拡散法
、合金法、イオン打込み法、成長接合形成法等番こよっ
て作られていた。しかしこれｑ等の方法で作製したｐ−
ｎ接合は、いずれにおいても不純物ａ度は統計的番こ分
布し、空間的１こも連続的に変化している。このためた
とえば半導体素子を微細化しようとする時、この不純物
濃度が統計的に分布していることから来る物理的限界が
存在した。Conventionally, p-n junctions, which are the main part of semiconductor devices, have been made by various methods, such as diffusion methods, alloy methods, ion implantation methods, and growth junction formation methods. However, this p-
In all n-junctions, the degree of impurity is statistically distributed and continuously changes spatially. For this reason, when attempting to miniaturize semiconductor elements, for example, there are physical limits due to the statistical distribution of this impurity concentration.
本発明は半導体層中ｆこ不純物を添加する場合、不純物
原子を単原子層の単位で制御し、不純物を半導体層内の
所定領域に局在せしめることにより、従来の方法では達
成することが出来ない特性を有する半導体装置を提供す
ることを目的とする。When adding impurities into a semiconductor layer, the present invention controls the impurity atoms in units of monoatomic layers and localizes the impurities in predetermined regions within the semiconductor layer, which cannot be achieved using conventional methods. An object of the present invention is to provide a semiconductor device having unique characteristics.
本発明の骨子は不純物を実質的に含有しない第１の半導
体層と、これ１こ近接し且不純物を含有する第２の半導
体層を設け、且該第１の半導体層をキャリアの移送領域
とせしむるものである。The gist of the present invention is to provide a first semiconductor layer that does not substantially contain impurities, and a second semiconductor layer that is adjacent to the first semiconductor layer and that contains impurities, and to use the first semiconductor layer as a carrier transport region. It's something to feel.
こうした構成は分子線エピタキシャル法の開発を待って
はじめて実現出来たものである。This configuration was only possible after the development of the molecular beam epitaxial method.
以下、本発明をひとつの具体例を用いて詳細に説明する
。第１図、第２図は本実施例の半導体装置の製造工程の
各段階を示す装置断面図である。Hereinafter, the present invention will be explained in detail using one specific example. FIGS. 1 and 2 are device cross-sectional views showing each stage of the manufacturing process of the semiconductor device of this embodiment.
シリコン（Ｓｉ）基板４１を分子線エピタキシャル装置
内に装着し、シリコンおよびほう素（Ｂｌの分子線源を
準備する。分子線エピタキシャル装置内を真空度１Ｏ−
Ｔｏｒｒとなし、シリコン基板４１上（仁厚さ１０
ｍのシリコン層４２を分子線エピタキシャル成長し、更
に続けてシリコン層４２上に単原子層内にほう素を濃度
５ Ｘ １ ｄ’ｍ−２で含有せしめたシリコン、’＋
！ ４３ 、：６よびこのシリコン層４３上Ｉこ厚ざ１
０ ｍ（１０００人）ののシリコン層４４を分子線
エピタキシャル成長する。第１図はこの状態を示した断
面図である。この例では不純物は単原子層内に局在せし
めたが、札
一般には更に多数層に不域物を導入しても良い。A silicon (Si) substrate 41 is mounted in a molecular beam epitaxial apparatus, and silicon and boron (Bl) molecular beam sources are prepared.
Torr and on the silicon substrate 41 (thickness 10
A silicon layer 42 of m is grown by molecular beam epitaxial growth, and then silicon containing boron at a concentration of 5 x 1 d'm-2 in a monoatomic layer on the silicon layer 42, '+
! 43 , :6 and the thickness of this silicon layer 43 1
A silicon layer 44 of 0 m (1000 layers) is grown by molecular beam epitaxial growth. FIG. 1 is a sectional view showing this state. In this example, impurities are localized within a single atomic layer, but in general, impurities may be introduced into many more layers.
この場合肝要なことは従来の如き不純物導入の方法と異
なり、不純物濃度が実質的に統計的分布を有さないよう
局在せしめることである。ゲート酸化膜５６としては第
１図に示した多層構造体の上部を周知の熱酸化法によっ
て厚さ５００ＡのＳｉＯ□膜としこれを用いた。又ソー
スおよびドｌツイン電極領域５５ 、５５ ’の形成は
ＣＶＤ法に依る５ｉｎ２膜を拡散用マスクとして砒素を
第１の半導体層に周知の熱拡散法によって形成した。What is important in this case, unlike conventional impurity introduction methods, is to localize the impurity concentration so that it has substantially no statistical distribution. As the gate oxide film 56, an SiO□ film having a thickness of 500 Å was formed on the upper part of the multilayer structure shown in FIG. 1 by a well-known thermal oxidation method. The source and dou-twin electrode regions 55 and 55' were formed by forming arsenic in the first semiconductor layer by a well-known thermal diffusion method using a 5in2 film formed by CVD as a diffusion mask.
ゲート電琢５７は前記ゲート酸化膜５６上ｆこ金属ＡＩ
を蒸着して形成した。第２図がこの状態を示す断面図で
ある。A gate electrode 57 is made of metal AI on the gate oxide film 56.
was formed by vapor deposition. FIG. 2 is a sectional view showing this state.
この様にしてＦ”ＥＴ （電界効果トランジスタ）を作
製することができた。そのチャネル長は１０−’ ｍ
（１０００人）で、従来のシリコン・プロセスを用いた
技術で製造されたＦｇＴでは動作不能であったものであ
る。本例の半導体装置は次の様に構成されている。In this way, we were able to fabricate an F"ET (field effect transistor). Its channel length was 10-' m.
(1,000 people), which would have been inoperable with FgT manufactured using conventional silicon process technology. The semiconductor device of this example is configured as follows.
半導体装置の動作を担うキャリアが閉じ込められる第１
の半導体層と、この第１の半導体層１こ近接して且不純
物を含有する第２の半導体層が配される。上述の例では
シリコン層４４が第１の半導体層、はう素含有のシリコ
ン層４３が第２の半導体層に相当する。The first stage, where the carriers responsible for the operation of the semiconductor device are confined
A second semiconductor layer containing an impurity is disposed adjacent to the first semiconductor layer. In the above example, the silicon layer 44 corresponds to the first semiconductor layer, and the boron-containing silicon layer 43 corresponds to the second semiconductor layer.
この第１の半導体層は実質的に不純物を含有しない。This first semiconductor layer does not substantially contain impurities.
そして、第１の半導体層に電子的に接する如く配された
キャリアの移送手段、および該キャリアの制御手段を有
する。The semiconductor device also includes a carrier transport means disposed so as to be in electronic contact with the first semiconductor layer, and a carrier control means.
このキャリアの制御手段に所定の電圧を印加した時、前
記第１の半導体層のゲート電像側の界面には轟然エネル
ギー・バンドの井戸が構成される。When a predetermined voltage is applied to this carrier control means, a well of a powerful energy band is formed at the interface of the first semiconductor layer on the gate voltage side.
上記構成を有する半導体装置の動作は第３図に示した電
子エネルギー構造によって説明される。The operation of the semiconductor device having the above configuration will be explained using the electron energy structure shown in FIG.
第３図において１は半導体基板、２はバッファ層にの層
は必ずしも必要でげないが、半導体基板面の結晶性改善
のため、半導体装置の製造に一般的に用いられている手
段である）、３は第２の半導体層で不純物を含有してい
る層である。図はこの不純物がイオン化している状態を
示している。In FIG. 3, 1 is a semiconductor substrate, and 2 is a buffer layer.Although this layer is not necessarily necessary, it is a method commonly used in the manufacture of semiconductor devices to improve the crystallinity of the semiconductor substrate surface.) , 3 is a second semiconductor layer containing impurities. The figure shows the state in which this impurity is ionized.
４は第１の半導体層で実質的に不純物を含有していない
層である。６は第１の半導体層の界面にポテンシャルの
井戸を形成せしめるための所望の材料層、７はキャリア
の制御のためのゲート電極を示している。4 is a first semiconductor layer that does not substantially contain impurities. Reference numeral 6 indicates a desired material layer for forming a potential well at the interface of the first semiconductor layer, and 7 indicates a gate electrode for controlling carriers.
この機番こして本実施例の半導体装！においてはキャリ
アが閉じ込められる第１の半導体層４に近接して不純物
を含有する第２の半導体層３が配され、且不純物原子を
単原子層の単位で側倒出来る手段でもって層を形成する
ため、導入された不純物の＠度分布は砥めて局在し、実
質的をこ統計的分布を有さない。この分布の形態は、従
来の不純物の導入方法、たとえば拡散法、イオン打込み
法等ｌこよっては実現出来なかったものである。This model number is the semiconductor device of this example! In the method, a second semiconductor layer 3 containing impurities is disposed close to the first semiconductor layer 4 in which carriers are confined, and the layer is formed using a method that allows impurity atoms to fall sideways in units of monoatomic layers. Therefore, the degree distribution of the introduced impurities is sharply localized and does not substantially have this statistical distribution. This distribution form could not be achieved by conventional impurity introduction methods such as diffusion and ion implantation.
こうした半導体装置のゲート電極に電圧Ｖ。を印加する
ことによりチャネル内のキャリア＃度が変化し、従って
ソースおよびド１ツイン間のコンダクタンスが変化しＦ
ＥＴの動作を行なわしむることかできる。なお、チャネ
ル内のキャリア濃度はゲート電極に印７１０した電圧Ｖ
。と上記不純物を含む第２の半導体層３に依存する不純
物分布とによって決められる。A voltage V is applied to the gate electrode of such a semiconductor device. By applying F, the number of carriers in the channel changes, and therefore the conductance between the source and the double twin changes.
It is possible to perform ET operations. Note that the carrier concentration in the channel is determined by the voltage V applied 710 to the gate electrode.
. and the impurity distribution depending on the second semiconductor layer 3 containing the impurity.
なお、上述の具体例では半導体材料とし−ごシリコンの
例を説明したが、本発明はこの例【こ限られるものでは
ないことはいうまでもなく、たとえば周知のガリウム−
砒素を代表とする化合物半導体等にも適用し得る。In the above-described specific example, silicon is used as a semiconductor material, but the present invention is not limited to this example; for example, the well-known gallium
It can also be applied to compound semiconductors, typified by arsenic.
こうした構成上に特徴を有するが由に本、顆発明は次の
如き効果を有する。Because of these structural features, the present condyle invention has the following effects.
すなわち、チャネル領域に不純物を含有しないので、キ
ャリアは不純物散乱を受けることがない。That is, since the channel region does not contain impurities, carriers do not undergo impurity scattering.
従って、より高移動度となし得る。Therefore, higher mobility can be achieved.
通常のＭＯＳＦＥＴの場合、チャネル長（１）は基板の
不純物濃度（Ｎｉ）ｆこ対して１ｏｃＮｉ−”の関係を
保って設計される。しかし、この場合、基板の不純物濃
度によって第１表に示す程度のキャリアの移動度を越え
るもの１いかなる製造方法を用いても実現し得ない。In the case of a normal MOSFET, the channel length (1) is designed to maintain a relationship of 1ocNi-'' to the impurity concentration (Ni) of the substrate.However, in this case, depending on the impurity concentration of the substrate, as shown in Table 1, No matter what manufacturing method is used, it cannot be realized that the carrier mobility exceeds the carrier mobility of 1.
これに対し、本発明の実施例のＭＯ８Ｆ’ＥＴにおいて
は第１表に示す通り、従来例ｉこ比較してはるかに高移
動度のＦ’ＥＴを実現出来る。なお、比較を容易ならし
めるため表中、本実施例の場合の添加不純物濃度はチャ
ネル領域におけるディプ１ノツシヨン領域（ｄｅｐｌｅ
ｔｉｏｎ ｒｅｇｉｏｎ ）で平均した実効的不純物＠
度として示した。On the other hand, as shown in Table 1, in the MO8F'ET of the embodiment of the present invention, an F'ET with much higher mobility can be realized compared to the conventional example. For ease of comparison, the added impurity concentration in this example is shown in the table as the depth 1 notation region in the channel region.
Effective impurity averaged over region )
Shown as degrees.
なお、本実施例によれば、下記の如き副次的長所が得ら
れる。In addition, according to this embodiment, the following secondary advantages can be obtained.
（Ａｌ 短チヤネル化、即ち半導体装置の微細化を可
能とする。従来ＭＯＳトランジスタの微細化の第１表
移動度の比較
限界は基板Ｓｉ中の不純物濃度によって決まるとされて
いた。すなわちＭＯＳトランジスタのチャネル長ｌを小
さくするには、基板の不純物濃度Ｎｉを高くすることが
必要であり、その最小のチャネル長１と不純物濃度Ｎｉ
は前述したようにＩｏｅＮｉ−２の関係にある。しかし
、不純物情ＩＪｊＮｉを大きくするとＭＯＳ）ランジス
タのチャネル内のポテンシャルの空間的な変動が大きく
なることから、Ｎｉの上限は、約１ｏ２４（ｍ−３）で
ある。この場合不納原子間の平均距離は♂＝ １０ ＄
−’ｍ（１００λ）であり、従って、ＭＯＳトランジス
タのチャネル長を凡 の１０倍（１０−’ ｍ（１０
００＆））以下にすることは原理的に不可能であった。(Al enables shorter channels, that is, miniaturization of semiconductor devices.Table 1 of miniaturization of conventional MOS transistors
It was believed that the comparative limit of mobility was determined by the impurity concentration in the Si substrate. In other words, in order to reduce the channel length l of a MOS transistor, it is necessary to increase the impurity concentration Ni of the substrate, and the minimum channel length l and the impurity concentration Ni
As mentioned above, is in the IoeNi-2 relationship. However, if the impurity information IJjNi is increased, the spatial fluctuation of the potential within the channel of the MOS transistor increases, so the upper limit of Ni is approximately 1024 (m-3). In this case, the average distance between non-conforming atoms is ♂ = 10 $
-'m (100λ), therefore, the channel length of the MOS transistor is 10 times the normal length (10-'m (100λ)).
00 &)) or less was impossible in principle.
しかし、本実施例の半導体装置においてはチャネル近傍
に不純物がすく、ポテンシャルノ井戸に空間的震動が極
めて小さくすることができ、従って短チヤネル化を実現
することが出来る。However, in the semiconductor device of this embodiment, since there are few impurities near the channel, spatial vibration in the potential well can be made extremely small, and therefore a short channel can be realized.
たとえば、Ｎ１０ＳトランジスタのＳ ｉ０２とＳｉの
界面から厚さＤの節回にある不純物原子数と同数の不純
物原子をＳｉＯ□とＳｉの界面から距離りだけはなれた
単原子層にだけ集中して添カロした場合を考えてみる。For example, the same number of impurity atoms as the number of impurity atoms in a node of thickness D from the interface between Si02 and Si of an N10S transistor is concentrated and added only to a monoatomic layer that is a distance away from the interface between SiO□ and Si. Let's consider what happens when you lose weight.
従来の基板に不純物を均一に添加した場合のＭＯＳトラ
ンジスタのチャネルポテンシャルの変動は
になる。すなわちポテンシャルの変動は（Ｒ′＊／Ｄ）
３倍だけ小さくなる。ここでＲ″は単原子層内の不純物
原子間の平均距離である。When impurities are uniformly added to a conventional substrate, the channel potential of a MOS transistor fluctuates as follows. In other words, the variation in potential is (R'*/D)
It will be 3 times smaller. Here, R'' is the average distance between impurity atoms in a monoatomic layer.
これを不純物Ｑ度の上限Ｎ ｉ ＝ １０” ｍ−３と
するとＲ＊＝ １０−８ｍ 、 Ｒ”＝０．５Ｘ１０−
’となり、Ｄ＝５００人とすると、従来の場合より、チ
ャネルにおけるポテンシャルの変動ハ１／１００以下に
なる。If this is the upper limit of impurity Q degree N i = 10" m-3, then R* = 10-8m, R" = 0.5X10-
', and if D=500 people, the variation in potential in the channel will be 1/100 or less compared to the conventional case.
チャネル内のポテンシャルの変動が少ｆｌいことから高
周波での雑音も低い。Noise at high frequencies is also low because the fluctuations in the potential within the channel are small.
（Ｂｌ 多数の半導体素子のしきい値のばらつきが小
さくなる。従って歩留りが向上する。(Bl Variations in the threshold values of a large number of semiconductor elements are reduced. Therefore, the yield is improved.
これは前述した通りチャネル近傍に不純物がすく、ポテ
ンシャルの井戸に空間的変動が極めて小さくなるためで
ある。ポテンシャルの井戸の空間的変動が大きい場合ゲ
ート電圧ｖｏｌこよってド１ツイン電流工、かどの様に
立ち上がる乃）を測定すると、ゲート電圧のしきい電圧
値（Ｖｔｈ）がはっきりしなくなる。しかも多数の半導
体素子において、このしきい値が統計的にばらつくこと
となる。本実施例においてはこうした問題点は大巾に小
さいものとなし得る。即ち、しきい電圧近傍でのソース
と１１７４２間の電流の立上がりが鋭くなる。This is because, as described above, impurities are concentrated near the channel, and spatial fluctuations in the potential well become extremely small. When the spatial variation of the potential well is large, the threshold voltage value (Vth) of the gate voltage becomes unclear when measuring the gate voltage vol (which causes the do1 twin current to rise). Moreover, this threshold value varies statistically among a large number of semiconductor elements. In this embodiment, these problems can be greatly reduced. That is, the rise of the current between the source and 11742 near the threshold voltage becomes sharp.
なお、以上の実施例では不純物を添加する層は単原子層
一層のみであるがこれは多原子層であってもよいし、こ
れらの複数の１−から成っている場合でもよい。動作層
内に空乏層を含む半導体装置においては単原子層もしく
は該空乏層さ同等またはそれより薄い単一または複数の
層に局在して不純物を含有せしめるものである。In the above embodiments, the layer to which impurities are added is only one monoatomic layer, but it may be a multiatomic layer or may be composed of a plurality of these 1- layers. In a semiconductor device including a depletion layer in the active layer, impurities are locally contained in a monoatomic layer or in a single layer or layers that are equal to or thinner than the depletion layer.
第１図および第２図は本発明の実施例である半導体装置
の製造工程を説明するための装置の断面図、第３図は半
導体装置の動作を説明するための有する第２の半導体層
、４，４４：不純物を含有しない第１の半導体層、５５
．５５’：キャリアの移送手段、７．５７：制御手段。1 and 2 are cross-sectional views of a device for explaining the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view of a device for explaining the operation of the semiconductor device. 4, 44: first semiconductor layer containing no impurities, 55
．． 55': Carrier transport means, 7.57: Control means.
Claims (1)
れに近接し且不純物を含有する第２の半導体層とを少な
くとも有し、少なくとも前記不純物を含有する第２の半
導体層の存在と外部電界とに依存して、前記第１の半導
体層内に形成されるポテンシャルの井戸をキャリア移送
領域とする半導体装置であって、 前記不純物は前記第２の半導体層内に実質的に限定され
ていることを特徴とする半導体装置。[Scope of Claims] 1. At least a first semiconductor layer that does not substantially contain impurities and a second semiconductor layer that is adjacent to the first semiconductor layer and contains impurities, and a second semiconductor layer that contains at least the impurities. A semiconductor device in which a potential well formed in the first semiconductor layer is used as a carrier transport region depending on the presence of the semiconductor layer and an external electric field, wherein the impurity is contained in the second semiconductor layer. A semiconductor device characterized in that the semiconductor device is substantially limited to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8091487A JPS62271475A (en) | 1987-04-03 | 1987-04-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8091487A JPS62271475A (en) | 1987-04-03 | 1987-04-03 | Semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP966277A Division JPS5915388B2 (en) | 1977-02-02 | 1977-02-02 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62271475A true JPS62271475A (en) | 1987-11-25 |
Family
ID=13731661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8091487A Pending JPS62271475A (en) | 1987-04-03 | 1987-04-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62271475A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0430275A2 (en) * | 1989-12-01 | 1991-06-05 | Seiko Instruments Inc. | Doping method of barrier region in semiconductor device |
| JPH0582777A (en) * | 1991-09-24 | 1993-04-02 | Nec Corp | Mos type field effect transistor and its manufacture |
| US5366922A (en) * | 1989-12-06 | 1994-11-22 | Seiko Instruments Inc. | Method for producing CMOS transistor |
| US5514620A (en) * | 1989-12-01 | 1996-05-07 | Seiko Instruments Inc. | Method of producing PN junction device |
| US5527733A (en) * | 1989-07-27 | 1996-06-18 | Seiko Instruments Inc. | Impurity doping method with adsorbed diffusion source |
| US5532185A (en) * | 1991-03-27 | 1996-07-02 | Seiko Instruments Inc. | Impurity doping method with adsorbed diffusion source |
| US5753530A (en) * | 1992-04-21 | 1998-05-19 | Seiko Instruments, Inc. | Impurity doping method with diffusion source of boron-silicide film |
| US5874352A (en) * | 1989-12-06 | 1999-02-23 | Sieko Instruments Inc. | Method of producing MIS transistors having a gate electrode of matched conductivity type |
| US5925574A (en) * | 1989-12-01 | 1999-07-20 | Seiko Instruments Inc. | Method of producing a bipolar transistor |
| WO2004008512A1 (en) * | 2002-07-11 | 2004-01-22 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for manufacturing same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5395571A (en) * | 1977-02-02 | 1978-08-21 | Hitachi Ltd | Semiconductor device |
-
1987
- 1987-04-03 JP JP8091487A patent/JPS62271475A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5395571A (en) * | 1977-02-02 | 1978-08-21 | Hitachi Ltd | Semiconductor device |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5527733A (en) * | 1989-07-27 | 1996-06-18 | Seiko Instruments Inc. | Impurity doping method with adsorbed diffusion source |
| EP0430275A2 (en) * | 1989-12-01 | 1991-06-05 | Seiko Instruments Inc. | Doping method of barrier region in semiconductor device |
| US5338697A (en) * | 1989-12-01 | 1994-08-16 | Seiko Instruments Inc. | Doping method of barrier region in semiconductor device |
| US5514620A (en) * | 1989-12-01 | 1996-05-07 | Seiko Instruments Inc. | Method of producing PN junction device |
| US5925574A (en) * | 1989-12-01 | 1999-07-20 | Seiko Instruments Inc. | Method of producing a bipolar transistor |
| US5366922A (en) * | 1989-12-06 | 1994-11-22 | Seiko Instruments Inc. | Method for producing CMOS transistor |
| US5874352A (en) * | 1989-12-06 | 1999-02-23 | Sieko Instruments Inc. | Method of producing MIS transistors having a gate electrode of matched conductivity type |
| US5532185A (en) * | 1991-03-27 | 1996-07-02 | Seiko Instruments Inc. | Impurity doping method with adsorbed diffusion source |
| JPH0582777A (en) * | 1991-09-24 | 1993-04-02 | Nec Corp | Mos type field effect transistor and its manufacture |
| US5753530A (en) * | 1992-04-21 | 1998-05-19 | Seiko Instruments, Inc. | Impurity doping method with diffusion source of boron-silicide film |
| WO2004008512A1 (en) * | 2002-07-11 | 2004-01-22 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for manufacturing same |
| US7507999B2 (en) | 2002-07-11 | 2009-03-24 | Panasonic Corporation | Semiconductor device and method for manufacturing same |
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