JPS5935480A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5935480A JPS5935480A JP14737982A JP14737982A JPS5935480A JP S5935480 A JPS5935480 A JP S5935480A JP 14737982 A JP14737982 A JP 14737982A JP 14737982 A JP14737982 A JP 14737982A JP S5935480 A JPS5935480 A JP S5935480A
- Authority
- JP
- Japan
- Prior art keywords
- active layer
- layer
- recessed part
- film
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 12
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 229910045601 alloy Inorganic materials 0.000 abstract description 3
- 239000000956 alloy Substances 0.000 abstract description 3
- 230000001681 protective effect Effects 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract 2
- 239000012808 vapor phase Substances 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- MSWZFWKMSRAUBD-RSVSWTKNSA-N (3r,4s,5s,6r)-3-amino-6-(hydroxymethyl)oxane-2,4,5-triol Chemical compound N[C@H]1C(O)O[C@H](CO)[C@@H](O)[C@H]1O MSWZFWKMSRAUBD-RSVSWTKNSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
(al 発明の技術分野
本発明は半導体装置に係り、特にリセス構造のGaAs
電界効果型トランジスタ(FE′r)の構造に関する。DETAILED DESCRIPTION OF THE INVENTION (al) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly relates to a semiconductor device having a recessed structure.
This invention relates to the structure of a field effect transistor (FE'r).
(bl 従来技術と問題点
従来GaAs F E Tは、電気的特性の安定化の
ため、ソース及びドレイン電極形成後、素子表面に化学
気相成長法(CVD法)を用いて二酸化シリコン(5i
02 )膜或いは窒化シリコン−(Si3N4)膜のよ
うな絶縁膜を形成し、これを表面保護膜としていた。(bl) Conventional technology and problems Conventional GaAs FETs are made by depositing silicon dioxide (5i
02) film or an insulating film such as a silicon nitride (Si3N4) film was formed and used as a surface protection film.
ところが基板材料がGaAsのため、上記保護膜形成工
程を凡そ450(’C)以下の比較的低温において実施
しなければならい。従って形成された絶縁膜の膜質は完
全でなく、また上記絶縁膜とGaAs層との界面に多量
のトラップが存在する。そのためかかる従来のGaAs
F E Tにおいては、界面リーク電流やGaAs
1!表面の空乏化を生じるという問題があり、電気的特
性及び信頼度が必ずしも満足し得るとは言い難かった。However, since the substrate material is GaAs, the above protective film forming step must be performed at a relatively low temperature of approximately 450 ('C) or less. Therefore, the quality of the formed insulating film is not perfect, and a large number of traps exist at the interface between the insulating film and the GaAs layer. Therefore, conventional GaAs
In FET, interfacial leakage current and GaAs
1! There is a problem in that surface depletion occurs, and it cannot be said that the electrical characteristics and reliability are necessarily satisfactory.
tel 発明の目的
本発明の目的は上記問題点を解消して、改良された表面
保護膜を具備せるGaAs F E Tを提供するこ
とにある。tel OBJECT OF THE INVENTION An object of the present invention is to solve the above problems and provide a GaAs FET provided with an improved surface protection film.
+dl 発明の構成
本発明の特徴は、選択的に凹部が形成された半導体能動
層と、前記能動層の主面上に前記凹部を挟んで対向して
配設された一対のオーミック電極と、前記凹部内におい
て前記能動層とショットキ接触をなずゲート電極とを有
し、且つ前記能動層の主面の前記一対のオーミック電極
形成部を除く残りの領域が前記能動層の酸化物層により
被覆されてなることにある。+dl Structure of the Invention The features of the present invention include: a semiconductor active layer in which a recess is selectively formed; a pair of ohmic electrodes disposed on the main surface of the active layer to face each other across the recess; The recess has a gate electrode in Schottky contact with the active layer, and the remaining region of the main surface of the active layer excluding the pair of ohmic electrode forming portions is covered with an oxide layer of the active layer. It's about becoming.
(e) 発明の実施例
以下本発明の一実施例をその製造工程と共に、第1図〜
第6図を用いて説明する。(e) Embodiment of the Invention Below, an embodiment of the present invention, together with its manufacturing process, is shown in Figs.
This will be explained using FIG.
第1図において、1はGaAsよりなる半絶縁性基板、
2はノンドープのGaAsよりなるバッファ層、3はn
1GaAsよりなる能動層である。In FIG. 1, 1 is a semi-insulating substrate made of GaAs;
2 is a buffer layer made of non-doped GaAs, 3 is n
This is an active layer made of 1GaAs.
上記バッファ層2及び能動M3はいずれも半絶縁性基板
1上に液相エピタキシアル成長法により連続的に成長せ
しめる。上記バッファM2の厚さは例えば凡そ5〔μm
〕、能動層3の不純物濃度は例えば凡そI XIO(c
m’) 、厚さは例えば凡そ0.5〔μm〕としてよい
。Both the buffer layer 2 and the active M3 are continuously grown on the semi-insulating substrate 1 by liquid phase epitaxial growth. The thickness of the buffer M2 is approximately 5 μm, for example.
], the impurity concentration of the active layer 3 is approximately IXIO(c
m'), the thickness may be approximately 0.5 [μm], for example.
上述の如くエピタキシアル成長を終了した後、同図に示
すように金・ゲルマニウム/金(^uGe/Au)を、
能動層3の表面に選択的に被着せしめ、ソース電極4及
びドレイン電極5を形成する。After epitaxial growth is completed as described above, gold/germanium/gold (^uGe/Au) is grown as shown in the figure.
It is selectively deposited on the surface of the active layer 3 to form a source electrode 4 and a drain electrode 5.
次いで第2図に示す如く非酸化性雰囲気例えば窒素(N
2)中において凡そ450(’C)の温度で加熱処理を
施して、上記ソース電極4及びドレイン電極5と能動層
3とのアロイ層6を形成し、更に酸化性雰囲気例えば酸
素(02)と窒素(N2)との混合雰囲気中において、
凡そ400(”C)の温度で加熱処理を施すことにより
、上記ソース電極4及びドレイン電極5に被覆去れてい
る部分を除く残りの能動層の露出せる表面を酸化し、例
えば凡そ0.1〜0.2〔μm〕の厚さの酸化N7を形
成する。Next, as shown in FIG. 2, a non-oxidizing atmosphere such as nitrogen (N
2) Heat treatment is carried out at a temperature of approximately 450 ('C) in the interior to form an alloy layer 6 of the source electrode 4 and drain electrode 5 and the active layer 3, and further in an oxidizing atmosphere such as oxygen (02). In a mixed atmosphere with nitrogen (N2),
By performing heat treatment at a temperature of approximately 400°C, the exposed surface of the remaining active layer excluding the portions covered by the source electrode 4 and drain electrode 5 is oxidized, for example, at a temperature of approximately 0.1 to Form N7 oxide with a thickness of 0.2 [μm].
次いで第3図に示す如く上記酸化層8及びソース及びド
レイン電極上を含む基板1上全面に、例えばCVD法に
より、二酸化シリコン(SiO2)膜8を形成し、その
上に上記一対のオーミック電極の間に所定の開口10を
有するレジスト膜9を形成する。Next, as shown in FIG. 3, a silicon dioxide (SiO2) film 8 is formed on the entire surface of the substrate 1 including the oxide layer 8 and the source and drain electrodes by, for example, the CVD method, and the pair of ohmic electrodes are formed on the silicon dioxide (SiO2) film 8. A resist film 9 having a predetermined opening 10 therebetween is formed.
次いで第4図に示すように、上記レジスト膜9をマスク
として、まず5i02膜8を弗酸系の薬品を用いて選択
的に除去する。このときサイドエツチングにより 5i
02膜8の開口部寸法は図示した如くレジスト膜の開口
10より僅かに大きく形成される。この後、異方性エソ
チンダ液を用いて処理することにより、上記開口3部の
能動層3表面を選択的に除去し、能動層3表面に凹部1
1を形成する。ここで形成された四部11は、頂部の寸
法が前記5i02膜8の開口寸法と略等しくなる。Next, as shown in FIG. 4, using the resist film 9 as a mask, the 5i02 film 8 is first selectively removed using a hydrofluoric acid-based chemical. At this time, by side etching, 5i
The opening size of the 02 film 8 is formed to be slightly larger than the opening 10 of the resist film as shown. Thereafter, the surface of the active layer 3 at the openings 3 is selectively removed by treatment using an anisotropic ethotinda solution, and the recesses 1 are formed on the surface of the active layer 3.
form 1. The dimensions of the top portions of the four portions 11 formed here are approximately equal to the opening dimensions of the 5i02 film 8.
本工程において、能動層3の選択的除去に先立ち、第4
図に見られる如く、既に形成されている一対のオーミッ
ク電極4及び5表面にそれぞれ剣状導体12.12を接
触せしめ、両者間に電流6113を接続し、所定の電圧
を印加したときにこの電流計13に流れる電流を監視し
ながら上述の能動層3のエツチングを行えば、凹部11
底部に残留せしめる能動N14の厚さを正確に制御する
ことが出来る。In this step, prior to selective removal of the active layer 3, a fourth
As shown in the figure, sword-shaped conductors 12 and 12 are brought into contact with the surfaces of a pair of ohmic electrodes 4 and 5 that have already been formed, and a current 6113 is connected between them, and when a predetermined voltage is applied, this current If the above-described etching of the active layer 3 is performed while monitoring the current flowing through the total 13, the recess 11
The thickness of the active N14 remaining at the bottom can be precisely controlled.
即ち上述の電流はエツチングの進行と共に減少するので
、残留せしめる能動層14の厚さと電流値との相関を予
め調べておくことにより、上記制御を行うことが出来る
。That is, since the above-mentioned current decreases as etching progresses, the above-mentioned control can be performed by examining in advance the correlation between the thickness of the active layer 14 to be left and the current value.
このような制御方法は、当該エツチング工程を実施する
に際し、既にソース電極4及びドレイン電極5が存在す
ることにより、可能となるものである。Such a control method is possible because the source electrode 4 and drain electrode 5 are already present when performing the etching process.
次いで第5図に示す如く、アルミニウム(Al)を蒸着
法により被着せしめて、ゲート電極15を形成する。Next, as shown in FIG. 5, aluminum (Al) is deposited by vapor deposition to form a gate electrode 15.
この後第6図に示すように、凹部11の形成工程におい
てマスクとして用いた5i02 l!l!8 、 レ
ジスト膜9及びこのレジスト膜9上に被着せるAllN
13を除去して、本実施例の半導体装置の完成体が得ら
れる。本工程はリフトオフ法、即ち5i02INSを弗
酸系の薬品により除去することにより、その上に積層さ
れたレジスト膜9及びAj![15も同時に除去出来る
。After this, as shown in FIG. 6, 5i02l! was used as a mask in the process of forming the recess 11. l! 8. Resist film 9 and AllN deposited on this resist film 9
By removing 13, a completed semiconductor device of this example is obtained. This step is carried out using a lift-off method, that is, by removing 5i02INS with a hydrofluoric acid-based chemical, the resist film 9 and Aj! [15 can also be removed at the same time.
以上により得られた本実施例の半導体装置は、能動層3
の主面の、ソース電極4及びドレイン電極5が形成され
た部分を除く残りの部分は、能動層3を構成するGaA
sの酸化層6により被覆されている。この酸化層6は高
抵抗層であり且つ膜質を良好で、従来の3102膜やS
i3N4膜を用いた場合と異なり、界面リーク電流が大
幅に減少する。The semiconductor device of this example obtained as described above has an active layer 3
The remaining portion of the main surface of the active layer 3 except for the portion where the source electrode 4 and the drain electrode 5 are formed is made of GaA, which constitutes the active layer 3.
It is covered with an oxide layer 6 of s. This oxide layer 6 is a high resistance layer and has good film quality, compared to the conventional 3102 film or S
Unlike the case where an i3N4 film is used, the interfacial leakage current is significantly reduced.
従って半導体装置の電気的特性及び信頼度が向上する。Therefore, the electrical characteristics and reliability of the semiconductor device are improved.
(f) 発明の詳細
な説明した如く本発明により、界面リーク電流の少ない
良質の保護膜を表面に具備せるGaAsFETが提供さ
れる。(f) DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention provides a GaAsFET having a high-quality protective film on its surface with little interfacial leakage current.
第1図〜第6図は本発明の一実施例を製造工程と共に示
す要部断面図である。
図において、1はGaAsよりなる半絶縁性基板、2は
ノンドープのGaAsよりなるハソファ層、3はn型G
aAsよりなる能動層、4及び5はそれぞれソース電極
及びドレイン電極、6はアロイ屓、7はGa’Asの酸
化層、11は能動層表面に形成された凹部、14は上記
凹部11の底部に残留せしめた能動層、15は能動M1
4表面とショットキ接触を形成するゲート電極を示す。
法 派FIGS. 1 to 6 are sectional views of essential parts showing an embodiment of the present invention along with manufacturing steps. In the figure, 1 is a semi-insulating substrate made of GaAs, 2 is a haphazard layer made of undoped GaAs, and 3 is an n-type G
An active layer made of aAs, 4 and 5 are source and drain electrodes, respectively, 6 is an alloy layer, 7 is an oxide layer of Ga'As, 11 is a recess formed on the surface of the active layer, and 14 is at the bottom of the recess 11. The remaining active layer, 15 is active M1
4 shows the gate electrode forming a Schottky contact with the surface. Law school
Claims (1)
の主面上に前記四部を挟んで対向して配設された一対の
オーミック電極と、前記凹部内において前記能動層とシ
ョットキ接触をなすゲート電極とを有し、且つ前記能動
層の主面の前記一対のオーミック電極形成部を除く残り
の領域が前記能動層の酸化物層により被覆されてなるこ
とを特徴とする半導体装置。a semiconductor active layer in which a recess is selectively formed; a pair of ohmic electrodes disposed on the main surface of the active layer to face each other across the four parts; and a Schottky contact with the active layer within the recess. a gate electrode, and the remaining region of the main surface of the active layer other than the pair of ohmic electrode forming portions is covered with an oxide layer of the active layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14737982A JPS5935480A (en) | 1982-08-24 | 1982-08-24 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14737982A JPS5935480A (en) | 1982-08-24 | 1982-08-24 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5935480A true JPS5935480A (en) | 1984-02-27 |
Family
ID=15428906
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14737982A Pending JPS5935480A (en) | 1982-08-24 | 1982-08-24 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5935480A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01274477A (en) * | 1988-04-26 | 1989-11-02 | Fujitsu Ltd | Manufacture of semiconductor device |
JPH02165641A (en) * | 1988-12-20 | 1990-06-26 | Sanyo Electric Co Ltd | Manufacture of field effect transistor |
US5031006A (en) * | 1985-06-07 | 1991-07-09 | U.S. Philips Corp. | Semiconductor device having a Schottky decoupling diode |
-
1982
- 1982-08-24 JP JP14737982A patent/JPS5935480A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5031006A (en) * | 1985-06-07 | 1991-07-09 | U.S. Philips Corp. | Semiconductor device having a Schottky decoupling diode |
JPH01274477A (en) * | 1988-04-26 | 1989-11-02 | Fujitsu Ltd | Manufacture of semiconductor device |
JPH02165641A (en) * | 1988-12-20 | 1990-06-26 | Sanyo Electric Co Ltd | Manufacture of field effect transistor |
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