JPS60107867A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS60107867A JPS60107867A JP21397083A JP21397083A JPS60107867A JP S60107867 A JPS60107867 A JP S60107867A JP 21397083 A JP21397083 A JP 21397083A JP 21397083 A JP21397083 A JP 21397083A JP S60107867 A JPS60107867 A JP S60107867A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode
- fet
- gate electrode
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000013078 crystal Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 3
- 239000000969 carrier Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 13
- 239000002184 metal Substances 0.000 abstract description 13
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 12
- 239000011810 insulating material Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 239000007772 electrode material Substances 0.000 abstract description 3
- 229910052721 tungsten Inorganic materials 0.000 abstract description 3
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 239000010410 layer Substances 0.000 abstract 7
- 229910000676 Si alloy Inorganic materials 0.000 abstract 1
- 239000010953 base metal Substances 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 229910052750 molybdenum Inorganic materials 0.000 abstract 1
- 229910052697 platinum Inorganic materials 0.000 abstract 1
- 239000002344 surface layer Substances 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 229910008938 W—Si Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 210000000056 organ Anatomy 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 239000011669 selenium Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はＧａＡｓ−ＦＥＴとこれらを中心に集積した半
導体装置及びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a GaAs-FET, a semiconductor device mainly integrated with the GaAs-FET, and a method for manufacturing the same.
従来のＧａＡｓ−ＦＥ’Ｉ’は、第１図に示すように、
性能を向上するためにゲート電極２０とソース・ドレイ
ン領域１５がセルファラインで形成され、この間隔δ１
．δ２が１μｍ以下になるよう配慮されている。半絶縁
性Ｇ ａ Ａ ｓ基板結晶１ｏの所定位置にＳｉイオン
が打込まれｎ形ＧａＡｓ層１１となる。つぎにＷを主体
とした高融点金属のゲート電極２０をｎ影領域１１上に
加工する。つづいて高濃度のＳｉイオンを打込み、ゲー
ト電極２゜の周辺に低抵抗ｎ０形領域１５を形成する。The conventional GaAs-FE'I', as shown in FIG.
In order to improve performance, the gate electrode 20 and the source/drain regions 15 are formed with self-aligned lines, and this interval δ1
．． Consideration is given so that δ2 is 1 μm or less. Si ions are implanted into predetermined positions of the semi-insulating GaAs substrate crystal 1o to form an n-type GaAs layer 11. Next, a gate electrode 20 made of a high melting point metal mainly composed of W is processed on the n-shaded region 11. Subsequently, high concentration Si ions are implanted to form a low resistance n0 type region 15 around the gate electrode 2°.
この場合、ゲート電極２０の直下及びδ１．δ２領域（
これは、ホトレジパターンをゲート電極２ｏ上に残した
ま家打込むとできる領域）はｎ形のまま保持され、セル
ファラインによって０９形が加工される。つづいてイオ
ン打込みされた３ｉをＧａＡｓ中で活性化するために８
０００以上のアニールを施す。この場合、Ｗ系のゲート
電極２ｏはショットキ特性を保つ必要がある。つづいて
ＡＬＩＧｅ系のソース・ドレイン電極３０．３１を０９
形１５上に形成したプロセスを基本として素子が作られ
ている。このＰＥＴは、最大温度５ｏｏｃで処理するプ
ロセスが必要であるため、ゲート電極材の種類がＷ系に
限られていること、高温によってＧａＡｓと各種材質（
例えば８１０ｚ、Ｗ系など）の反応が起きやすくなシ、
これがＰＥＴ特性がばらつく原因の１つとして考えられ
ていること、イオン打込みでの００形のキャリア濃度は
〜１０１８コ／ｃｍ”以上にできないため、オーミック
接触抵抗、直列抵抗を極限まで小さくできない、などの
欠点が考えられていた。In this case, directly below the gate electrode 20 and δ1. δ2 region (
This is because the area (formed when the photoresist pattern is left on the gate electrode 2o) is kept as an n-type, and the 09 type is processed by the self-alignment. Next, in order to activate the ion-implanted 3i in GaAs, 8
000 or more is applied. In this case, the W-based gate electrode 2o needs to maintain Schottky characteristics. Next, add the ALIGe-based source/drain electrodes 30.31 to 09
The device is fabricated based on the process formed on Shape 15. This PET requires a process that processes at a maximum temperature of 5ooc, so the type of gate electrode material is limited to W-based materials.
For example, 810z, W series, etc.) reactions are likely to occur.
This is thought to be one of the causes of variations in PET properties, and because the carrier concentration of type 00 during ion implantation cannot be higher than ~1018 co/cm, ohmic contact resistance and series resistance cannot be minimized. disadvantages were considered.
本発明の目的は、従来のセル７アラインプロセスで８０
０Ｃの高温処理を必要とする工程にかわって、より低温
で処理できる製造法を提供し、新構造の半導体装置を提
供することにある。It is an object of the present invention to
The object of the present invention is to provide a manufacturing method that allows processing at a lower temperature instead of a process requiring high temperature processing at 0C, and to provide a semiconductor device with a new structure.
上記目的を達成するための本発明の構成は、ＰＥＴの能
動層上に高濃度からなるオーミック電極領域を選択的に
設けることにあろう
また、ゲート電極を形成後に、従来はｎ０形領域をイオ
ン打込みし、アニールして形成していた工程にかわって
、本発明ではｎ０形領域を結晶成長によって形成する工
程を特徴とする。結晶成長によるｎ９形層はＤＭＶＰＥ
法では成長温度の低温化限界として低圧ＣＶＤ技術を用
いて５５０〜６００Ｃであり、ＭＢＥ法では５００〜６
００Ｃである。またこの時のｎ形キャリア濃度としてＳ
ｅ（セレン）やＳ（いおう）を用いることにより１０′
８〜５×１０′９／ｃｒｎ３の範囲で制御できる。The structure of the present invention for achieving the above object is to selectively provide a high concentration ohmic electrode region on the active layer of PET.Furthermore, after forming the gate electrode, conventionally the n0 type region is ionized. In place of the step of forming the n0 type region by implantation and annealing, the present invention is characterized by a step of forming the n0 type region by crystal growth. The n9 type layer formed by crystal growth is DMVPE.
In the MBE method, the growth temperature limit is 550 to 600C using low pressure CVD technology, and 500 to 600C in the MBE method.
It is 00C. Also, the n-type carrier concentration at this time is S
10' by using e (selenium) and S (sulfur)
It can be controlled within the range of 8 to 5×10'9/crn3.
以下、本発明を実施例によって説明する。第２図は本発
明による一実施例のＧａＡｓ−ＦＥＴの断面図でおる。Hereinafter, the present invention will be explained by examples. FIG. 2 is a sectional view of a GaAs-FET according to an embodiment of the present invention.
半絶縁性Ｇ ａ Ａ ｓ基板結晶１０に選択的にｎ形Ｇ
ａＡｓ１１を形成し、同領域上にゲート電極２０を加工
する。絶縁材４１．４２を形成した後に、結晶成長によ
って０１形層１２を形成し、ソース・ドレイン電極３０
．３１を形成した主工程によ！Ｄ、ＦＥＴは構成されて
いる。ゲート電極２０の側面にある絶縁材４２はｎ０形
層とゲート電極２０の接触をさけるためにある。このＦ
ＥＴの製造方法を図３により説明する。半絶縁性基板結
晶１０にレジストパターン１を加工し、Ｓｉイオンを５
０ｋＶで〜１０Ｉ！コ／ｃｍ”打込む。つづいてレジス
トを除去したあと、８００Ｃで結晶を加熱してｎ形層１
１を形成する（ａ）。Ｗ−Ｓｉメタルをスパッタで被着
したのち、レジストノ（ターンでケート電極２０を加工
し、全面をＣＶＩｌｌ１８ｉ（ｈ膜３０００人で覆い、
のちレジストパターン２を加工する（ｂ）。つづいてＣ
Ｆ４系ガスを用いた異方性のプラズマエツチングによっ
て３＋０．膜を加工して、ｎ形層１１０表面一部を露出
する。この場合ゲート電極２０の側面には５ｉ０２膜４
２が残る（Ｃ）。レジスト２を除去したのち、ｎ０形Ｇ
ａ Ａ ｓ層１２を〜６００ＣのＯＭ （Ｏｒｇａｎ
ｉｃ Ｍｅｔａｌ ）−ＶＰＥ （Ｖｏｐｅｒ Ｐｈａ
ｓｅｌｉ：ｐｉｔａｘｙ ）法にヨッテ〜０６３μｍの
厚さに結晶成長する。この成長では、８ｉ０２やｗ−ｓ
ｉヅメタル上はＧａＡｓが成長できず、ｎ形ＧａＡｓ１
ｌ、ｈのみに〜１×１０Ｉ９コ／ｃｍ”の高濃度をもつ
ｎ３形層１２がえられる（ｄｉ、つぎＫＣＶＤ−８ｉ
０２ 膜を”３０００人被着したのち、リフトオフ法に
よってＡｕＧｅ系のオーミックメタルを形成し、ソース
・ドレイン電極３０．３１をを加工する。これによって
ＧａＡｓ−ＦＥＴの新構造がえられる。この構造ではゲ
ート電極２０とソース・ドレイン領域となるｎ１形Ｇ
ａ Ａ ８層１２がセル７アラインされ、第１図で示し
たδｌ、δ、が５ｉ（ｈ膜４２の０．３μｍで短間隔に
形成できた。Selectively injecting n-type G into the semi-insulating GaAs substrate crystal 10
AAs 11 is formed, and a gate electrode 20 is processed on the same region. After forming the insulating materials 41 and 42, the 01 type layer 12 is formed by crystal growth, and the source/drain electrodes 30 are formed.
．． By the main process that formed 31! D. FET is configured. The insulating material 42 on the side surface of the gate electrode 20 is provided to avoid contact between the n0 type layer and the gate electrode 20. This F
The method for manufacturing ET will be explained with reference to FIG. A resist pattern 1 is processed on a semi-insulating substrate crystal 10, and 5 Si ions are applied.
~10I at 0kV! After removing the resist, heat the crystal at 800C to form the n-type layer 1.
1 (a). After depositing W-Si metal by sputtering, the gate electrode 20 is processed using a resist layer (turn), and the entire surface is covered with a CVIll18i (h film of 3,000 layers).
Afterwards, the resist pattern 2 is processed (b). Continued by C
3+0. by anisotropic plasma etching using F4 gas. The film is processed to expose a portion of the surface of the n-type layer 110. In this case, a 5i02 film 4 is formed on the side surface of the gate electrode 20.
2 remains (C). After removing resist 2, n0 type G
aAs layer 12 is OM (Organ) at ~600C
ic Metal )-VPE (Voper Pha
Crystals are grown to a thickness of ~063 μm using the seli: pitaxy) method. With this growth, 8i02 and w-s
GaAs cannot grow on izu metal, and n-type GaAs1
An n3 type layer 12 with a high concentration of ~1×10I9/cm” is obtained only in l and h (di, then KCVD-8i
02 After 3,000 layers of film are deposited, an AuGe-based ohmic metal is formed using the lift-off method, and the source/drain electrodes 30 and 31 are processed. As a result, a new structure of GaAs-FET is obtained. n1 type G which becomes the gate electrode 20 and the source/drain region
a A The eight layers 12 were aligned in the cell 7, and δl and δ shown in FIG. 1 could be formed at short intervals of 5i (h at 0.3 μm of the film 42).
この発明による構造では（１）ｎ’形層の形成温度が〜
６００Ｃと低いので、ゲート電極２０と（ｊａＡｓの反
応がなくショットキ接合の性質は８００Ｃで処理するも
のよ多安定である。（２） ｒｌ ”形が高濃度で厚く
形成できるので、オーミック接触抵抗とｎ０形Ｑ ａ
Ａ ８直列抵抗は小さい（３）第１図と第２図を比較し
て明らかなように、本発明による構造の方がＩＣ，ＬＳ
Ｉ化にとってより平坦化でき、集積化しやすい、などの
特徴がある。ＯＭ−ＶＰＥ法によるＧａＡｓ成長層はウ
ェーハ内の厚さ、濃度の均一性がよく、イオン打込み技
術と対等の制御性がある。In the structure according to this invention, (1) the formation temperature of the n'-type layer is ~
Since the temperature is as low as 600C, there is no reaction between the gate electrode 20 (jaAs) and the properties of the Schottky junction are more stable than those processed at 800C. n0 type Q a
A 8 Series resistance is small (3) As is clear from comparing Figures 1 and 2, the structure according to the present invention is better for ICs and LSs.
It has the characteristics that it can be made more flat for integrated circuits and easier to integrate. The GaAs grown layer by the OM-VPE method has good uniformity in thickness and concentration within the wafer, and has controllability comparable to that of ion implantation technology.
本発明の他の実施例を第４図で説明する。半絶縁性Ｇａ
Ａｓ１ Ｏの一部にｎ形層１１を形成し、つづいてＷメ
タルのゲート電極２１を加工する。不要のＧ ａ Ａ
ｓ表面は８１０２膜４５で被覆し、ＯＭ−ＶＰＥにより
ｎ３形層１２を気相成長させる（ａ）。Another embodiment of the invention will be described with reference to FIG. Semi-insulating Ga
An n-type layer 11 is formed on a part of As1O, and then a gate electrode 21 of W metal is processed. Unnecessary G a A
The s surface is covered with an 8102 film 45, and the n3 type layer 12 is grown in vapor phase by OM-VPE (a).
この後、ＷがドライエッチできるＣ Ｆ ａ系ガスを用
いたプラズマエッチ装置により試料表面を削るとゲート
電極と００形層１２が間隔１００，１０１によって両者
は絶縁されてＦＥＴが形成される（ｂ）。After that, when the sample surface is etched using a plasma etching device using CFa-based gas that can dry-etch W, the gate electrode and the 00 type layer 12 are insulated by the gaps 100 and 101, forming an FET (b ).
この場合、両者を絶縁する手段としてあらかじめメタル
ゲートの表面に酸化膜の薄膜を形成したりｎ０形層Ｇａ
Ａｓを約０．１μｍ程度ウェットエッチすることも可能
である。In this case, as a means to insulate the two, a thin oxide film may be formed on the surface of the metal gate in advance, or an n0 type layer Ga
It is also possible to wet-etch As by about 0.1 μm.
本発明のさらに他の実施例を第５図で説明する。Still another embodiment of the present invention will be described with reference to FIG.
半絶縁性ＧａＡｓ１Ｏの一部にｎ形層１１を形成し、Ｍ
ｏ−５ｔのゲート電極２２とこの上面に８ｊＯｚの絶縁
膜２−５を形成する。不用のＧ ａ Ａ ｓ表面を８ｉ
０ｚ膜４６で被覆して、ＯＭ−ＶＰＥによりｎ１形層１
２を形成し、ＭＯ・Ｓｉをドライエッチにより２００，
２０１のサイドエッチを施す（ａ）。An n-type layer 11 is formed on a part of semi-insulating GaAs1O, and M
A gate electrode 22 of o-5t and an insulating film 2-5 of 8jOz are formed on its upper surface. 8i of unnecessary G a As surface
The n1 type layer 1 is coated with a 0z film 46 and formed by OM-VPE.
2 and dry etched MO/Si to 200,
Perform side etching of 201 (a).
このあとレジストのパターンを利用してＡ ｕ Ｑ ｅ
系のオーミックメタル３５，３６．３７をリフトオフで
形成しくｂ）、ゲート電極上についたメタル３６を、絶
縁膜２５の除去と共に取シ去って、ソース・ドレイン電
極３５．３７を形成する。この上に５ｌｏｚ膜４７を被
覆してＦＥＴがえられる（Ｃ）。ここで述べた構造では
ゲート電極２２に対して、ｎ０形層１２とソース・ドレ
イン電極３５．３７が共にセルファラインできる特長を
有する。After this, using the resist pattern, A u Q e
The ohmic metals 35, 36, 37 of the system are formed by lift-off b), and the metal 36 on the gate electrode is removed together with the removal of the insulating film 25, to form source/drain electrodes 35, 37. A FET is obtained by covering this with a 5loz film 47 (C). The structure described here has the feature that both the n0 type layer 12 and the source/drain electrodes 35 and 37 can be self-aligned with respect to the gate electrode 22.
本発明の製法によって、ゲート電極の材質を選定できる
領域が広がった。つまり従来、８００Ｃのアニールに対
してはＷとＷ−Ｓｔ金合金けが使用できるメタルでちっ
たが、処理温度を６００Ｃ近辺まで下げることで例えば
ＭＯ系メタルやＷ。The manufacturing method of the present invention has expanded the range in which the material of the gate electrode can be selected. In other words, conventionally, metals that can be used for annealing at 800C are W and W-St gold alloy, but by lowering the processing temperature to around 600C, for example, MO-based metal or W.
ＭＯをベースとしてｐｔ、Ａｕなどの低抵抗メタルの積
層膜でもプロセスに耐えて使える。これによって、ゲー
ト電極の低抵抗化を達成することができる。また高濃度
の０９形層であるため、従来のＡＵＧｅ合金系のオーミ
ック電極材にかわって、Ｎｉなど低マロイ温度で処理で
きるプロセスに改良できる特徴を有する。MO-based laminated films of low-resistance metals such as PT and Au can withstand the process and can be used. This makes it possible to reduce the resistance of the gate electrode. Moreover, since it is a highly concentrated 09 type layer, it has the characteristic that it can be improved to a process that can be processed at a low malloy temperature, such as Ni, in place of the conventional AUGe alloy-based ohmic electrode material.
ｎ０形ＧａＡｓ層の形成法は以上の実施例で述べた他に
ＭＢ Ｅ （Ｍｏ１ｅｃｕｌ、Ｉｒ ＢｅａＷ Ｅｐｉ
ｔａｘｙ ）、Ｌ Ｐ Ｅ （Ｌｉｑｕｉｄ Ｐｈａｓ
ｅ Ｅｐｉｔａｘｙ）法でｓつても本発明の趣旨を逸脱
するものではない。In addition to the method described in the above embodiments, the method for forming the n0 type GaAs layer may be
taxi), L P E (Liquid Phas
(Epitaxy) method does not depart from the spirit of the present invention.
第１図は従来のＧａＡｓ−ＦＥＴの断面図、第２図は本
発明の一実施例としてのＦＥＴの断面図、第３〜５図は
本発明の他の実施例としての製造工程を示す概略図であ
る。
１０ ・・・半絶縁性ＧａＡＳ、１１−・ｎ形ＧａＡｓ
、 １２・・・結晶成長で形成したｎ°形ＧａＡｓ、２
θ・・・ゲート電極、４０，４１．４２・・・絶縁材、
３０．３１第 １ 図
第 ２図
第３ 日
２
第４− 図
第５ 図
第１頁の続き
０発 明 者 柳 沢 寛 国分寺布［央研究所１
粗砥ケ窪１丁目２８幡地 株式会社日立製作所中勺Fig. 1 is a cross-sectional view of a conventional GaAs-FET, Fig. 2 is a cross-sectional view of an FET as an embodiment of the present invention, and Figs. 3 to 5 are schematic diagrams showing manufacturing steps as other embodiments of the present invention. It is a diagram. 10...Semi-insulating GaAS, 11-・n-type GaAs
, 12...n° type GaAs formed by crystal growth, 2
θ...gate electrode, 40, 41.42...insulating material,
30.31 Figure 1 Figure 2 Figure 3 Day 2 4- Figure 5 Continuation of Figure 1 page 0 Inventor Hiroshi Yanagisawa Kokubunjifu [Central Research Institute 1 Kotogakubo 1-28 Hatachi Co., Ltd. Hitachi, Ltd.
Claims (1)
いて能動層なる層上に高濃度からなるオーミック電極領
域層を選択的に設けたことを特徴とする半導体装置。 ２、ゲート電極を有する半導体結晶と、少なくとも上記
ゲート電極が結晶成長上の温度にショットキ特性が保持
される材質で構成され、ゲート電極を結晶成長時のマス
クとしてこの近傍に高濃度のキャリアをもつ半導体結晶
層を設けた工程を基本としてなる半導体装置の製法。[Scope of Claims] 1. A semiconductor device characterized in that a highly doped ohmic electrode region layer is selectively provided on an active layer of an FET consisting of a gate, source, and drain region. 2. A semiconductor crystal having a gate electrode, and at least the gate electrode made of a material that maintains Schottky characteristics at the temperature of crystal growth, and having a high concentration of carriers in the vicinity of the gate electrode as a mask during crystal growth. A method for manufacturing semiconductor devices that is based on a process in which a semiconductor crystal layer is provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58213970A JP2624642B2 (en) | 1983-11-16 | 1983-11-16 | Semiconductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58213970A JP2624642B2 (en) | 1983-11-16 | 1983-11-16 | Semiconductor device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60107867A true JPS60107867A (en) | 1985-06-13 |
| JP2624642B2 JP2624642B2 (en) | 1997-06-25 |
Family
ID=16648074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58213970A Expired - Lifetime JP2624642B2 (en) | 1983-11-16 | 1983-11-16 | Semiconductor device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2624642B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6230382A (en) * | 1985-04-12 | 1987-02-09 | Nec Corp | Manufacture of semiconductor device |
| JPS62200771A (en) * | 1986-02-28 | 1987-09-04 | Hitachi Ltd | Semiconductor device and manufacture thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58145162A (en) * | 1982-02-23 | 1983-08-29 | Nec Corp | Manufacture of semiconductor device |
| JPS58213970A (en) * | 1982-06-05 | 1983-12-13 | 日産自動車株式会社 | Check link support structure of door for automobile |
-
1983
- 1983-11-16 JP JP58213970A patent/JP2624642B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58145162A (en) * | 1982-02-23 | 1983-08-29 | Nec Corp | Manufacture of semiconductor device |
| JPS58213970A (en) * | 1982-06-05 | 1983-12-13 | 日産自動車株式会社 | Check link support structure of door for automobile |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6230382A (en) * | 1985-04-12 | 1987-02-09 | Nec Corp | Manufacture of semiconductor device |
| JPS62200771A (en) * | 1986-02-28 | 1987-09-04 | Hitachi Ltd | Semiconductor device and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2624642B2 (en) | 1997-06-25 |
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